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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;                                                              ;;
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;;                                                              ;;
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;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
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;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
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;; Distributed under terms of the GNU General Public License    ;;
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;; Distributed under terms of the GNU General Public License    ;;
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;;                                                              ;;
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;;                                                              ;;
- 
 
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;;  HT.inc                                                      ;;                                                    ;;
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;;                                                              ;;
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;;                                                              ;;
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;;  AMD HyperTransport bus control                              ;;
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;;  AMD HyperTransport bus control                              ;;
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;;                                                              ;;
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;;                                                              ;;
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;;                  art_zh                ;;
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;;                  art_zh                ;;
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;;                                                              ;;
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;;                                                              ;;
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;=============================================================================
 21 
;=============================================================================
21 
;
 22 
;
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; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
 23 
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
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;
 24 
;
24 
;=============================================================================
 25 
;=============================================================================
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 26 
 
- 
 
 27 
org $-OS_BASE	; physical addresses needed at initial stage
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 28 
 
25 
align 4
 29 
align 4
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 30 
 
27 
;------------------------------------------
 31 
;------------------------------------------
28 
;       params:   al = nbconfig register#
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;       params:   al = nbconfig register#
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;
 73 
;
70 
;***************************************************************************
 74 
;***************************************************************************
71 
align 4
 75 
align 4
72 
rs7xx_unlock_bar3:
 76 
rs7xx_unlock_bar3:
73 
	mov	eax, NB_MISC_INDEX
 77 
	mov	eax, NB_MISC_INDEX
74 
	mov	ebx, 0x080			; reg#0; write-enable
 78 
	mov	ebx, 0x080			; NBMISCIND:0x0; write-enable
75 
	call	rs7xx_nbconfig_write_pci	; set index
 79 
	call	rs7xx_nbconfig_write_pci	; set index
76 
	mov	eax, NB_MISC_DATA
 80 
	mov	eax, NB_MISC_DATA
77 
	call	rs7xx_nbconfig_read_pci 	; read data
 81 
	call	rs7xx_nbconfig_read_pci 	; read data
78 
	mov	ebx, eax
 82 
	mov	ebx, eax
79 
	and	ebx, 0xFFFFFFF7 		; clear bit3
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	and	ebx, 0xFFFFFFF7 		; clear bit3
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82 
	mov	eax, NB_MISC_INDEX
 86 
	mov	eax, NB_MISC_INDEX
83 
	xor	ebx, ebx			; reg#0; write-locked
 87 
	xor	ebx, ebx			; reg#0; write-locked
84 
	call	rs7xx_nbconfig_write_pci	; set index
 88 
	call	rs7xx_nbconfig_write_pci	; set index
85 
	ret
 89 
	ret
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 90 
 
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 91 
 
- 
 
 92 
 
- 
 
 93 
;***************************************************************************
- 
 
 94 
;   Function
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 95 
;      rs7xx_pcie_init:
- 
 
 96 
;
- 
 
 97 
;   Description
- 
 
 98 
;       PCIe extended (memory-mapped) config space detection
- 
 
 99 
;
- 
 
 100 
;***************************************************************************
- 
 
 101 
 
- 
 
 102 
align 4
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 103 
 
- 
 
 104 
rs7xx_pcie_init:
- 
 
 105 
	call	rs7xx_unlock_bar3
- 
 
 106 
	mov	al, 0x7C		       ; NB_IOC_CFG_CNTL
- 
 
 107 
	call	rs7xx_nbconfig_read_pci
- 
 
 108 
	mov	ebx, eax
- 
 
 109 
;       call    rs7xx_nbconfig_flush_pci
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 110 
	test	ebx, 0x20000000 		; BAR3 locked?
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 111 
	jz	$
- 
 
 112 
	mov	al, 0x84			; NB_PCI_ARB
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 113 
	call	rs7xx_nbconfig_read_pci
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 114 
	shr	eax,16
- 
 
 115 
	and	ax, 7				; the Bus range lays here:
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 116 
	jnz	@f
- 
 
 117 
	mov	ax, 8					; 1=2Mb,  2=4MB,  3=8MB,  4=16MB
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 118 
@@:
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 119 
	mov	word[PCIe_bus_range-OS_BASE], ax	; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb
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 120 
	mov	cl, al
- 
 
 121 
	call	rs7xx_nbconfig_flush_pci
- 
 
 122 
	dec	cl				; <4M ?
- 
 
 123 
	jz	@f
- 
 
 124 
	dec	cl				; one PDE needed anyway
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 125 
@@:
- 
 
 126 
	mov	ebx, 1
- 
 
 127 
	shl	ebx, cl
- 
 
 128 
	mov	word[mmio_pcie_cfg_pdes-OS_BASE], bx	; 1..64 PDE(s) needed,
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 129 
	shl	ebx, 22
- 
 
 130 
	mov	dword[mmio_pcie_cfg_lim-OS_BASE], ebx	; or 4..256Mb space to map
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 131 
	dec	dword[mmio_pcie_cfg_lim-OS_BASE]
- 
 
 132 
 
- 
 
 133 
	mov	al, 0x1C			; NB_BAR3_PCIEXP_MMCFG
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 134 
	call	rs7xx_nbconfig_read_pci
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 135 
	mov	ebx, eax
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 136 
	call	rs7xx_nbconfig_flush_pci
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 137 
	mov	eax, ebx
- 
 
 138 
	and	eax, 0xFFE00000 		; valid bits [31..21]
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 139 
	jz	$				; NB BAR3 may be invisible!
- 
 
 140 
.addr_found:
- 
 
 141 
	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; physical address (lower 32 bits)
- 
 
 142 
	add	dword[mmio_pcie_cfg_lim-OS_BASE],  eax
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 143 
 
- 
 
 144 
	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  by the way, UW is unsafe!
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 145 
	mov	ecx, PCIe_CONFIG_SPACE			; linear address
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 146 
	mov	ebx, ecx
- 
 
 147 
	shr	ebx, 20
- 
 
 148 
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
- 
 
 149 
	mov	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	; 1 page = 4M in address space
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 150 
	cmp	dl, 0x34	; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
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 151 
	jb	@f
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 152 
	mov	dl, 0x33
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 153 
	mov	byte[mmio_pcie_cfg_pdes-OS_BASE], dl
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 154 
@@:
- 
 
 155 
	xor	dx,  dx 			; PDEs counter
- 
 
 156 
.write_pde:
- 
 
 157 
	mov	dword[ebx], eax 		; map 4 buses
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 158 
	add	bx,  4				; new PDE
- 
 
 159 
	add	eax, 0x400000			; +4M phys.
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 160 
	add	ecx, 0x400000			; +4M lin.
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 161 
	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
- 
 
 162 
	jae	.pcie_cfg_mapped
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 163 
	inc	dl
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 164 
	jmp	.write_pde
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 165 
;        mov     eax, cr3
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 166 
;        mov     cr3, eax                        ; flush TLB
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 167 
.pcie_cfg_mapped:
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 168 
	ret	; <<< OK >>>
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 169 
 
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 170 
 
- 
 
 171 
; ================================================================================
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 172 
 
- 
 
 173 
org OS_BASE+$	; back to the linear address space
86 
 
 174 
 
87 
;--------------------------------------------------------------
 175 
;--------------------------------------------------------------
88 
align 4
 176 
align 4
89 
rs780_read_misc:
 177 
rs780_read_misc:
90 
;  in: eax(al) - reg#           out: eax = NBMISCIND data
 178 
;  in: eax(al) - reg#           out: eax = NBMISCIND data
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	pop	edx
 278 
	pop	edx
191 
	ret
 279 
	ret
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 - 
 
193 
 
 - 
 
194 
 
 - 
 
195 
;***************************************************************************
 - 
 
196 
;   Function
 - 
 
197 
;      rs7xx_pcie_init:
 - 
 
198 
;
 - 
 
199 
;   Description
 - 
 
200 
;       PCIe extended (memory-mapped) config space detection
 - 
 
201 
;
 - 
 
202 
;***************************************************************************
 - 
 
203 
 
 - 
 
204 
align 4
 - 
 
205 
 
 - 
 
206 
rs7xx_pcie_init:
 - 
 
207 
	call	rs7xx_unlock_bar3
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208 
	mov	al, 0x7C		       ; NB_IOC_CFG_CNTL
 - 
 
209 
	call	rs7xx_nbconfig_read_pci
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210 
	mov	ebx, eax
 - 
 
211 
	call	rs7xx_nbconfig_flush_pci
 - 
 
212 
	test	ebx, 0x20000000 		; BAR3 locked?
 - 
 
213 
	jz	.rs7xx_pcie_blocked
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214 
	mov	al, 0x84			; NB_PCI_ARB
 - 
 
215 
	call	rs7xx_nbconfig_read_pci
 - 
 
216 
	shr	eax,16
 - 
 
217 
	and	ax, 7				; the Bus range lays here:
 - 
 
218 
	jnz	@f
 - 
 
219 
	mov	ax, 8				; 1=2Mb,  2=4MB,  3=8MB,  4=16MB
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220 
@@:
 - 
 
221 
	mov	[PCIe_bus_range], ax		; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb
 - 
 
222 
	mov	cl, al
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223 
	call	rs7xx_nbconfig_flush_pci
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224 
	dec	cl				; <4M ?
 - 
 
225 
	jnz	@f
 - 
 
226 
	inc	cl				; one PDE needed anyway
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227 
@@:
 - 
 
228 
	dec	cl
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229 
	mov	ebx, 1
 - 
 
230 
	shl	ebx, cl
 - 
 
231 
	mov	[mmio_pcie_cfg_pdes], bx	; 1..64 PDE(s) needed,
 - 
 
232 
	shl	ebx, 22
 - 
 
233 
	mov	[mmio_pcie_cfg_lim], ebx	; or 4..256Mb space to map
 - 
 
234 
	dec	[mmio_pcie_cfg_lim]
 - 
 
235 
 
 - 
 
236 
	mov	al, 0x1C			; NB_BAR3_PCIEXP_MMCFG
 - 
 
237 
	call	rs7xx_nbconfig_read_pci
 - 
 
238 
	mov	ebx, eax
 - 
 
239 
	call	rs7xx_nbconfig_flush_pci
 - 
 
240 
	mov	eax, ebx
 - 
 
241 
	and	eax, 0xFFE00000 		; valid bits [31..21]
 - 
 
242 
	jz	.rs7xx_pcie_blocked		; NB BAR3 may be invisible!
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243 
						; try to get pcie ecfg address indirectly
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244 
.addr_found:
 - 
 
245 
	mov	[mmio_pcie_cfg_addr], eax	; physical address (lower 32 bits)
 - 
 
246 
	add	[mmio_pcie_cfg_lim],  eax
 - 
 
247 
 
 - 
 
248 
	or	eax, (PG_SHARED + PG_LARGE + PG_UW)  ;  by the way, UW is unsafe!
 - 
 
249 
	mov	ecx, PCIe_CONFIG_SPACE		; linear address
 - 
 
250 
	mov	ebx, ecx
 - 
 
251 
	shr	ebx, 20
 - 
 
252 
	add	ebx, sys_pgdir			; PgDir entry @
 - 
 
253 
	mov	dl, byte[mmio_pcie_cfg_pdes]	; 1 page = 4M in address space
 - 
 
254 
	cmp	dl, (USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4194304
 - 
 
255 
	jb	@f
 - 
 
256 
	mov	dl, ((USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4194304) - 1
 - 
 
257 
	mov	byte[mmio_pcie_cfg_pdes], dl
 - 
 
258 
@@:
 - 
 
259 
	xor	dx,  dx 			; PDEs counter
 - 
 
260 
@@:
 - 
 
261 
	mov	dword[ebx], eax 		; map 4 buses
 - 
 
262 
	add	bx,  4				; new PDE
 - 
 
263 
	add	eax, 0x400000			; +4M phys.
 - 
 
264 
	add	ecx, 0x400000			; +4M lin.
 - 
 
265 
	cmp	dl, byte[mmio_pcie_cfg_pdes]
 - 
 
266 
	jnc	.pcie_cfg_mapped
 - 
 
267 
	inc	dl
 - 
 
268 
	jmp	@b
 - 
 
269 
	mov	eax, cr3
 - 
 
270 
	mov	cr3, eax			; flush TLB
 - 
 
271 
.pcie_cfg_mapped:
 - 
 
272 
	mov	esi, boot_pcie_ok
 - 
 
273 
	call	boot_log
 - 
 
274 
	ret	; <<< OK >>>
 - 
 
275 
.rs7xx_pcie_fail:
 - 
 
276 
	mov	esi, boot_rs7xx_fail
 - 
 
277 
	call	boot_log
 - 
 
278 
	jmp	$
 - 
 
279 
.rs7xx_pcie_blocked:
 - 
 
280 
	mov	esi, boot_rs7xx_blkd
 - 
 
281 
	call	boot_log
 - 
 
282 
	jmp	$
 - 
 
283 

            -