WebSVN – Kolibri OS – Diff – /drivers/video/drm/vmwgfx/vmwgfx_fifo.c


/**************************************************************************
 *
 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/
#define mb()    asm volatile("mfence" : : : "memory")
#define rmb()   asm volatile("lfence" : : : "memory")
#define wmb()   asm volatile("sfence" : : : "memory")
 
#include "vmwgfx_drv.h"
#include 
#include 
 
#define TASK_INTERRUPTIBLE      1
#define TASK_UNINTERRUPTIBLE    2
 
bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t fifo_min, hwversion;
	const struct vmw_fifo_state *fifo = &dev_priv->fifo;
 
	if (!(dev_priv->capabilities & SVGA_CAP_3D))
		return false;
 
	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
		uint32_t result;
 
		if (!dev_priv->has_mob)
			return false;
 
		mutex_lock(&dev_priv->hw_mutex);
		vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
		result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
		mutex_unlock(&dev_priv->hw_mutex);
 
		return (result != 0);
	}
 
	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
		return false;
 
	fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
		return false;
 
	hwversion = ioread32(fifo_mem +
			     ((fifo->capabilities &
			       SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
			      SVGA_FIFO_3D_HWVERSION_REVISED :
			      SVGA_FIFO_3D_HWVERSION));
 
	if (hwversion == 0)
		return false;
 
	if (hwversion < SVGA3D_HWVERSION_WS8_B1)
		return false;
 
	/* Non-Screen Object path does not support surfaces */
	if (!dev_priv->sou_priv)
		return false;
 
	return true;
}
 
bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t caps;
 
	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
		return false;
 
	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
		return true;
 
	return false;
}
 
int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max;
	uint32_t min;
	uint32_t dummy;
 
 
 
	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
    fifo->static_buffer = KernelAlloc(fifo->static_buffer_size);
	if (unlikely(fifo->static_buffer == NULL))
		return -ENOMEM;
 
	fifo->dynamic_buffer = NULL;
	fifo->reserved_size = 0;
	fifo->using_bounce_buffer = false;
 
	mutex_init(&fifo->fifo_mutex);
//   init_rwsem(&fifo->rwsem);
 
	/*
	 * Allow mapping the first page read-only to user-space.
	 */
 
	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
 
	mutex_lock(&dev_priv->hw_mutex);
	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
 
	min = 4;
	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
		min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
	min <<= 2;
 
	if (min < PAGE_SIZE)
		min = PAGE_SIZE;
 
	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
    wmb();
	iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
	iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
    mb();
 
    vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
	mutex_unlock(&dev_priv->hw_mutex);
 
	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
 
	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
		 (unsigned int) max,
		 (unsigned int) min,
		 (unsigned int) fifo->capabilities);
 
	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
    vmw_marker_queue_init(&fifo->marker_queue);
 
    int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy);
 
    return ret;
}
 
void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 
	mutex_lock(&dev_priv->hw_mutex);
 
	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
		iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
		vmw_write(dev_priv, SVGA_REG_SYNC, reason);
	}
 
	mutex_unlock(&dev_priv->hw_mutex);
}
 
void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 
	mutex_lock(&dev_priv->hw_mutex);
 
	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
		vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 
	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
 
	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
		  dev_priv->config_done_state);
	vmw_write(dev_priv, SVGA_REG_ENABLE,
		  dev_priv->enable_state);
	vmw_write(dev_priv, SVGA_REG_TRACES,
		  dev_priv->traces_state);
 
	mutex_unlock(&dev_priv->hw_mutex);
	vmw_marker_queue_takedown(&fifo->marker_queue);
 
	if (likely(fifo->static_buffer != NULL)) {
		vfree(fifo->static_buffer);
		fifo->static_buffer = NULL;
	}
 
	if (likely(fifo->dynamic_buffer != NULL)) {
		vfree(fifo->dynamic_buffer);
		fifo->dynamic_buffer = NULL;
	}
}
 
static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 
	return ((max - next_cmd) + (stop - min) <= bytes);
}
 
static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
			       uint32_t bytes, bool interruptible,
			       unsigned long timeout)
{
	int ret = 0;
	unsigned long end_jiffies = jiffies + timeout;
//	DEFINE_WAIT(__wait);
 
	DRM_INFO("Fifo wait noirq.\n");
 
	for (;;) {
//       prepare_to_wait(&dev_priv->fifo_queue, &__wait,
//               (interruptible) ?
//               TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
		if (!vmw_fifo_is_full(dev_priv, bytes))
			break;
		if (time_after_eq(jiffies, end_jiffies)) {
			ret = -EBUSY;
			DRM_ERROR("SVGA device lockup.\n");
			break;
		}
        delay(1);
	}
//   finish_wait(&dev_priv->fifo_queue, &__wait);
	wake_up_all(&dev_priv->fifo_queue);
	DRM_INFO("Fifo noirq exit.\n");
	return ret;
}
 
static int vmw_fifo_wait(struct vmw_private *dev_priv,
			 uint32_t bytes, bool interruptible,
			 unsigned long timeout)
{
	long ret = 1L;
	unsigned long irq_flags;
 
	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
		return 0;
 
	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
		return vmw_fifo_wait_noirq(dev_priv, bytes,
					   interruptible, timeout);
 
	mutex_lock(&dev_priv->hw_mutex);
	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		outl(SVGA_IRQFLAG_FIFO_PROGRESS,
		     dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
		dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);
 
	if (interruptible)
		ret = wait_event_interruptible_timeout
		    (dev_priv->fifo_queue,
		     !vmw_fifo_is_full(dev_priv, bytes), timeout);
	else
		ret = wait_event_timeout
		    (dev_priv->fifo_queue,
		     !vmw_fifo_is_full(dev_priv, bytes), timeout);
 
	if (unlikely(ret == 0))
		ret = -EBUSY;
	else if (likely(ret > 0))
		ret = 0;
 
	mutex_lock(&dev_priv->hw_mutex);
	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);
 
	return ret;
}
 
/**
 * Reserve @bytes number of bytes in the fifo.
 *
 * This function will return NULL (error) on two conditions:
 *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 *   available fifo space.
 *
 * Returns:
 *   Pointer to the fifo, or null on error (possible hardware hang).
 */
void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max;
	uint32_t min;
	uint32_t next_cmd;
	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	int ret;
 
	mutex_lock(&fifo_state->fifo_mutex);
	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 
	if (unlikely(bytes >= (max - min)))
		goto out_err;
 
	BUG_ON(fifo_state->reserved_size != 0);
	BUG_ON(fifo_state->dynamic_buffer != NULL);
 
	fifo_state->reserved_size = bytes;
 
	while (1) {
		uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
		bool need_bounce = false;
		bool reserve_in_place = false;
 
		if (next_cmd >= stop) {
			if (likely((next_cmd + bytes < max ||
				    (next_cmd + bytes == max && stop > min))))
				reserve_in_place = true;
 
			else if (vmw_fifo_is_full(dev_priv, bytes)) {
				ret = vmw_fifo_wait(dev_priv, bytes,
						    false, 3 * HZ);
				if (unlikely(ret != 0))
					goto out_err;
			} else
				need_bounce = true;
 
		} else {
 
			if (likely((next_cmd + bytes < stop)))
				reserve_in_place = true;
			else {
				ret = vmw_fifo_wait(dev_priv, bytes,
						    false, 3 * HZ);
				if (unlikely(ret != 0))
					goto out_err;
			}
		}
 
		if (reserve_in_place) {
			if (reserveable || bytes <= sizeof(uint32_t)) {
				fifo_state->using_bounce_buffer = false;
 
				if (reserveable)
					iowrite32(bytes, fifo_mem +
						  SVGA_FIFO_RESERVED);
				return fifo_mem + (next_cmd >> 2);
			} else {
				need_bounce = true;
			}
		}
 
		if (need_bounce) {
			fifo_state->using_bounce_buffer = true;
			if (bytes < fifo_state->static_buffer_size)
				return fifo_state->static_buffer;
			else {
                fifo_state->dynamic_buffer = kmalloc(bytes,0);
				return fifo_state->dynamic_buffer;
			}
		}
	}
out_err:
	fifo_state->reserved_size = 0;
	mutex_unlock(&fifo_state->fifo_mutex);
	return NULL;
}
 
static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
			      __le32 __iomem *fifo_mem,
			      uint32_t next_cmd,
			      uint32_t max, uint32_t min, uint32_t bytes)
{
	uint32_t chunk_size = max - next_cmd;
	uint32_t rest;
	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	    fifo_state->dynamic_buffer : fifo_state->static_buffer;
 
 
 
	if (bytes < chunk_size)
		chunk_size = bytes;
 
	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
    mb();
    memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
	rest = bytes - chunk_size;
	if (rest)
        memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
			    rest);
 
 
}
 
static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
			       __le32 __iomem *fifo_mem,
			       uint32_t next_cmd,
			       uint32_t max, uint32_t min, uint32_t bytes)
{
	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	    fifo_state->dynamic_buffer : fifo_state->static_buffer;
 
 
	while (bytes > 0) {
		iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
		next_cmd += sizeof(uint32_t);
		if (unlikely(next_cmd == max))
			next_cmd = min;
		mb();
		iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
		mb();
		bytes -= sizeof(uint32_t);
	}
 
}
 
void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 
 
 
	BUG_ON((bytes & 3) != 0);
	BUG_ON(bytes > fifo_state->reserved_size);
 
	fifo_state->reserved_size = 0;
 
	if (fifo_state->using_bounce_buffer) {
		if (reserveable)
			vmw_fifo_res_copy(fifo_state, fifo_mem,
					  next_cmd, max, min, bytes);
		else
			vmw_fifo_slow_copy(fifo_state, fifo_mem,
					   next_cmd, max, min, bytes);
 
		if (fifo_state->dynamic_buffer) {
			vfree(fifo_state->dynamic_buffer);
			fifo_state->dynamic_buffer = NULL;
		}
 
	}
 
//   down_write(&fifo_state->rwsem);
	if (fifo_state->using_bounce_buffer || reserveable) {
		next_cmd += bytes;
		if (next_cmd >= max)
			next_cmd -= max - min;
		mb();
		iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	}
 
	if (reserveable)
		iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
    mb();
//   up_write(&fifo_state->rwsem);
	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
	mutex_unlock(&fifo_state->fifo_mutex);
 
 
}
 
int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	struct svga_fifo_cmd_fence *cmd_fence;
	void *fm;
	int ret = 0;
	uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
 
	fm = vmw_fifo_reserve(dev_priv, bytes);
	if (unlikely(fm == NULL)) {
		*seqno = atomic_read(&dev_priv->marker_seq);
		ret = -ENOMEM;
		(void)vmw_fallback_wait(dev_priv, false, true, *seqno,
					false, 3*HZ);
		goto out_err;
	}
 
	do {
		*seqno = atomic_add_return(1, &dev_priv->marker_seq);
	} while (*seqno == 0);
 
	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
 
		/*
		 * Don't request hardware to send a fence. The
		 * waiting code in vmwgfx_irq.c will emulate this.
		 */
 
		vmw_fifo_commit(dev_priv, 0);
		return 0;
	}
 
	*(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
	cmd_fence = (struct svga_fifo_cmd_fence *)
	    ((unsigned long)fm + sizeof(__le32));
 
	iowrite32(*seqno, &cmd_fence->fence);
	vmw_fifo_commit(dev_priv, bytes);
	(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
	vmw_update_seqno(dev_priv, fifo_state);
 
out_err:
	return ret;
}
 
/**
 * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
 * legacy query commands.
 *
 * @dev_priv: The device private structure.
 * @cid: The hardware context id used for the query.
 *
 * See the vmw_fifo_emit_dummy_query documentation.
 */
static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
			      uint32_t cid)
{
	/*
	 * A query wait without a preceding query end will
	 * actually finish all queries for this cid
	 * without writing to the query result structure.
	 */
 
	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	struct {
		SVGA3dCmdHeader header;
		SVGA3dCmdWaitForQuery body;
	} *cmd;
 
	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
 
	if (unlikely(cmd == NULL)) {
		DRM_ERROR("Out of fifo space for dummy query.\n");
		return -ENOMEM;
	}
 
	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
	cmd->header.size = sizeof(cmd->body);
	cmd->body.cid = cid;
	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
 
	if (bo->mem.mem_type == TTM_PL_VRAM) {
		cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
		cmd->body.guestResult.offset = bo->offset;
	} else {
		cmd->body.guestResult.gmrId = bo->mem.start;
		cmd->body.guestResult.offset = 0;
	}
 
	vmw_fifo_commit(dev_priv, sizeof(*cmd));
 
	return 0;
}
 
/**
 * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 * guest-backed resource query commands.
 *
 * @dev_priv: The device private structure.
 * @cid: The hardware context id used for the query.
 *
 * See the vmw_fifo_emit_dummy_query documentation.
 */
static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
					uint32_t cid)
{
	/*
	 * A query wait without a preceding query end will
	 * actually finish all queries for this cid
	 * without writing to the query result structure.
	 */
 
	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	struct {
		SVGA3dCmdHeader header;
		SVGA3dCmdWaitForGBQuery body;
	} *cmd;
 
	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
 
	if (unlikely(cmd == NULL)) {
		DRM_ERROR("Out of fifo space for dummy query.\n");
		return -ENOMEM;
	}
 
	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
	cmd->header.size = sizeof(cmd->body);
	cmd->body.cid = cid;
	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
	cmd->body.mobid = bo->mem.start;
	cmd->body.offset = 0;
 
	vmw_fifo_commit(dev_priv, sizeof(*cmd));
 
	return 0;
}
 
 
/**
 * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 * appropriate resource query commands.
 *
 * @dev_priv: The device private structure.
 * @cid: The hardware context id used for the query.
 *
 * This function is used to emit a dummy occlusion query with
 * no primitives rendered between query begin and query end.
 * It's used to provide a query barrier, in order to know that when
 * this query is finished, all preceding queries are also finished.
 *
 * A Query results structure should have been initialized at the start
 * of the dev_priv->dummy_query_bo buffer object. And that buffer object
 * must also be either reserved or pinned when this function is called.
 *
 * Returns -ENOMEM on failure to reserve fifo space.
 */
int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
			      uint32_t cid)
{
	if (dev_priv->has_mob)
		return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
 
	return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
}

Rev 4570	Rev 5078
1	/**************************************************************************	1	/**************************************************************************
2	*	2	*
3	* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA	3	* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4	* All Rights Reserved.	4	* All Rights Reserved.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the	7	* copy of this software and associated documentation files (the
8	* "Software"), to deal in the Software without restriction, including	8	* "Software"), to deal in the Software without restriction, including
9	* without limitation the rights to use, copy, modify, merge, publish,	9	* without limitation the rights to use, copy, modify, merge, publish,
10	* distribute, sub license, and/or sell copies of the Software, and to	10	* distribute, sub license, and/or sell copies of the Software, and to
11	* permit persons to whom the Software is furnished to do so, subject to	11	* permit persons to whom the Software is furnished to do so, subject to
12	* the following conditions:	12	* the following conditions:
13	*	13	*
14	* The above copyright notice and this permission notice (including the	14	* The above copyright notice and this permission notice (including the
15	* next paragraph) shall be included in all copies or substantial portions	15	* next paragraph) shall be included in all copies or substantial portions
16	* of the Software.	16	* of the Software.
17	*	17	*
18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24	* USE OR OTHER DEALINGS IN THE SOFTWARE.	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
25	*	25	*
26	**************************************************************************/	26	**************************************************************************/
27	#define mb() asm volatile("mfence" : : : "memory")	27	#define mb() asm volatile("mfence" : : : "memory")
28	#define rmb() asm volatile("lfence" : : : "memory")	28	#define rmb() asm volatile("lfence" : : : "memory")
29	#define wmb() asm volatile("sfence" : : : "memory")	29	#define wmb() asm volatile("sfence" : : : "memory")
30		30
31	#include "vmwgfx_drv.h"	31	#include "vmwgfx_drv.h"
32	#include	32	#include
33	#include	33	#include
34		34
35	#define TASK_INTERRUPTIBLE 1	35	#define TASK_INTERRUPTIBLE 1
36	#define TASK_UNINTERRUPTIBLE 2	36	#define TASK_UNINTERRUPTIBLE 2
37		37
38	bool vmw_fifo_have_3d(struct vmw_private *dev_priv)	38	bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
39	{	39	{
40	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;	40	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
41	uint32_t fifo_min, hwversion;	41	uint32_t fifo_min, hwversion;
42	const struct vmw_fifo_state *fifo = &dev_priv->fifo;	42	const struct vmw_fifo_state *fifo = &dev_priv->fifo;
43		43
44	if (!(dev_priv->capabilities & SVGA_CAP_3D))	44	if (!(dev_priv->capabilities & SVGA_CAP_3D))
45	return false;	45	return false;
46		46
47	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {	47	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
48	uint32_t result;	48	uint32_t result;
49		49
50	if (!dev_priv->has_mob)	50	if (!dev_priv->has_mob)
51	return false;	51	return false;
52		52
53	mutex_lock(&dev_priv->hw_mutex);	53	mutex_lock(&dev_priv->hw_mutex);
54	vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);	54	vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
55	result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);	55	result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
56	mutex_unlock(&dev_priv->hw_mutex);	56	mutex_unlock(&dev_priv->hw_mutex);
57		57
58	return (result != 0);	58	return (result != 0);
59	}	59	}
60		60
61	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))	61	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
62	return false;	62	return false;
63		63
64	fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);	64	fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);
65	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))	65	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
66	return false;	66	return false;
67		67
68	hwversion = ioread32(fifo_mem +	68	hwversion = ioread32(fifo_mem +
69	((fifo->capabilities &	69	((fifo->capabilities &
70	SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?	70	SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
71	SVGA_FIFO_3D_HWVERSION_REVISED :	71	SVGA_FIFO_3D_HWVERSION_REVISED :
72	SVGA_FIFO_3D_HWVERSION));	72	SVGA_FIFO_3D_HWVERSION));
73		73
74	if (hwversion == 0)	74	if (hwversion == 0)
75	return false;	75	return false;
76		76
77	if (hwversion < SVGA3D_HWVERSION_WS8_B1)	77	if (hwversion < SVGA3D_HWVERSION_WS8_B1)
78	return false;	78	return false;
79		79
80	/* Non-Screen Object path does not support surfaces */	80	/* Non-Screen Object path does not support surfaces */
81	if (!dev_priv->sou_priv)	81	if (!dev_priv->sou_priv)
82	return false;	82	return false;
83		83
84	return true;	84	return true;
85	}	85	}
86		86
87	bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)	87	bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
88	{	88	{
89	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;	89	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
90	uint32_t caps;	90	uint32_t caps;
91		91
92	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))	92	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
93	return false;	93	return false;
94		94
95	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);	95	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
96	if (caps & SVGA_FIFO_CAP_PITCHLOCK)	96	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
97	return true;	97	return true;
98		98
99	return false;	99	return false;
100	}	100	}
101		101
102	int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo)	102	int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
103	{	103	{
104	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;	104	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
105	uint32_t max;	105	uint32_t max;
106	uint32_t min;	106	uint32_t min;
107	uint32_t dummy;	107	uint32_t dummy;
108		-
109	ENTER();	-
110		108
111	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;	109	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
112	fifo->static_buffer = KernelAlloc(fifo->static_buffer_size);	110	fifo->static_buffer = KernelAlloc(fifo->static_buffer_size);
113	if (unlikely(fifo->static_buffer == NULL))	111	if (unlikely(fifo->static_buffer == NULL))
114	return -ENOMEM;	112	return -ENOMEM;
115		113
116	fifo->dynamic_buffer = NULL;	114	fifo->dynamic_buffer = NULL;
117	fifo->reserved_size = 0;	115	fifo->reserved_size = 0;
118	fifo->using_bounce_buffer = false;	116	fifo->using_bounce_buffer = false;
119		117
120	mutex_init(&fifo->fifo_mutex);	118	mutex_init(&fifo->fifo_mutex);
121	// init_rwsem(&fifo->rwsem);	119	// init_rwsem(&fifo->rwsem);
122		120
123	/*	121	/*
124	* Allow mapping the first page read-only to user-space.	122	* Allow mapping the first page read-only to user-space.
125	*/	123	*/
126		124
127	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));	125	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
128	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));	126	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
129	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));	127	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
130		128
131	mutex_lock(&dev_priv->hw_mutex);	129	mutex_lock(&dev_priv->hw_mutex);
132	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);	130	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
133	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);	131	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
134	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);	132	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
135	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);	133	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
136		134
137	min = 4;	135	min = 4;
138	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)	136	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
139	min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);	137	min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
140	min <<= 2;	138	min <<= 2;
141		139
142	if (min < PAGE_SIZE)	140	if (min < PAGE_SIZE)
143	min = PAGE_SIZE;	141	min = PAGE_SIZE;
144		142
145	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);	143	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
146	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);	144	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
147	wmb();	145	wmb();
148	iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD);	146	iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
149	iowrite32(min, fifo_mem + SVGA_FIFO_STOP);	147	iowrite32(min, fifo_mem + SVGA_FIFO_STOP);
150	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);	148	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
151	mb();	149	mb();
152		150
153	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);	151	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
154	mutex_unlock(&dev_priv->hw_mutex);	152	mutex_unlock(&dev_priv->hw_mutex);
155		153
156	max = ioread32(fifo_mem + SVGA_FIFO_MAX);	154	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
157	min = ioread32(fifo_mem + SVGA_FIFO_MIN);	155	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
158	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);	156	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
159		157
160	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",	158	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
161	(unsigned int) max,	159	(unsigned int) max,
162	(unsigned int) min,	160	(unsigned int) min,
163	(unsigned int) fifo->capabilities);	161	(unsigned int) fifo->capabilities);
164		162
165	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);	163	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
166	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);	164	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
167	vmw_marker_queue_init(&fifo->marker_queue);	165	vmw_marker_queue_init(&fifo->marker_queue);
168		166
169	int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy);	167	int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy);
170	LEAVE();	-
171	return ret;	168	return ret;
172	}	169	}
173		170
174	void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)	171	void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
175	{	172	{
176	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;	173	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
177		174
178	mutex_lock(&dev_priv->hw_mutex);	175	mutex_lock(&dev_priv->hw_mutex);
179		176
180	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {	177	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
181	iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);	178	iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
182	vmw_write(dev_priv, SVGA_REG_SYNC, reason);	179	vmw_write(dev_priv, SVGA_REG_SYNC, reason);
183	}	180	}
184		181
185	mutex_unlock(&dev_priv->hw_mutex);	182	mutex_unlock(&dev_priv->hw_mutex);
186	}	183	}
187		184
188	void vmw_fifo_release(struct vmw_private dev_priv, struct vmw_fifo_state fifo)	185	void vmw_fifo_release(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
189	{	186	{
190	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;	187	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
191		188
192	mutex_lock(&dev_priv->hw_mutex);	189	mutex_lock(&dev_priv->hw_mutex);
193		190
194	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)	191	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
195	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);	192	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
196		193
197	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);	194	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
198		195
199	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,	196	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
200	dev_priv->config_done_state);	197	dev_priv->config_done_state);
201	vmw_write(dev_priv, SVGA_REG_ENABLE,	198	vmw_write(dev_priv, SVGA_REG_ENABLE,
202	dev_priv->enable_state);	199	dev_priv->enable_state);
203	vmw_write(dev_priv, SVGA_REG_TRACES,	200	vmw_write(dev_priv, SVGA_REG_TRACES,
204	dev_priv->traces_state);	201	dev_priv->traces_state);
205		202
206	mutex_unlock(&dev_priv->hw_mutex);	203	mutex_unlock(&dev_priv->hw_mutex);
207	vmw_marker_queue_takedown(&fifo->marker_queue);	204	vmw_marker_queue_takedown(&fifo->marker_queue);
208		205
209	if (likely(fifo->static_buffer != NULL)) {	206	if (likely(fifo->static_buffer != NULL)) {
210	vfree(fifo->static_buffer);	207	vfree(fifo->static_buffer);
211	fifo->static_buffer = NULL;	208	fifo->static_buffer = NULL;
212	}	209	}
213		210
214	if (likely(fifo->dynamic_buffer != NULL)) {	211	if (likely(fifo->dynamic_buffer != NULL)) {
215	vfree(fifo->dynamic_buffer);	212	vfree(fifo->dynamic_buffer);
216	fifo->dynamic_buffer = NULL;	213	fifo->dynamic_buffer = NULL;
217	}	214	}
218	}	215	}
219		216
220	static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)	217	static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
221	{	218	{
222	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;	219	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
223	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);	220	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
224	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);	221	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
225	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);	222	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
226	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);	223	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
227		224
228	return ((max - next_cmd) + (stop - min) <= bytes);	225	return ((max - next_cmd) + (stop - min) <= bytes);
229	}	226	}
230		227
231	static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,	228	static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
232	uint32_t bytes, bool interruptible,	229	uint32_t bytes, bool interruptible,
233	unsigned long timeout)	230	unsigned long timeout)
234	{	231	{
235	int ret = 0;	232	int ret = 0;
236	unsigned long end_jiffies = GetTimerTicks() + timeout;	233	unsigned long end_jiffies = jiffies + timeout;
237	// DEFINE_WAIT(__wait);	234	// DEFINE_WAIT(__wait);
238		235
239	DRM_INFO("Fifo wait noirq.\n");	236	DRM_INFO("Fifo wait noirq.\n");
240		237
241	for (;;) {	238	for (;;) {
242	// prepare_to_wait(&dev_priv->fifo_queue, &__wait,	239	// prepare_to_wait(&dev_priv->fifo_queue, &__wait,
243	// (interruptible) ?	240	// (interruptible) ?
244	// TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);	241	// TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
245	if (!vmw_fifo_is_full(dev_priv, bytes))	242	if (!vmw_fifo_is_full(dev_priv, bytes))
246	break;	243	break;
247	if (time_after_eq(GetTimerTicks(), end_jiffies)) {	244	if (time_after_eq(jiffies, end_jiffies)) {
248	ret = -EBUSY;	245	ret = -EBUSY;
249	DRM_ERROR("SVGA device lockup.\n");	246	DRM_ERROR("SVGA device lockup.\n");
250	break;	247	break;
251	}	248	}
252	delay(1);	249	delay(1);
253	}	250	}
254	// finish_wait(&dev_priv->fifo_queue, &__wait);	251	// finish_wait(&dev_priv->fifo_queue, &__wait);
255	wake_up_all(&dev_priv->fifo_queue);	252	wake_up_all(&dev_priv->fifo_queue);
256	DRM_INFO("Fifo noirq exit.\n");	253	DRM_INFO("Fifo noirq exit.\n");
257	return ret;	254	return ret;
258	}	255	}
259		256
260	static int vmw_fifo_wait(struct vmw_private *dev_priv,	257	static int vmw_fifo_wait(struct vmw_private *dev_priv,
261	uint32_t bytes, bool interruptible,	258	uint32_t bytes, bool interruptible,
262	unsigned long timeout)	259	unsigned long timeout)
263	{	260	{
264	long ret = 1L;	261	long ret = 1L;
265	unsigned long irq_flags;	262	unsigned long irq_flags;
266		263
267	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))	264	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
268	return 0;	265	return 0;
269		266
270	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);	267	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
271	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))	268	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
272	return vmw_fifo_wait_noirq(dev_priv, bytes,	269	return vmw_fifo_wait_noirq(dev_priv, bytes,
273	interruptible, timeout);	270	interruptible, timeout);
274		271
275	mutex_lock(&dev_priv->hw_mutex);	272	mutex_lock(&dev_priv->hw_mutex);
276	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {	273	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
277	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);	274	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
278	outl(SVGA_IRQFLAG_FIFO_PROGRESS,	275	outl(SVGA_IRQFLAG_FIFO_PROGRESS,
279	dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);	276	dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
280	dev_priv->irq_mask \|= SVGA_IRQFLAG_FIFO_PROGRESS;	277	dev_priv->irq_mask \|= SVGA_IRQFLAG_FIFO_PROGRESS;
281	vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);	278	vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
282	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);	279	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
283	}	280	}
284	mutex_unlock(&dev_priv->hw_mutex);	281	mutex_unlock(&dev_priv->hw_mutex);
285		282
286	if (interruptible)	283	if (interruptible)
287	ret = wait_event_interruptible_timeout	284	ret = wait_event_interruptible_timeout
288	(dev_priv->fifo_queue,	285	(dev_priv->fifo_queue,
289	!vmw_fifo_is_full(dev_priv, bytes), timeout);	286	!vmw_fifo_is_full(dev_priv, bytes), timeout);
290	else	287	else
291	ret = wait_event_timeout	288	ret = wait_event_timeout
292	(dev_priv->fifo_queue,	289	(dev_priv->fifo_queue,
293	!vmw_fifo_is_full(dev_priv, bytes), timeout);	290	!vmw_fifo_is_full(dev_priv, bytes), timeout);
294		291
295	if (unlikely(ret == 0))	292	if (unlikely(ret == 0))
296	ret = -EBUSY;	293	ret = -EBUSY;
297	else if (likely(ret > 0))	294	else if (likely(ret > 0))
298	ret = 0;	295	ret = 0;
299		296
300	mutex_lock(&dev_priv->hw_mutex);	297	mutex_lock(&dev_priv->hw_mutex);
301	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {	298	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
302	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);	299	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
303	dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;	300	dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
304	vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);	301	vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
305	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);	302	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
306	}	303	}
307	mutex_unlock(&dev_priv->hw_mutex);	304	mutex_unlock(&dev_priv->hw_mutex);
308		305
309	return ret;	306	return ret;
310	}	307	}
311		308
312	/**	309	/**
313	* Reserve @bytes number of bytes in the fifo.	310	* Reserve @bytes number of bytes in the fifo.
314	*	311	*
315	* This function will return NULL (error) on two conditions:	312	* This function will return NULL (error) on two conditions:
316	* If it timeouts waiting for fifo space, or if @bytes is larger than the	313	* If it timeouts waiting for fifo space, or if @bytes is larger than the
317	* available fifo space.	314	* available fifo space.
318	*	315	*
319	* Returns:	316	* Returns:
320	* Pointer to the fifo, or null on error (possible hardware hang).	317	* Pointer to the fifo, or null on error (possible hardware hang).
321	*/	318	*/
322	void vmw_fifo_reserve(struct vmw_private dev_priv, uint32_t bytes)	319	void vmw_fifo_reserve(struct vmw_private dev_priv, uint32_t bytes)
323	{	320	{
324	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;	321	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
325	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;	322	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
326	uint32_t max;	323	uint32_t max;
327	uint32_t min;	324	uint32_t min;
328	uint32_t next_cmd;	325	uint32_t next_cmd;
329	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;	326	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
330	int ret;	327	int ret;
331		328
332	mutex_lock(&fifo_state->fifo_mutex);	329	mutex_lock(&fifo_state->fifo_mutex);
333	max = ioread32(fifo_mem + SVGA_FIFO_MAX);	330	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
334	min = ioread32(fifo_mem + SVGA_FIFO_MIN);	331	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
335	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);	332	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
336		333
337	if (unlikely(bytes >= (max - min)))	334	if (unlikely(bytes >= (max - min)))
338	goto out_err;	335	goto out_err;
339		336
340	BUG_ON(fifo_state->reserved_size != 0);	337	BUG_ON(fifo_state->reserved_size != 0);
341	BUG_ON(fifo_state->dynamic_buffer != NULL);	338	BUG_ON(fifo_state->dynamic_buffer != NULL);
342		339
343	fifo_state->reserved_size = bytes;	340	fifo_state->reserved_size = bytes;
344		341
345	while (1) {	342	while (1) {
346	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);	343	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
347	bool need_bounce = false;	344	bool need_bounce = false;
348	bool reserve_in_place = false;	345	bool reserve_in_place = false;
349		346
350	if (next_cmd >= stop) {	347	if (next_cmd >= stop) {
351	if (likely((next_cmd + bytes < max \|\|	348	if (likely((next_cmd + bytes < max \|\|
352	(next_cmd + bytes == max && stop > min))))	349	(next_cmd + bytes == max && stop > min))))
353	reserve_in_place = true;	350	reserve_in_place = true;
354		351
355	else if (vmw_fifo_is_full(dev_priv, bytes)) {	352	else if (vmw_fifo_is_full(dev_priv, bytes)) {
356	ret = vmw_fifo_wait(dev_priv, bytes,	353	ret = vmw_fifo_wait(dev_priv, bytes,
357	false, 3 * HZ);	354	false, 3 * HZ);
358	if (unlikely(ret != 0))	355	if (unlikely(ret != 0))
359	goto out_err;	356	goto out_err;
360	} else	357	} else
361	need_bounce = true;	358	need_bounce = true;
362		359
363	} else {	360	} else {
364		361
365	if (likely((next_cmd + bytes < stop)))	362	if (likely((next_cmd + bytes < stop)))
366	reserve_in_place = true;	363	reserve_in_place = true;
367	else {	364	else {
368	ret = vmw_fifo_wait(dev_priv, bytes,	365	ret = vmw_fifo_wait(dev_priv, bytes,
369	false, 3 * HZ);	366	false, 3 * HZ);
370	if (unlikely(ret != 0))	367	if (unlikely(ret != 0))
371	goto out_err;	368	goto out_err;
372	}	369	}
373	}	370	}
374		371
375	if (reserve_in_place) {	372	if (reserve_in_place) {
376	if (reserveable \|\| bytes <= sizeof(uint32_t)) {	373	if (reserveable \|\| bytes <= sizeof(uint32_t)) {
377	fifo_state->using_bounce_buffer = false;	374	fifo_state->using_bounce_buffer = false;
378		375
379	if (reserveable)	376	if (reserveable)
380	iowrite32(bytes, fifo_mem +	377	iowrite32(bytes, fifo_mem +
381	SVGA_FIFO_RESERVED);	378	SVGA_FIFO_RESERVED);
382	return fifo_mem + (next_cmd >> 2);	379	return fifo_mem + (next_cmd >> 2);
383	} else {	380	} else {
384	need_bounce = true;	381	need_bounce = true;
385	}	382	}
386	}	383	}
387		384
388	if (need_bounce) {	385	if (need_bounce) {
389	fifo_state->using_bounce_buffer = true;	386	fifo_state->using_bounce_buffer = true;
390	if (bytes < fifo_state->static_buffer_size)	387	if (bytes < fifo_state->static_buffer_size)
391	return fifo_state->static_buffer;	388	return fifo_state->static_buffer;
392	else {	389	else {
393	fifo_state->dynamic_buffer = kmalloc(bytes,0);	390	fifo_state->dynamic_buffer = kmalloc(bytes,0);
394	return fifo_state->dynamic_buffer;	391	return fifo_state->dynamic_buffer;
395	}	392	}
396	}	393	}
397	}	394	}
398	out_err:	395	out_err:
399	fifo_state->reserved_size = 0;	396	fifo_state->reserved_size = 0;
400	mutex_unlock(&fifo_state->fifo_mutex);	397	mutex_unlock(&fifo_state->fifo_mutex);
401	return NULL;	398	return NULL;
402	}	399	}
403		400
404	static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,	401	static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
405	__le32 __iomem *fifo_mem,	402	__le32 __iomem *fifo_mem,
406	uint32_t next_cmd,	403	uint32_t next_cmd,
407	uint32_t max, uint32_t min, uint32_t bytes)	404	uint32_t max, uint32_t min, uint32_t bytes)
408	{	405	{
409	uint32_t chunk_size = max - next_cmd;	406	uint32_t chunk_size = max - next_cmd;
410	uint32_t rest;	407	uint32_t rest;
411	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?	408	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
412	fifo_state->dynamic_buffer : fifo_state->static_buffer;	409	fifo_state->dynamic_buffer : fifo_state->static_buffer;
413		-
414	ENTER();	-
415		410
416	if (bytes < chunk_size)	411	if (bytes < chunk_size)
417	chunk_size = bytes;	412	chunk_size = bytes;
418		413
419	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);	414	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
420	mb();	415	mb();
421	memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);	416	memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
422	rest = bytes - chunk_size;	417	rest = bytes - chunk_size;
423	if (rest)	418	if (rest)
424	memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),	419	memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
425	rest);	420	rest);
426	LEAVE();	-
427		-
428	}	421	}
429		422
430	static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,	423	static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
431	__le32 __iomem *fifo_mem,	424	__le32 __iomem *fifo_mem,
432	uint32_t next_cmd,	425	uint32_t next_cmd,
433	uint32_t max, uint32_t min, uint32_t bytes)	426	uint32_t max, uint32_t min, uint32_t bytes)
434	{	427	{
435	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?	428	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
436	fifo_state->dynamic_buffer : fifo_state->static_buffer;	429	fifo_state->dynamic_buffer : fifo_state->static_buffer;
437	ENTER();	-
438		430
439	while (bytes > 0) {	431	while (bytes > 0) {
440	iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));	432	iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
441	next_cmd += sizeof(uint32_t);	433	next_cmd += sizeof(uint32_t);
442	if (unlikely(next_cmd == max))	434	if (unlikely(next_cmd == max))
443	next_cmd = min;	435	next_cmd = min;
444	mb();	436	mb();
445	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);	437	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
446	mb();	438	mb();
447	bytes -= sizeof(uint32_t);	439	bytes -= sizeof(uint32_t);
448	}	440	}
449	LEAVE();	-
450	}	441	}
451		442
452	void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)	443	void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
453	{	444	{
454	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;	445	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
455	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;	446	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
456	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);	447	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
457	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);	448	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
458	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);	449	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
459	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;	450	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
460		-
461	// ENTER();	-
462		451
463	BUG_ON((bytes & 3) != 0);	452	BUG_ON((bytes & 3) != 0);
464	BUG_ON(bytes > fifo_state->reserved_size);	453	BUG_ON(bytes > fifo_state->reserved_size);
465		454
466	fifo_state->reserved_size = 0;	455	fifo_state->reserved_size = 0;
467		456
468	if (fifo_state->using_bounce_buffer) {	457	if (fifo_state->using_bounce_buffer) {
469	if (reserveable)	458	if (reserveable)
470	vmw_fifo_res_copy(fifo_state, fifo_mem,	459	vmw_fifo_res_copy(fifo_state, fifo_mem,
471	next_cmd, max, min, bytes);	460	next_cmd, max, min, bytes);
472	else	461	else
473	vmw_fifo_slow_copy(fifo_state, fifo_mem,	462	vmw_fifo_slow_copy(fifo_state, fifo_mem,
474	next_cmd, max, min, bytes);	463	next_cmd, max, min, bytes);
475		464
476	if (fifo_state->dynamic_buffer) {	465	if (fifo_state->dynamic_buffer) {
477	vfree(fifo_state->dynamic_buffer);	466	vfree(fifo_state->dynamic_buffer);
478	fifo_state->dynamic_buffer = NULL;	467	fifo_state->dynamic_buffer = NULL;
479	}	468	}
480		469
481	}	470	}
482		471
483	// down_write(&fifo_state->rwsem);	472	// down_write(&fifo_state->rwsem);
484	if (fifo_state->using_bounce_buffer \|\| reserveable) {	473	if (fifo_state->using_bounce_buffer \|\| reserveable) {
485	next_cmd += bytes;	474	next_cmd += bytes;
486	if (next_cmd >= max)	475	if (next_cmd >= max)
487	next_cmd -= max - min;	476	next_cmd -= max - min;
488	mb();	477	mb();
489	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);	478	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
490	}	479	}
491		480
492	if (reserveable)	481	if (reserveable)
493	iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);	482	iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
494	mb();	483	mb();
495	// up_write(&fifo_state->rwsem);	484	// up_write(&fifo_state->rwsem);
496	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);	485	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
497	mutex_unlock(&fifo_state->fifo_mutex);	486	mutex_unlock(&fifo_state->fifo_mutex);
498		-
499	// LEAVE();	-
500	}	487	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/vmwgfx/vmwgfx_fifo.c – Rev 4570 → 5078