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Rev 4570 | Rev 5078 | ||
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Line 140... | Line 140... | ||
140 | * Ioctl definitions. |
140 | * Ioctl definitions. |
141 | */ |
141 | */ |
Line 142... | Line 142... | ||
142 | 142 | ||
143 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
143 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
144 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
144 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
145 | DRM_AUTH | DRM_UNLOCKED), |
145 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
146 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
146 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
147 | DRM_AUTH | DRM_UNLOCKED), |
147 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
148 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
148 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
149 | DRM_AUTH | DRM_UNLOCKED), |
149 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
150 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
150 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
151 | vmw_kms_cursor_bypass_ioctl, |
151 | vmw_kms_cursor_bypass_ioctl, |
Line 152... | Line 152... | ||
152 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
152 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
Line 157... | Line 157... | ||
157 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
157 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
158 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
158 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
159 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
159 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
Line 160... | Line 160... | ||
160 | 160 | ||
161 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
161 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
162 | DRM_AUTH | DRM_UNLOCKED), |
162 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
163 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
163 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
164 | DRM_AUTH | DRM_UNLOCKED), |
164 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
165 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
165 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
166 | DRM_AUTH | DRM_UNLOCKED), |
166 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
167 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
167 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
168 | DRM_AUTH | DRM_UNLOCKED), |
168 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
169 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
169 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
170 | DRM_AUTH | DRM_UNLOCKED), |
170 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
171 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
171 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
172 | DRM_AUTH | DRM_UNLOCKED), |
172 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
173 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
173 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
174 | DRM_AUTH | DRM_UNLOCKED), |
174 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
175 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, |
175 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, |
176 | vmw_fence_obj_signaled_ioctl, |
176 | vmw_fence_obj_signaled_ioctl, |
177 | DRM_AUTH | DRM_UNLOCKED), |
177 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
178 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, |
178 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, |
179 | DRM_AUTH | DRM_UNLOCKED), |
179 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
180 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, |
- | |
181 | vmw_fence_event_ioctl, |
180 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, |
182 | DRM_AUTH | DRM_UNLOCKED), |
181 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
183 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
182 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
Line 184... | Line 183... | ||
184 | DRM_AUTH | DRM_UNLOCKED), |
183 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
185 | 184 | ||
186 | /* these allow direct access to the framebuffers mark as master only */ |
185 | /* these allow direct access to the framebuffers mark as master only */ |
187 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, |
186 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, |
Line 192... | Line 191... | ||
192 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
191 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
193 | vmw_kms_update_layout_ioctl, |
192 | vmw_kms_update_layout_ioctl, |
194 | DRM_MASTER | DRM_UNLOCKED), |
193 | DRM_MASTER | DRM_UNLOCKED), |
195 | VMW_IOCTL_DEF(VMW_CREATE_SHADER, |
194 | VMW_IOCTL_DEF(VMW_CREATE_SHADER, |
196 | vmw_shader_define_ioctl, |
195 | vmw_shader_define_ioctl, |
197 | DRM_AUTH | DRM_UNLOCKED), |
196 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
198 | VMW_IOCTL_DEF(VMW_UNREF_SHADER, |
197 | VMW_IOCTL_DEF(VMW_UNREF_SHADER, |
199 | vmw_shader_destroy_ioctl, |
198 | vmw_shader_destroy_ioctl, |
200 | DRM_AUTH | DRM_UNLOCKED), |
199 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
201 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, |
200 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, |
202 | vmw_gb_surface_define_ioctl, |
201 | vmw_gb_surface_define_ioctl, |
203 | DRM_AUTH | DRM_UNLOCKED), |
202 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
204 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, |
203 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, |
205 | vmw_gb_surface_reference_ioctl, |
204 | vmw_gb_surface_reference_ioctl, |
206 | DRM_AUTH | DRM_UNLOCKED), |
205 | DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
207 | VMW_IOCTL_DEF(VMW_SYNCCPU, |
206 | VMW_IOCTL_DEF(VMW_SYNCCPU, |
208 | vmw_user_dmabuf_synccpu_ioctl, |
207 | vmw_user_dmabuf_synccpu_ioctl, |
209 | DRM_AUTH | DRM_UNLOCKED), |
208 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
210 | }; |
209 | }; |
211 | #endif |
210 | #endif |
Line 212... | Line 211... | ||
212 | 211 | ||
213 | static struct pci_device_id vmw_pci_id_list[] = { |
212 | static struct pci_device_id vmw_pci_id_list[] = { |
Line 313... | Line 312... | ||
313 | &bo); |
312 | &bo); |
Line 314... | Line 313... | ||
314 | 313 | ||
315 | if (unlikely(ret != 0)) |
314 | if (unlikely(ret != 0)) |
Line 316... | Line 315... | ||
316 | return ret; |
315 | return ret; |
317 | 316 | ||
Line 318... | Line 317... | ||
318 | ret = ttm_bo_reserve(bo, false, true, false, 0); |
317 | ret = ttm_bo_reserve(bo, false, true, false, NULL); |
319 | BUG_ON(ret != 0); |
318 | BUG_ON(ret != 0); |
320 | 319 | ||
Line 339... | Line 338... | ||
339 | } |
338 | } |
Line 340... | Line 339... | ||
340 | 339 | ||
341 | static int vmw_request_device(struct vmw_private *dev_priv) |
340 | static int vmw_request_device(struct vmw_private *dev_priv) |
342 | { |
341 | { |
343 | int ret; |
- | |
Line 344... | Line 342... | ||
344 | ENTER(); |
342 | int ret; |
345 | 343 | ||
346 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
344 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
347 | if (unlikely(ret != 0)) { |
345 | if (unlikely(ret != 0)) { |
Line 352... | Line 350... | ||
352 | // ret = vmw_dummy_query_bo_create(dev_priv); |
350 | // ret = vmw_dummy_query_bo_create(dev_priv); |
353 | // if (unlikely(ret != 0)) |
351 | // if (unlikely(ret != 0)) |
354 | // goto out_no_query_bo; |
352 | // goto out_no_query_bo; |
355 | // vmw_dummy_query_bo_prepare(dev_priv); |
353 | // vmw_dummy_query_bo_prepare(dev_priv); |
Line 356... | Line 354... | ||
356 | 354 | ||
Line 357... | Line 355... | ||
357 | LEAVE(); |
355 | |
Line 358... | Line 356... | ||
358 | 356 | ||
359 | return 0; |
357 | return 0; |
Line 532... | Line 530... | ||
532 | int ret; |
530 | int ret; |
533 | uint32_t svga_id; |
531 | uint32_t svga_id; |
534 | enum vmw_res_type i; |
532 | enum vmw_res_type i; |
535 | bool refuse_dma = false; |
533 | bool refuse_dma = false; |
Line 536... | Line -... | ||
536 | - | ||
537 | ENTER(); |
- | |
538 | 534 | ||
539 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
535 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
540 | if (unlikely(dev_priv == NULL)) { |
536 | if (unlikely(dev_priv == NULL)) { |
541 | DRM_ERROR("Failed allocating a device private struct.\n"); |
537 | DRM_ERROR("Failed allocating a device private struct.\n"); |
542 | return -ENOMEM; |
538 | return -ENOMEM; |
Line 550... | Line 546... | ||
550 | mutex_init(&dev_priv->hw_mutex); |
546 | mutex_init(&dev_priv->hw_mutex); |
551 | mutex_init(&dev_priv->cmdbuf_mutex); |
547 | mutex_init(&dev_priv->cmdbuf_mutex); |
552 | mutex_init(&dev_priv->release_mutex); |
548 | mutex_init(&dev_priv->release_mutex); |
553 | mutex_init(&dev_priv->binding_mutex); |
549 | mutex_init(&dev_priv->binding_mutex); |
554 | rwlock_init(&dev_priv->resource_lock); |
550 | rwlock_init(&dev_priv->resource_lock); |
- | 551 | ttm_lock_init(&dev_priv->reservation_sem); |
|
Line 555... | Line 552... | ||
555 | 552 | ||
556 | for (i = vmw_res_context; i < vmw_res_max; ++i) { |
553 | for (i = vmw_res_context; i < vmw_res_max; ++i) { |
557 | idr_init(&dev_priv->res_idr[i]); |
554 | idr_init(&dev_priv->res_idr[i]); |
558 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); |
555 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); |
Line 568... | Line 565... | ||
568 | 565 | ||
569 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); |
566 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); |
570 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); |
567 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); |
Line 571... | Line -... | ||
571 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); |
- | |
572 | - | ||
573 | printk("io: %x vram: %x mmio: %x\n",dev_priv->io_start, |
- | |
574 | dev_priv->vram_start,dev_priv->mmio_start); |
568 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); |
Line 575... | Line 569... | ||
575 | 569 | ||
Line 576... | Line 570... | ||
576 | dev_priv->enable_fb = enable_fbdev; |
570 | dev_priv->enable_fb = enable_fbdev; |
Line 614... | Line 608... | ||
614 | * memory. But all HWV8 hardware supports GMR2. |
608 | * memory. But all HWV8 hardware supports GMR2. |
615 | */ |
609 | */ |
616 | dev_priv->memory_size = 512*1024*1024; |
610 | dev_priv->memory_size = 512*1024*1024; |
617 | } |
611 | } |
618 | dev_priv->max_mob_pages = 0; |
612 | dev_priv->max_mob_pages = 0; |
- | 613 | dev_priv->max_mob_size = 0; |
|
619 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
614 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
620 | uint64_t mem_size = |
615 | uint64_t mem_size = |
621 | vmw_read(dev_priv, |
616 | vmw_read(dev_priv, |
622 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); |
617 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); |
Line 623... | Line 618... | ||
623 | 618 | ||
624 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; |
619 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; |
625 | dev_priv->prim_bb_mem = |
620 | dev_priv->prim_bb_mem = |
626 | vmw_read(dev_priv, |
621 | vmw_read(dev_priv, |
- | 622 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); |
|
- | 623 | dev_priv->max_mob_size = |
|
627 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); |
624 | vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); |
628 | } else |
625 | } else |
Line 629... | Line 626... | ||
629 | dev_priv->prim_bb_mem = dev_priv->vram_size; |
626 | dev_priv->prim_bb_mem = dev_priv->vram_size; |
630 | 627 | ||
Line 665... | Line 662... | ||
665 | dev_priv->active_master = &dev_priv->fbdev_master; |
662 | dev_priv->active_master = &dev_priv->fbdev_master; |
Line 666... | Line 663... | ||
666 | 663 | ||
667 | 664 | ||
- | 665 | ret = ttm_bo_device_init(&dev_priv->bdev, |
|
- | 666 | dev_priv->bo_global_ref.ref.object, |
|
668 | ret = ttm_bo_device_init(&dev_priv->bdev, |
667 | &vmw_bo_driver, |
669 | dev_priv->bo_global_ref.ref.object, |
668 | NULL, |
670 | &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, |
669 | VMWGFX_FILE_PAGE_OFFSET, |
671 | false); |
670 | false); |
672 | if (unlikely(ret != 0)) { |
671 | if (unlikely(ret != 0)) { |
673 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); |
672 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); |
Line 715... | Line 714... | ||
715 | ret = -ENOSYS; |
714 | ret = -ENOSYS; |
716 | DRM_ERROR("Hardware has no pitchlock\n"); |
715 | DRM_ERROR("Hardware has no pitchlock\n"); |
717 | goto out_err4; |
716 | goto out_err4; |
718 | } |
717 | } |
Line 719... | Line 718... | ||
719 | 718 | ||
720 | // dev_priv->tdev = ttm_object_device_init |
719 | dev_priv->tdev = ttm_object_device_init |
Line 721... | Line 720... | ||
721 | // (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); |
720 | (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); |
722 | 721 | ||
723 | // if (unlikely(dev_priv->tdev == NULL)) { |
722 | if (unlikely(dev_priv->tdev == NULL)) { |
724 | // DRM_ERROR("Unable to initialize TTM object management.\n"); |
723 | DRM_ERROR("Unable to initialize TTM object management.\n"); |
725 | // ret = -ENOMEM; |
724 | ret = -ENOMEM; |
Line 726... | Line 725... | ||
726 | // goto out_err4; |
725 | goto out_err4; |
Line 727... | Line 726... | ||
727 | // } |
726 | } |
Line 728... | Line 727... | ||
728 | 727 | ||
729 | dev->dev_private = dev_priv; |
728 | dev->dev_private = dev_priv; |
730 | 729 | ||
731 | #if 0 |
730 | #if 0 |
732 | 731 | ||
733 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
732 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
734 | ret = drm_irq_install(dev); |
733 | ret = drm_irq_install(dev, dev->pdev->irq); |
Line 759... | Line 758... | ||
759 | // vmw_fb_init(dev_priv); |
758 | // vmw_fb_init(dev_priv); |
760 | } |
759 | } |
Line 761... | Line 760... | ||
761 | 760 | ||
Line 762... | Line -... | ||
762 | main_device = dev; |
- | |
763 | 761 | main_device = dev; |
|
Line 764... | Line 762... | ||
764 | LEAVE(); |
762 | |
765 | return 0; |
763 | return 0; |
766 | 764 | ||
Line 888... | Line 886... | ||
888 | // vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); |
886 | // vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); |
889 | // if (unlikely(vmw_fp->tfile == NULL)) |
887 | // if (unlikely(vmw_fp->tfile == NULL)) |
890 | // goto out_no_tfile; |
888 | // goto out_no_tfile; |
Line 891... | Line 889... | ||
891 | 889 | ||
892 | file_priv->driver_priv = vmw_fp; |
- | |
Line 893... | Line 890... | ||
893 | // dev_priv->bdev.dev_mapping = dev->dev_mapping; |
890 | file_priv->driver_priv = vmw_fp; |
Line 894... | Line 891... | ||
894 | 891 | ||
895 | return 0; |
892 | return 0; |
Line 1092... | Line 1089... | ||
1092 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
1089 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
1093 | void *ptr) |
1090 | void *ptr) |
1094 | { |
1091 | { |
1095 | struct vmw_private *dev_priv = |
1092 | struct vmw_private *dev_priv = |
1096 | container_of(nb, struct vmw_private, pm_nb); |
1093 | container_of(nb, struct vmw_private, pm_nb); |
1097 | struct vmw_master *vmaster = dev_priv->active_master; |
- | |
Line 1098... | Line 1094... | ||
1098 | 1094 | ||
1099 | switch (val) { |
1095 | switch (val) { |
1100 | case PM_HIBERNATION_PREPARE: |
1096 | case PM_HIBERNATION_PREPARE: |
1101 | case PM_SUSPEND_PREPARE: |
1097 | case PM_SUSPEND_PREPARE: |
Line 1102... | Line 1098... | ||
1102 | ttm_suspend_lock(&vmaster->lock); |
1098 | ttm_suspend_lock(&dev_priv->reservation_sem); |
1103 | 1099 | ||
1104 | /** |
1100 | /** |
1105 | * This empties VRAM and unbinds all GMR bindings. |
1101 | * This empties VRAM and unbinds all GMR bindings. |
Line 1111... | Line 1107... | ||
1111 | 1107 | ||
1112 | break; |
1108 | break; |
1113 | case PM_POST_HIBERNATION: |
1109 | case PM_POST_HIBERNATION: |
1114 | case PM_POST_SUSPEND: |
1110 | case PM_POST_SUSPEND: |
1115 | case PM_POST_RESTORE: |
1111 | case PM_POST_RESTORE: |
Line 1116... | Line 1112... | ||
1116 | ttm_suspend_unlock(&vmaster->lock); |
1112 | ttm_suspend_unlock(&dev_priv->reservation_sem); |
1117 | 1113 | ||
1118 | break; |
1114 | break; |
1119 | case PM_RESTORE_PREPARE: |
1115 | case PM_RESTORE_PREPARE: |
Line 1199... | Line 1195... | ||
1199 | 1195 | ||
Line 1200... | Line 1196... | ||
1200 | #endif |
1196 | #endif |
1201 | 1197 | ||
1202 | static struct drm_driver driver = { |
1198 | static struct drm_driver driver = { |
1203 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | |
1199 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | |
1204 | DRIVER_MODESET, |
1200 | DRIVER_MODESET | DRIVER_RENDER, |
1205 | .load = vmw_driver_load, |
1201 | .load = vmw_driver_load, |
1206 | // .unload = vmw_driver_unload, |
1202 | // .unload = vmw_driver_unload, |
1207 | // .lastclose = vmw_lastclose, |
1203 | // .lastclose = vmw_lastclose, |
Line 1246... | Line 1242... | ||
1246 | { |
1242 | { |
1247 | static pci_dev_t device; |
1243 | static pci_dev_t device; |
1248 | const struct pci_device_id *ent; |
1244 | const struct pci_device_id *ent; |
1249 | int err; |
1245 | int err; |
Line 1250... | Line -... | ||
1250 | - | ||
Line 1251... | Line 1246... | ||
1251 | ENTER(); |
1246 | |
1252 | 1247 | ||
1253 | ent = find_pci_device(&device, vmw_pci_id_list); |
1248 | ent = find_pci_device(&device, vmw_pci_id_list); |
1254 | if( unlikely(ent == NULL) ) |
1249 | if( unlikely(ent == NULL) ) |
Line 1261... | Line 1256... | ||
1261 | 1256 | ||
1262 | DRM_INFO("device %x:%x\n", device.pci_dev.vendor, |
1257 | DRM_INFO("device %x:%x\n", device.pci_dev.vendor, |
Line 1263... | Line 1258... | ||
1263 | device.pci_dev.device); |
1258 | device.pci_dev.device); |
1264 | - | ||
Line 1265... | Line 1259... | ||
1265 | err = drm_get_pci_dev(&device.pci_dev, ent, &driver); |
1259 | |
1266 | LEAVE(); |
1260 | err = drm_get_pci_dev(&device.pci_dev, ent, &driver); |