WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/uvd_v2_2.c


/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König 
 */
 
#include 
#include 
#include "radeon.h"
#include "radeon_asic.h"
#include "rv770d.h"
 
/**
 * uvd_v2_2_fence_emit - emit an fence & trap command
 *
 * @rdev: radeon_device pointer
 * @fence: fence to emit
 *
 * Write a fence and a trap command to the ring.
 */
void uvd_v2_2_fence_emit(struct radeon_device *rdev,
			 struct radeon_fence *fence)
{
	struct radeon_ring *ring = &rdev->ring[fence->ring];
	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
 
	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
	radeon_ring_write(ring, fence->seq);
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
	radeon_ring_write(ring, lower_32_bits(addr));
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
	radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
	radeon_ring_write(ring, 0);
 
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
	radeon_ring_write(ring, 0);
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
	radeon_ring_write(ring, 2);
}
 
/**
 * uvd_v2_2_semaphore_emit - emit semaphore command
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring pointer
 * @semaphore: semaphore to emit commands for
 * @emit_wait: true if we should emit a wait command
 *
 * Emit a semaphore command (either wait or signal) to the UVD ring.
 */
bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
			     struct radeon_ring *ring,
			     struct radeon_semaphore *semaphore,
			     bool emit_wait)
{
	uint64_t addr = semaphore->gpu_addr;
 
	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
	radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
 
	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
	radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
 
	radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
	radeon_ring_write(ring, emit_wait ? 1 : 0);
 
	return true;
}
 
/**
 * uvd_v2_2_resume - memory controller programming
 *
 * @rdev: radeon_device pointer
 *
 * Let the UVD memory controller know it's offsets
 */
int uvd_v2_2_resume(struct radeon_device *rdev)
{
	uint64_t addr;
	uint32_t chip_id, size;
	int r;
 
	/* RV770 uses V1.0 MC */
	if (rdev->family == CHIP_RV770)
		return uvd_v1_0_resume(rdev);
 
	r = radeon_uvd_resume(rdev);
	if (r)
		return r;
 
	/* programm the VCPU memory controller bits 0-27 */
	addr = rdev->uvd.gpu_addr >> 3;
	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
	WREG32(UVD_VCPU_CACHE_SIZE0, size);
 
	addr += size;
	size = RADEON_UVD_STACK_SIZE >> 3;
	WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
	WREG32(UVD_VCPU_CACHE_SIZE1, size);
 
	addr += size;
	size = RADEON_UVD_HEAP_SIZE >> 3;
	WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
	WREG32(UVD_VCPU_CACHE_SIZE2, size);
 
	/* bits 28-31 */
	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
	WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
 
	/* bits 32-39 */
	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
	WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 
	/* tell firmware which hardware it is running on */
	switch (rdev->family) {
	default:
		return -EINVAL;
	case CHIP_RV710:
		chip_id = 0x01000005;
		break;
	case CHIP_RV730:
		chip_id = 0x01000006;
		break;
	case CHIP_RV740:
		chip_id = 0x01000007;
		break;
	case CHIP_CYPRESS:
	case CHIP_HEMLOCK:
		chip_id = 0x01000008;
		break;
	case CHIP_JUNIPER:
		chip_id = 0x01000009;
		break;
	case CHIP_REDWOOD:
		chip_id = 0x0100000a;
		break;
	case CHIP_CEDAR:
		chip_id = 0x0100000b;
		break;
	case CHIP_SUMO:
	case CHIP_SUMO2:
		chip_id = 0x0100000c;
		break;
	case CHIP_PALM:
		chip_id = 0x0100000e;
		break;
	case CHIP_CAYMAN:
		chip_id = 0x0100000f;
		break;
	case CHIP_BARTS:
		chip_id = 0x01000010;
		break;
	case CHIP_TURKS:
		chip_id = 0x01000011;
		break;
	case CHIP_CAICOS:
		chip_id = 0x01000012;
		break;
	case CHIP_TAHITI:
		chip_id = 0x01000014;
		break;
	case CHIP_VERDE:
		chip_id = 0x01000015;
		break;
	case CHIP_PITCAIRN:
	case CHIP_OLAND:
		chip_id = 0x01000016;
		break;
	case CHIP_ARUBA:
		chip_id = 0x01000017;
		break;
	}
	WREG32(UVD_VCPU_CHIP_ID, chip_id);
 
	return 0;
}

Rev 5271	Rev 6104
1	/*	1	/*
2	* Copyright 2013 Advanced Micro Devices, Inc.	2	* Copyright 2013 Advanced Micro Devices, Inc.
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice shall be included in	11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.	12	* all copies or substantial portions of the Software.
13	*	13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.	20	* OTHER DEALINGS IN THE SOFTWARE.
21	*	21	*
22	* Authors: Christian König	22	* Authors: Christian König
23	*/	23	*/
24		24
25	#include	25	#include
26	#include	26	#include
27	#include "radeon.h"	27	#include "radeon.h"
28	#include "radeon_asic.h"	28	#include "radeon_asic.h"
29	#include "rv770d.h"	29	#include "rv770d.h"
30		30
31	/**	31	/**
32	* uvd_v2_2_fence_emit - emit an fence & trap command	32	* uvd_v2_2_fence_emit - emit an fence & trap command
33	*	33	*
34	* @rdev: radeon_device pointer	34	* @rdev: radeon_device pointer
35	* @fence: fence to emit	35	* @fence: fence to emit
36	*	36	*
37	* Write a fence and a trap command to the ring.	37	* Write a fence and a trap command to the ring.
38	*/	38	*/
39	void uvd_v2_2_fence_emit(struct radeon_device *rdev,	39	void uvd_v2_2_fence_emit(struct radeon_device *rdev,
40	struct radeon_fence *fence)	40	struct radeon_fence *fence)
41	{	41	{
42	struct radeon_ring *ring = &rdev->ring[fence->ring];	42	struct radeon_ring *ring = &rdev->ring[fence->ring];
43	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;	43	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
44		44
45	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));	45	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
46	radeon_ring_write(ring, fence->seq);	46	radeon_ring_write(ring, fence->seq);
47	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));	47	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
48	radeon_ring_write(ring, lower_32_bits(addr));	48	radeon_ring_write(ring, lower_32_bits(addr));
49	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));	49	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
50	radeon_ring_write(ring, upper_32_bits(addr) & 0xff);	50	radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
51	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));	51	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
52	radeon_ring_write(ring, 0);	52	radeon_ring_write(ring, 0);
53		53
54	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));	54	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
55	radeon_ring_write(ring, 0);	55	radeon_ring_write(ring, 0);
56	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));	56	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
57	radeon_ring_write(ring, 0);	57	radeon_ring_write(ring, 0);
58	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));	58	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
59	radeon_ring_write(ring, 2);	59	radeon_ring_write(ring, 2);
60	}	60	}
61		61
62	/**	62	/**
-		63	* uvd_v2_2_semaphore_emit - emit semaphore command
-		64	*
-		65	* @rdev: radeon_device pointer
-		66	* @ring: radeon_ring pointer
-		67	* @semaphore: semaphore to emit commands for
-		68	* @emit_wait: true if we should emit a wait command
-		69	*
-		70	* Emit a semaphore command (either wait or signal) to the UVD ring.
-		71	*/
-		72	bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
-		73	struct radeon_ring *ring,
-		74	struct radeon_semaphore *semaphore,
-		75	bool emit_wait)
-		76	{
-		77	uint64_t addr = semaphore->gpu_addr;
-		78
-		79	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
-		80	radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
-		81
-		82	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
-		83	radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
-		84
-		85	radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
-		86	radeon_ring_write(ring, emit_wait ? 1 : 0);
-		87
-		88	return true;
-		89	}
-		90
-		91	/**
63	* uvd_v2_2_resume - memory controller programming	92	* uvd_v2_2_resume - memory controller programming
64	*	93	*
65	* @rdev: radeon_device pointer	94	* @rdev: radeon_device pointer
66	*	95	*
67	* Let the UVD memory controller know it's offsets	96	* Let the UVD memory controller know it's offsets
68	*/	97	*/
69	int uvd_v2_2_resume(struct radeon_device *rdev)	98	int uvd_v2_2_resume(struct radeon_device *rdev)
70	{	99	{
71	uint64_t addr;	100	uint64_t addr;
72	uint32_t chip_id, size;	101	uint32_t chip_id, size;
73	int r;	102	int r;
74		103
75	/* RV770 uses V1.0 MC */	104	/* RV770 uses V1.0 MC */
76	if (rdev->family == CHIP_RV770)	105	if (rdev->family == CHIP_RV770)
77	return uvd_v1_0_resume(rdev);	106	return uvd_v1_0_resume(rdev);
78		107
79	r = radeon_uvd_resume(rdev);	108	r = radeon_uvd_resume(rdev);
80	if (r)	109	if (r)
81	return r;	110	return r;
82		111
83	/* programm the VCPU memory controller bits 0-27 */	112	/* programm the VCPU memory controller bits 0-27 */
84	addr = rdev->uvd.gpu_addr >> 3;	113	addr = rdev->uvd.gpu_addr >> 3;
85	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;	114	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
86	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);	115	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
87	WREG32(UVD_VCPU_CACHE_SIZE0, size);	116	WREG32(UVD_VCPU_CACHE_SIZE0, size);
88		117
89	addr += size;	118	addr += size;
90	size = RADEON_UVD_STACK_SIZE >> 3;	119	size = RADEON_UVD_STACK_SIZE >> 3;
91	WREG32(UVD_VCPU_CACHE_OFFSET1, addr);	120	WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
92	WREG32(UVD_VCPU_CACHE_SIZE1, size);	121	WREG32(UVD_VCPU_CACHE_SIZE1, size);
93		122
94	addr += size;	123	addr += size;
95	size = RADEON_UVD_HEAP_SIZE >> 3;	124	size = RADEON_UVD_HEAP_SIZE >> 3;
96	WREG32(UVD_VCPU_CACHE_OFFSET2, addr);	125	WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
97	WREG32(UVD_VCPU_CACHE_SIZE2, size);	126	WREG32(UVD_VCPU_CACHE_SIZE2, size);
98		127
99	/* bits 28-31 */	128	/* bits 28-31 */
100	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;	129	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
101	WREG32(UVD_LMI_ADDR_EXT, (addr << 12) \| (addr << 0));	130	WREG32(UVD_LMI_ADDR_EXT, (addr << 12) \| (addr << 0));
102		131
103	/* bits 32-39 */	132	/* bits 32-39 */
104	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;	133	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
105	WREG32(UVD_LMI_EXT40_ADDR, addr \| (0x9 << 16) \| (0x1 << 31));	134	WREG32(UVD_LMI_EXT40_ADDR, addr \| (0x9 << 16) \| (0x1 << 31));
106		135
107	/* tell firmware which hardware it is running on */	136	/* tell firmware which hardware it is running on */
108	switch (rdev->family) {	137	switch (rdev->family) {
109	default:	138	default:
110	return -EINVAL;	139	return -EINVAL;
111	case CHIP_RV710:	140	case CHIP_RV710:
112	chip_id = 0x01000005;	141	chip_id = 0x01000005;
113	break;	142	break;
114	case CHIP_RV730:	143	case CHIP_RV730:
115	chip_id = 0x01000006;	144	chip_id = 0x01000006;
116	break;	145	break;
117	case CHIP_RV740:	146	case CHIP_RV740:
118	chip_id = 0x01000007;	147	chip_id = 0x01000007;
119	break;	148	break;
120	case CHIP_CYPRESS:	149	case CHIP_CYPRESS:
121	case CHIP_HEMLOCK:	150	case CHIP_HEMLOCK:
122	chip_id = 0x01000008;	151	chip_id = 0x01000008;
123	break;	152	break;
124	case CHIP_JUNIPER:	153	case CHIP_JUNIPER:
125	chip_id = 0x01000009;	154	chip_id = 0x01000009;
126	break;	155	break;
127	case CHIP_REDWOOD:	156	case CHIP_REDWOOD:
128	chip_id = 0x0100000a;	157	chip_id = 0x0100000a;
129	break;	158	break;
130	case CHIP_CEDAR:	159	case CHIP_CEDAR:
131	chip_id = 0x0100000b;	160	chip_id = 0x0100000b;
132	break;	161	break;
133	case CHIP_SUMO:	162	case CHIP_SUMO:
134	case CHIP_SUMO2:	163	case CHIP_SUMO2:
135	chip_id = 0x0100000c;	164	chip_id = 0x0100000c;
136	break;	165	break;
137	case CHIP_PALM:	166	case CHIP_PALM:
138	chip_id = 0x0100000e;	167	chip_id = 0x0100000e;
139	break;	168	break;
140	case CHIP_CAYMAN:	169	case CHIP_CAYMAN:
141	chip_id = 0x0100000f;	170	chip_id = 0x0100000f;
142	break;	171	break;
143	case CHIP_BARTS:	172	case CHIP_BARTS:
144	chip_id = 0x01000010;	173	chip_id = 0x01000010;
145	break;	174	break;
146	case CHIP_TURKS:	175	case CHIP_TURKS:
147	chip_id = 0x01000011;	176	chip_id = 0x01000011;
148	break;	177	break;
149	case CHIP_CAICOS:	178	case CHIP_CAICOS:
150	chip_id = 0x01000012;	179	chip_id = 0x01000012;
151	break;	180	break;
152	case CHIP_TAHITI:	181	case CHIP_TAHITI:
153	chip_id = 0x01000014;	182	chip_id = 0x01000014;
154	break;	183	break;
155	case CHIP_VERDE:	184	case CHIP_VERDE:
156	chip_id = 0x01000015;	185	chip_id = 0x01000015;
157	break;	186	break;
158	case CHIP_PITCAIRN:	187	case CHIP_PITCAIRN:
159	case CHIP_OLAND:	188	case CHIP_OLAND:
160	chip_id = 0x01000016;	189	chip_id = 0x01000016;
161	break;	190	break;
162	case CHIP_ARUBA:	191	case CHIP_ARUBA:
163	chip_id = 0x01000017;	192	chip_id = 0x01000017;
164	break;	193	break;
165	}	194	}
166	WREG32(UVD_VCPU_CHIP_ID, chip_id);	195	WREG32(UVD_VCPU_CHIP_ID, chip_id);
167		196
168	return 0;	197	return 0;
169	}	198	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/uvd_v2_2.c – Rev 5271 → 6104