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Rev 5078 Rev 5271
Line 68... Line 68...
68 
{
 68 
{
69 
	WREG32(UVD_RBC_RB_WPTR, ring->wptr);
 69 
	WREG32(UVD_RBC_RB_WPTR, ring->wptr);
70 
}
 70 
}
Line 71... Line 71...
71 
 
 71 
 
- 
 
 72 
/**
- 
 
 73 
 * uvd_v1_0_fence_emit - emit an fence & trap command
- 
 
 74 
 *
- 
 
 75 
 * @rdev: radeon_device pointer
- 
 
 76 
 * @fence: fence to emit
- 
 
 77 
 *
- 
 
 78 
 * Write a fence and a trap command to the ring.
- 
 
 79 
 */
- 
 
 80 
void uvd_v1_0_fence_emit(struct radeon_device *rdev,
- 
 
 81 
			 struct radeon_fence *fence)
- 
 
 82 
{
- 
 
 83 
	struct radeon_ring *ring = &rdev->ring[fence->ring];
- 
 
 84 
	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
- 
 
 85 
 
- 
 
 86 
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
- 
 
 87 
	radeon_ring_write(ring, addr & 0xffffffff);
- 
 
 88 
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
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 89 
	radeon_ring_write(ring, fence->seq);
- 
 
 90 
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
- 
 
 91 
	radeon_ring_write(ring, 0);
- 
 
 92 
 
- 
 
 93 
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
- 
 
 94 
	radeon_ring_write(ring, 0);
- 
 
 95 
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
- 
 
 96 
	radeon_ring_write(ring, 0);
- 
 
 97 
	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
- 
 
 98 
	radeon_ring_write(ring, 2);
- 
 
 99 
	return;
- 
 
 100 
}
- 
 
 101 
 
- 
 
 102 
/**
- 
 
 103 
 * uvd_v1_0_resume - memory controller programming
- 
 
 104 
 *
- 
 
 105 
 * @rdev: radeon_device pointer
- 
 
 106 
 *
- 
 
 107 
 * Let the UVD memory controller know it's offsets
- 
 
 108 
 */
- 
 
 109 
int uvd_v1_0_resume(struct radeon_device *rdev)
- 
 
 110 
{
- 
 
 111 
	uint64_t addr;
- 
 
 112 
	uint32_t size;
- 
 
 113 
	int r;
- 
 
 114 
 
- 
 
 115 
	r = radeon_uvd_resume(rdev);
- 
 
 116 
	if (r)
- 
 
 117 
		return r;
- 
 
 118 
 
- 
 
 119 
	/* programm the VCPU memory controller bits 0-27 */
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 120 
	addr = (rdev->uvd.gpu_addr >> 3) + 16;
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 121 
	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;
- 
 
 122 
	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
- 
 
 123 
	WREG32(UVD_VCPU_CACHE_SIZE0, size);
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 124 
 
- 
 
 125 
	addr += size;
- 
 
 126 
	size = RADEON_UVD_STACK_SIZE >> 3;
- 
 
 127 
	WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
- 
 
 128 
	WREG32(UVD_VCPU_CACHE_SIZE1, size);
- 
 
 129 
 
- 
 
 130 
	addr += size;
- 
 
 131 
	size = RADEON_UVD_HEAP_SIZE >> 3;
- 
 
 132 
	WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
- 
 
 133 
	WREG32(UVD_VCPU_CACHE_SIZE2, size);
- 
 
 134 
 
- 
 
 135 
	/* bits 28-31 */
- 
 
 136 
	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
- 
 
 137 
	WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
- 
 
 138 
 
- 
 
 139 
	/* bits 32-39 */
- 
 
 140 
	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
- 
 
 141 
	WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
- 
 
 142 
 
- 
 
 143 
	WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));
- 
 
 144 
 
- 
 
 145 
	return 0;
- 
 
 146 
}
- 
 
 147 
 
72 
/**
 148 
/**
73 
 * uvd_v1_0_init - start and test UVD block
 149 
 * uvd_v1_0_init - start and test UVD block
74 
 *
 150 
 *
75 
 * @rdev: radeon_device pointer
 151 
 * @rdev: radeon_device pointer
76 
 *
 152 
 *
Line 128... Line 204...
128 
 
 204 
 
129 
done:
 205 
done:
130 
	/* lower clocks again */
 206 
	/* lower clocks again */
Line 131... Line 207...
131 
	radeon_set_uvd_clocks(rdev, 0, 0);
 207 
	radeon_set_uvd_clocks(rdev, 0, 0);
- 
 
 208 
 
- 
 
 209 
	if (!r) {
- 
 
 210 
		switch (rdev->family) {
- 
 
 211 
		case CHIP_RV610:
- 
 
 212 
		case CHIP_RV630:
- 
 
 213 
		case CHIP_RV620:
- 
 
 214 
			/* 64byte granularity workaround */
- 
 
 215 
			WREG32(MC_CONFIG, 0);
- 
 
 216 
			WREG32(MC_CONFIG, 1 << 4);
- 
 
 217 
			WREG32(RS_DQ_RD_RET_CONF, 0x3f);
- 
 
 218 
			WREG32(MC_CONFIG, 0x1f);
- 
 
 219 
 
- 
 
 220 
			/* fall through */
- 
 
 221 
		case CHIP_RV670:
- 
 
 222 
		case CHIP_RV635:
- 
 
 223 
 
- 
 
 224 
			/* write clean workaround */
- 
 
 225 
			WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);
- 
 
 226 
			break;
- 
 
 227 
 
- 
 
 228 
		default:
- 
 
 229 
			/* TODO: Do we need more? */
- 
 
 230 
			break;
132 
 
 231 
		}
- 
 
 232 
 
Line 133... Line 233...
133 
	if (!r)
 233 
		DRM_INFO("UVD initialized successfully.\n");
134 
		DRM_INFO("UVD initialized successfully.\n");
 234 
	}
Line 135... Line 235...
135 
 
 235 
 
Line 216... Line 316...
216 
	WREG32(UVD_VCPU_CNTL,  1 << 9);
 316 
	WREG32(UVD_VCPU_CNTL,  1 << 9);
Line 217... Line 317...
217 
 
 317 
 
218 
	/* enable UMC */
 318 
	/* enable UMC */
Line -... Line 319...
- 
 
 319 
	WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
- 
 
 320 
 
219 
	WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
 321 
	WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
220 
 
 322 
 
221 
	/* boot up the VCPU */
 323 
	/* boot up the VCPU */
Line 222... Line -...
222 
	WREG32(UVD_SOFT_RESET, 0);
 - 
 
223 
	mdelay(10);
 - 
 
224 
 
 324 
	WREG32(UVD_SOFT_RESET, 0);
225 
	WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
 325 
	mdelay(10);
226 
 
 326 
 
227 
	for (i = 0; i < 10; ++i) {
 327 
	for (i = 0; i < 10; ++i) {
228 
		uint32_t status;
 328 
		uint32_t status;