Subversion Repositories Kolibri OS

#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001

#define SI_MAX_SH_GPRS           256

#define SI_MAX_TEMP_GPRS         16

#define SI_MAX_SH_THREADS        256

#define SI_MAX_SH_STACK_ENTRIES  4096

#define SI_MAX_FRC_EOV_CNT       16384

#define SI_MAX_BACKENDS          8

#define SI_MAX_BACKENDS_MASK     0xFF

#define SI_MAX_BACKENDS_PER_SE_MASK     0x0F

#define SI_MAX_SIMDS             12

#define SI_MAX_SIMDS_MASK        0x0FFF

#define SI_MAX_SIMDS_PER_SE_MASK        0x00FF

#define SI_MAX_PIPES             8

#define SI_MAX_PIPES_MASK        0xFF

#define SI_MAX_PIPES_PER_SIMD_MASK      0x3F

#define SI_MAX_LDS_NUM           0xFFFF

#define SI_MAX_TCC               16

#define SI_MAX_TCC_MASK          0xFFFF

/* SMC IND accessor regs */

#define SMC_IND_INDEX_0                              0x200

#define SMC_IND_DATA_0                               0x204

#define SMC_IND_ACCESS_CNTL                          0x228

#       define AUTO_INCREMENT_IND_0                  (1 << 0)

#define SMC_MESSAGE_0                                0x22c

#define SMC_RESP_0                                   0x230

/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */

#define SMC_CG_IND_START                    0xc0030000

#define SMC_CG_IND_END                      0xc0040000

#define	CG_CGTT_LOCAL_0				0x400

#define	CG_CGTT_LOCAL_1				0x401

/* SMC IND registers */

#define	SMC_SYSCON_RESET_CNTL				0x80000000

#       define RST_REG                                  (1 << 0)

#define	SMC_SYSCON_CLOCK_CNTL_0				0x80000004

#       define CK_DISABLE                               (1 << 0)

#       define CKEN                                     (1 << 24)

#define VGA_HDP_CONTROL  				0x328

#define		VGA_MEMORY_DISABLE				(1 << 4)

#define DCCG_DISP_SLOW_SELECT_REG                       0x4fc

#define		DCCG_DISP1_SLOW_SELECT(x)		((x) << 0)

#define		DCCG_DISP1_SLOW_SELECT_MASK		(7 << 0)

#define		DCCG_DISP1_SLOW_SELECT_SHIFT		0

#define		DCCG_DISP2_SLOW_SELECT(x)		((x) << 4)

#define		DCCG_DISP2_SLOW_SELECT_MASK		(7 << 4)

#define		DCCG_DISP2_SLOW_SELECT_SHIFT		4

#define	CG_SPLL_FUNC_CNTL				0x600

#define		SPLL_RESET				(1 << 0)

#define		SPLL_SLEEP				(1 << 1)

#define		SPLL_BYPASS_EN				(1 << 3)

#define		SPLL_REF_DIV(x)				((x) << 4)

#define		SPLL_REF_DIV_MASK			(0x3f << 4)

#define		SPLL_PDIV_A(x)				((x) << 20)

#define		SPLL_PDIV_A_MASK			(0x7f << 20)

#define		SPLL_PDIV_A_SHIFT			20

#define	CG_SPLL_FUNC_CNTL_2				0x604

#define		SCLK_MUX_SEL(x)				((x) << 0)

#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)

#define		SPLL_CTLREQ_CHG				(1 << 23)

#define		SCLK_MUX_UPDATE				(1 << 26)

#define	CG_SPLL_FUNC_CNTL_3				0x608

#define		SPLL_FB_DIV(x)				((x) << 0)

#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)

#define		SPLL_FB_DIV_SHIFT			0

#define		SPLL_DITHEN				(1 << 28)

#define	CG_SPLL_FUNC_CNTL_4				0x60c

#define	SPLL_STATUS					0x614

#define		SPLL_CHG_STATUS				(1 << 1)

#define	SPLL_CNTL_MODE					0x618

#define		SPLL_SW_DIR_CONTROL			(1 << 0)

#	define SPLL_REFCLK_SEL(x)			((x) << 26)

#	define SPLL_REFCLK_SEL_MASK			(3 << 26)

#define	CG_SPLL_SPREAD_SPECTRUM				0x620

#define		SSEN					(1 << 0)

#define		CLK_S(x)				((x) << 4)

#define		CLK_S_MASK				(0xfff << 4)

#define		CLK_S_SHIFT				4

#define	CG_SPLL_SPREAD_SPECTRUM_2			0x624

#define		CLK_V(x)				((x) << 0)

#define		CLK_V_MASK				(0x3ffffff << 0)

#define		CLK_V_SHIFT				0

#define	CG_SPLL_AUTOSCALE_CNTL				0x62c

#define	MPLL_BYPASSCLK_SEL				0x65c

#	define MPLL_CLKOUT_SEL(x)			((x) << 8)

#	define MPLL_CLKOUT_SEL_MASK			0xFF00

#define CG_CLKPIN_CNTL                                    0x660

#       define XTALIN_DIVIDE                              (1 << 1)

#       define BCLK_AS_XCLK                               (1 << 2)

#define CG_CLKPIN_CNTL_2                                  0x664

#       define FORCE_BIF_REFCLK_EN                        (1 << 3)

#       define MUX_TCLK_TO_XCLK                           (1 << 8)

#define	THM_CLK_CNTL					0x66c

#	define CMON_CLK_SEL(x)				((x) << 0)

#	define CMON_CLK_SEL_MASK			0xFF

#	define TMON_CLK_SEL(x)				((x) << 8)

#	define TMON_CLK_SEL_MASK			0xFF00

#define	MISC_CLK_CNTL					0x670

#	define DEEP_SLEEP_CLK_SEL(x)			((x) << 0)

#	define DEEP_SLEEP_CLK_SEL_MASK			0xFF

#	define ZCLK_SEL(x)				((x) << 8)

#	define ZCLK_SEL_MASK				0xFF00

#define	CG_THERMAL_CTRL					0x700

#define 	DPM_EVENT_SRC(x)			((x) << 0)

#define 	DPM_EVENT_SRC_MASK			(7 << 0)

#define		DIG_THERM_DPM(x)			((x) << 14)

#define		DIG_THERM_DPM_MASK			0x003FC000

#define		DIG_THERM_DPM_SHIFT			14

#define	CG_THERMAL_INT					0x708

#define		DIG_THERM_INTH(x)			((x) << 8)

#define		DIG_THERM_INTH_MASK			0x0000FF00

#define		DIG_THERM_INTH_SHIFT			8

#define		DIG_THERM_INTL(x)			((x) << 16)

#define		DIG_THERM_INTL_MASK			0x00FF0000

#define		DIG_THERM_INTL_SHIFT			16

#define 	THERM_INT_MASK_HIGH			(1 << 24)

#define 	THERM_INT_MASK_LOW			(1 << 25)

#       define THERMAL_PROTECTION_DIS                   (1 << 2)

#       define VOLT_PWRMGT_EN                           (1 << 10)

#define CG_TPC                                            0x784

#define SCLK_PWRMGT_CNTL                                  0x788

#       define SCLK_PWRMGT_OFF                            (1 << 0)

#       define FIR_RESET                                  (1 << 4)

#       define FIR_FORCE_TREND_SEL                        (1 << 5)

#       define GFX_CLK_FORCE_ON                           (1 << 8)

#       define GFX_CLK_REQUEST_OFF                        (1 << 9)

#       define GFX_CLK_FORCE_OFF                          (1 << 10)

#       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)

#       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)

#       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)

#       define CURRENT_STATE_INDEX_MASK                   (0xf << 4)

#       define CURRENT_STATE_INDEX_SHIFT                  4

#define CG_FFCT_0                                         0x7c0

#       define UTC_0(x)                                   ((x) << 0)

#       define UTC_0_MASK                                 (0x3ff << 0)

#       define DTC_0_MASK                                 (0x3ff << 10)

#define CG_BSP                                          0x7fc

#       define BSP(x)					((x) << 0)

#       define BSP_MASK					(0xffff << 0)

#       define BSU(x)					((x) << 16)

#       define CG_R(x)					((x) << 0)

#       define CG_R_MASK				(0xffff << 0)

#define CG_GIT                                          0x804

#       define CG_GICST_MASK                            (0xffff << 0)

#       define CG_GIPOT(x)                              ((x) << 16)

#define CG_SSP                                            0x80c

#       define SST(x)                                     ((x) << 0)

#       define SST_MASK                                   (0xffff << 0)

#       define SSTU(x)                                    ((x) << 16)

#       define SSTU_MASK                                  (0xf << 16)

#define CG_DISPLAY_GAP_CNTL                               0x828

#       define DISP1_GAP(x)                               ((x) << 0)

#       define DISP1_GAP_MASK                             (3 << 0)

#       define DISP2_GAP_MASK                             (3 << 2)

#       define VBI_TIMER_COUNT(x)                         ((x) << 4)

#       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)

#       define VBI_TIMER_UNIT(x)                          ((x) << 20)

#       define VBI_TIMER_UNIT_MASK                        (7 << 20)

#       define DISP1_GAP_MCHG(x)                          ((x) << 24)

#       define DISP1_GAP_MCHG_MASK                        (3 << 24)

#       define DISP2_GAP_MCHG(x)                          ((x) << 26)

#       define DISP2_GAP_MCHG_MASK                        (3 << 26)

#define	CG_ULV_CONTROL					0x878

#define	CG_ULV_PARAMETER				0x87c

#define	SMC_SCRATCH0					0x884

#define	CG_CAC_CTRL					0x8b8

#define DMIF_ADDR_CONFIG  				0xBD4

#define DMIF_ADDR_CALC  				0xC00

#define		PAGE_TABLE_BLOCK_SIZE(x)			(((x) & 0xF) << 24)

#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC

#define		PROTECTIONS_MASK			(0xf << 0)

#define		PROTECTIONS_SHIFT			0

		/* bit 0: range

		 * bit 1: pde0

		 * bit 2: valid

		 * bit 3: read

		 * bit 4: write

		 */

#define		MEMORY_CLIENT_ID_MASK			(0xff << 12)

#define		MEMORY_CLIENT_ID_SHIFT			12

#define		MEMORY_CLIENT_RW_MASK			(1 << 24)

#define		MEMORY_CLIENT_RW_SHIFT			24

#define		FAULT_VMID_MASK				(0xf << 25)

#define	VM_CONTEXT1_PAGE_TABLE_END_ADDR			0x1580

#define VM_L2_CG           				0x15c0

#define		MC_CG_ENABLE				(1 << 18)

#define MC_SHARED_BLACKOUT_CNTL           		0x20ac

#define MC_HUB_MISC_HUB_CG           			0x20b8

#define MC_HUB_MISC_VM_CG           			0x20bc

#define MC_HUB_MISC_SIP_CG           			0x20c0

#define MC_XPB_CLK_GAT           			0x2478

#define MC_CITF_MISC_RD_CG           			0x2648

#define MC_CITF_MISC_WR_CG           			0x264c

#define	MC_ARB_DRAM_TIMING				0x2774

#define	MC_ARB_DRAM_TIMING2				0x2778

#define MC_ARB_BURST_TIME                               0x2808

#define		STATE0(x)				((x) << 0)

#define		STATE0_MASK				(0x1f << 0)

#define		STATE0_SHIFT				0

#define		STATE1(x)				((x) << 5)

#define		STATE1_MASK				(0x1f << 5)

#define		STATE1_SHIFT				5

#define		STATE2(x)				((x) << 10)

#define		STATE2_MASK				(0x1f << 10)

#define		STATE2_SHIFT				10

#define		STATE3(x)				((x) << 15)

#define		STATE3_MASK				(0x1f << 15)

#define		STATE3_SHIFT				15

#define		RUN_MASK      				(1 << 0)

#define MC_IO_PAD_CNTL_D0           			0x29d0

#define		MEM_FALL_OUT_CMD      			(1 << 8)

#define MC_SEQ_RAS_TIMING                               0x28a0

#define MC_SEQ_CAS_TIMING                               0x28a4

#define MC_SEQ_MISC_TIMING                              0x28a8

#define MC_SEQ_MISC_TIMING2                             0x28ac

#define MC_SEQ_PMG_TIMING                               0x28b0

#define MC_SEQ_RD_CTL_D0                                0x28b4

#define MC_SEQ_RD_CTL_D1                                0x28b8

#define MC_SEQ_WR_CTL_D0                                0x28bc

#define MC_SEQ_WR_CTL_D1                                0x28c0

#define MC_SEQ_MISC0           				0x2a00

#define 	MC_SEQ_MISC0_VEN_ID_SHIFT               8

#define 	MC_SEQ_MISC0_VEN_ID_MASK                0x00000f00

#define 	MC_SEQ_MISC0_VEN_ID_VALUE               3

#define 	MC_SEQ_MISC0_REV_ID_SHIFT               12

#define 	MC_SEQ_MISC0_REV_ID_MASK                0x0000f000

#define 	MC_SEQ_MISC0_REV_ID_VALUE               1

#define 	MC_SEQ_MISC0_GDDR5_SHIFT                28

#define 	MC_SEQ_MISC0_GDDR5_MASK                 0xf0000000

#define 	MC_SEQ_MISC0_GDDR5_VALUE                5

#define MC_PMG_CMD_EMRS                                 0x2a0c

#define MC_SEQ_IO_DEBUG_INDEX           		0x2a44

#define MC_SEQ_IO_DEBUG_DATA           			0x2a48

#define MC_SEQ_MISC5                                    0x2a54

#define MC_SEQ_MISC6                                    0x2a58

#define MC_SEQ_MISC7                                    0x2a64

#define MC_SEQ_RAS_TIMING_LP                            0x2a6c

#define MC_SEQ_CAS_TIMING_LP                            0x2a70

#define MC_SEQ_MISC_TIMING_LP                           0x2a74

#define MC_SEQ_MISC_TIMING2_LP                          0x2a78

#define MC_SEQ_WR_CTL_D0_LP                             0x2a7c

#define MC_SEQ_WR_CTL_D1_LP                             0x2a80

#define MC_SEQ_PMG_CMD_EMRS_LP                          0x2a84

#define MC_SEQ_PMG_CMD_MRS_LP                           0x2a88

#define MC_PMG_CMD_MRS                                  0x2aac

#define MC_SEQ_RD_CTL_D0_LP                             0x2b1c

#define MC_SEQ_RD_CTL_D1_LP                             0x2b20

#define MC_PMG_CMD_MRS1                                 0x2b44

#define MC_SEQ_PMG_CMD_MRS1_LP                          0x2b48

#define MC_SEQ_PMG_TIMING_LP                            0x2b4c

#define MC_SEQ_WR_CTL_2                                 0x2b54

#define MC_SEQ_WR_CTL_2_LP                              0x2b58

#define MC_PMG_CMD_MRS2                                 0x2b5c

#define MC_SEQ_PMG_CMD_MRS2_LP                          0x2b60

#define	MCLK_PWRMGT_CNTL				0x2ba0

#       define DLL_SPEED(x)				((x) << 0)

#       define DLL_SPEED_MASK				(0x1f << 0)

#       define DLL_READY                                (1 << 6)

#       define MC_INT_CNTL                              (1 << 7)

#       define MRDCK0_PDNB                              (1 << 8)

#       define MRDCK1_PDNB                              (1 << 9)

#       define MRDCK0_RESET                             (1 << 16)

#       define MRDCK1_RESET                             (1 << 17)

#       define DLL_READY_READ                           (1 << 24)

#define	DLL_CNTL					0x2ba4

#       define MRDCK0_BYPASS                            (1 << 24)

#       define MRDCK1_BYPASS                            (1 << 25)

#define	MPLL_CNTL_MODE					0x2bb0

#       define MPLL_MCLK_SEL                            (1 << 11)

#define	MPLL_FUNC_CNTL					0x2bb4

#define		BWCTRL(x)				((x) << 20)

#define		BWCTRL_MASK				(0xff << 20)

#define	MPLL_FUNC_CNTL_1				0x2bb8

#define		VCO_MODE(x)				((x) << 0)

#define		VCO_MODE_MASK				(3 << 0)

#define		CLKFRAC(x)				((x) << 4)

#define		CLKFRAC_MASK				(0xfff << 4)

#define		CLKF(x)					((x) << 16)

#define		CLKF_MASK				(0xfff << 16)

#define	MPLL_FUNC_CNTL_2				0x2bbc

#define	MPLL_AD_FUNC_CNTL				0x2bc0

#define		YCLK_POST_DIV(x)			((x) << 0)

#define		YCLK_POST_DIV_MASK			(7 << 0)

#define	MPLL_DQ_FUNC_CNTL				0x2bc4

#define		YCLK_SEL(x)				((x) << 4)

#define		YCLK_SEL_MASK				(1 << 4)

#define	MPLL_SS1					0x2bcc

#define		CLKV(x)					((x) << 0)

#define	MPLL_SS2					0x2bd0

#define	HDP_NONSURFACE_INFO				0x2C08

#define	HDP_NONSURFACE_SIZE				0x2C0C

#define HDP_ADDR_CONFIG  				0x2F48

#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0

/* DCE6 ELD audio interface */

#define AZ_F0_CODEC_ENDPOINT_INDEX                       0x5E00

#       define AZ_ENDPOINT_REG_INDEX(x)                  (((x) & 0xff) << 0)

#       define AZ_ENDPOINT_REG_WRITE_EN                  (1 << 8)

#define AZ_F0_CODEC_ENDPOINT_DATA                        0x5E04

#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER          0x25

#define		SPEAKER_ALLOCATION(x)			(((x) & 0x7f) << 0)

#define		SPEAKER_ALLOCATION_MASK			(0x7f << 0)

#define		SPEAKER_ALLOCATION_SHIFT		0

#define		HDMI_CONNECTION				(1 << 16)

#define		DP_CONNECTION				(1 << 17)

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0        0x28 /* LPCM */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1        0x29 /* AC3 */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2        0x2A /* MPEG1 */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3        0x2B /* MP3 */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4        0x2C /* MPEG2 */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5        0x2D /* AAC */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6        0x2E /* DTS */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7        0x2F /* ATRAC */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8        0x30 /* one bit audio - leave at 0 (default) */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9        0x31 /* Dolby Digital */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10       0x32 /* DTS-HD */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11       0x33 /* MAT-MLP */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12       0x34 /* DTS */

#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13       0x35 /* WMA Pro */

#       define MAX_CHANNELS(x)                            (((x) & 0x7) << 0)

/* max channels minus one.  7 = 8 channels */

#       define SUPPORTED_FREQUENCIES(x)                   (((x) & 0xff) << 8)

#       define DESCRIPTOR_BYTE_2(x)                       (((x) & 0xff) << 16)

#       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) & 0xff) << 24) /* LPCM only */

/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO

 * bit0 = 32 kHz

 * bit1 = 44.1 kHz

 * bit2 = 48 kHz

 * bit3 = 88.2 kHz

 * bit4 = 96 kHz

 * bit5 = 176.4 kHz

 * bit6 = 192 kHz

 */

#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC         0x37

#       define VIDEO_LIPSYNC(x)                           (((x) & 0xff) << 0)

#       define AUDIO_LIPSYNC(x)                           (((x) & 0xff) << 8)

/* VIDEO_LIPSYNC, AUDIO_LIPSYNC

 * 0   = invalid

 * x   = legal delay value

 * 255 = sync not supported

 */

#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR             0x38

#       define HBR_CAPABLE                                (1 << 0) /* enabled by default */

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0               0x3a

#       define MANUFACTURER_ID(x)                        (((x) & 0xffff) << 0)

#       define PRODUCT_ID(x)                             (((x) & 0xffff) << 16)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1               0x3b

#       define SINK_DESCRIPTION_LEN(x)                   (((x) & 0xff) << 0)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2               0x3c

#       define PORT_ID0(x)                               (((x) & 0xffffffff) << 0)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3               0x3d

#       define PORT_ID1(x)                               (((x) & 0xffffffff) << 0)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4               0x3e

#       define DESCRIPTION0(x)                           (((x) & 0xff) << 0)

#       define DESCRIPTION1(x)                           (((x) & 0xff) << 8)

#       define DESCRIPTION2(x)                           (((x) & 0xff) << 16)

#       define DESCRIPTION3(x)                           (((x) & 0xff) << 24)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5               0x3f

#       define DESCRIPTION4(x)                           (((x) & 0xff) << 0)

#       define DESCRIPTION5(x)                           (((x) & 0xff) << 8)

#       define DESCRIPTION6(x)                           (((x) & 0xff) << 16)

#       define DESCRIPTION7(x)                           (((x) & 0xff) << 24)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6               0x40

#       define DESCRIPTION8(x)                           (((x) & 0xff) << 0)

#       define DESCRIPTION9(x)                           (((x) & 0xff) << 8)

#       define DESCRIPTION10(x)                          (((x) & 0xff) << 16)

#       define DESCRIPTION11(x)                          (((x) & 0xff) << 24)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7               0x41

#       define DESCRIPTION12(x)                          (((x) & 0xff) << 0)

#       define DESCRIPTION13(x)                          (((x) & 0xff) << 8)

#       define DESCRIPTION14(x)                          (((x) & 0xff) << 16)

#       define DESCRIPTION15(x)                          (((x) & 0xff) << 24)

#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8               0x42

#       define DESCRIPTION16(x)                          (((x) & 0xff) << 0)

#       define DESCRIPTION17(x)                          (((x) & 0xff) << 8)

#define AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL          0x54

#       define AUDIO_ENABLED                             (1 << 31)

#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT  0x56

#define		PORT_CONNECTIVITY_MASK				(3 << 30)

#define DPG_PIPE_STUTTER_CONTROL                          0x6cd4

#       define STUTTER_ENABLE                             (1 << 0)

#define CRTC_STATUS_FRAME_COUNT                         0x6e98

#define AFMT_AUDIO_SRC_CONTROL                          0x713c

#define		AFMT_AUDIO_SRC_SELECT(x)		(((x) & 7) << 0)

/* AFMT_AUDIO_SRC_SELECT

 * 0 = stream0

 * 1 = stream1

 * 2 = stream2

 * 3 = stream3

 * 4 = stream4

 * 5 = stream5

#define	SQC_CACHES					0x8C08

#define SQ_POWER_THROTTLE                               0x8e58

#define		MIN_POWER(x)				((x) << 0)

#define		MIN_POWER_MASK				(0x3fff << 0)

#define		MIN_POWER_SHIFT				0

#define		MAX_POWER(x)				((x) << 16)

#define		MAX_POWER_MASK				(0x3fff << 16)

#define		MAX_POWER_SHIFT				0

#define SQ_POWER_THROTTLE2                              0x8e5c

#define		MAX_POWER_DELTA(x)			((x) << 0)

#define		MAX_POWER_DELTA_MASK			(0x3fff << 0)

#define		MAX_POWER_DELTA_SHIFT			0

#define		STI_SIZE(x)				((x) << 16)

#define		STI_SIZE_MASK				(0x3ff << 16)

#define		STI_SIZE_SHIFT				16

#define		LTI_RATIO(x)				((x) << 27)

#define		TCC_DISABLE_SHIFT				16

#define	CGTS_SM_CTRL_REG				0x9150

#define		OVERRIDE				(1 << 21)

#define		LS_OVERRIDE				(1 << 22)

#define	CB_CGTT_SCLK_CTRL				0x9a60

#define	CP_MEM_SLP_CNTL					0xC1E4

#       define CP_MEM_LS_EN                             (1 << 0)

#define RLC_RL_SIZE                                       0xC308

#define RLC_STAT                                          0xC34C

#       define RLC_BUSY_STATUS                            (1 << 0)

#       define GFX_POWER_STATUS                           (1 << 1)

#       define GFX_CLOCK_STATUS                           (1 << 2)

#       define GFX_LS_STATUS                              (1 << 3)

#define	RLC_PG_CNTL					0xC35C

#	define GFX_PG_ENABLE				(1 << 0)

#	define GFX_PG_SRC				(1 << 1)

#define	RLC_CGTT_MGCG_OVERRIDE				0xC400

#define	RLC_CGCG_CGLS_CTRL				0xC404

#	define CGCG_EN					(1 << 0)

#	define CGLS_EN					(1 << 1)

#define	RLC_TTOP_D					0xC414

#	define RLC_PUD(x)				((x) << 0)

#	define RLC_PUD_MASK				(0xff << 0)

#	define RLC_PDD(x)				((x) << 8)

#	define RLC_PDD_MASK				(0xff << 8)

#	define RLC_TTPD(x)				((x) << 16)

#	define RLC_TTPD_MASK				(0xff << 16)

#	define RLC_MSD(x)				((x) << 24)

#	define RLC_MSD_MASK				(0xff << 24)

#define RLC_LB_INIT_CU_MASK                               0xC41C

#define	RLC_PG_AO_CU_MASK				0xC42C

#define	RLC_MAX_PG_CU					0xC430

#	define MAX_PU_CU(x)				((x) << 0)

#	define MAX_PU_CU_MASK				(0xff << 0)

#define	RLC_AUTO_PG_CTRL				0xC434

#	define AUTO_PG_EN				(1 << 0)

#	define GRBM_REG_SGIT(x)				((x) << 3)

#	define GRBM_REG_SGIT_MASK			(0xffff << 3)

#	define PG_AFTER_GRBM_REG_ST(x)			((x) << 19)

#	define PG_AFTER_GRBM_REG_ST_MASK		(0x1fff << 19)

#define RLC_SERDES_WR_MASTER_MASK_0                       0xC454

#define RLC_SERDES_WR_MASTER_MASK_1                       0xC458

#define RLC_SERDES_WR_CTRL                                0xC45C

#define RLC_SERDES_MASTER_BUSY_0                          0xC464

#define RLC_SERDES_MASTER_BUSY_1                          0xC468

#define RLC_GCPM_GENERAL_3                                0xC478

#define	DB_RENDER_CONTROL				0x28000

#define DB_DEPTH_INFO                                   0x2803c

/* PIF PHY0 registers idx/data 0x8/0xc */

#define PB0_PIF_CNTL                                      0x10

#       define LS2_EXIT_TIME(x)                           ((x) << 17)

#       define LS2_EXIT_TIME_MASK                         (0x7 << 17)

#       define LS2_EXIT_TIME_SHIFT                        17

#define PB0_PIF_PAIRING                                   0x11

#       define MULTI_PIF                                  (1 << 25)

#define PB0_PIF_PWRDOWN_0                                 0x12

#       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) << 7)

#       define PLL_POWER_STATE_IN_TXS2_0_MASK             (0x7 << 7)

#       define PLL_POWER_STATE_IN_TXS2_0_SHIFT            7

#       define PLL_POWER_STATE_IN_OFF_0(x)                ((x) << 10)

#       define PLL_POWER_STATE_IN_OFF_0_MASK              (0x7 << 10)

#       define PLL_POWER_STATE_IN_OFF_0_SHIFT             10

#       define PLL_RAMP_UP_TIME_0(x)                      ((x) << 24)

#       define PLL_RAMP_UP_TIME_0_MASK                    (0x7 << 24)

#       define PLL_RAMP_UP_TIME_0_SHIFT                   24

#define PB0_PIF_PWRDOWN_1                                 0x13

#       define PLL_POWER_STATE_IN_TXS2_1(x)               ((x) << 7)

#       define PLL_POWER_STATE_IN_TXS2_1_MASK             (0x7 << 7)

#       define PLL_POWER_STATE_IN_TXS2_1_SHIFT            7

#       define PLL_POWER_STATE_IN_OFF_1(x)                ((x) << 10)

#       define PLL_POWER_STATE_IN_OFF_1_MASK              (0x7 << 10)

#       define PLL_POWER_STATE_IN_OFF_1_SHIFT             10

#       define PLL_RAMP_UP_TIME_1(x)                      ((x) << 24)

#       define PLL_RAMP_UP_TIME_1_MASK                    (0x7 << 24)

#       define PLL_RAMP_UP_TIME_1_SHIFT                   24

#define PB0_PIF_PWRDOWN_2                                 0x17

#       define PLL_POWER_STATE_IN_TXS2_2(x)               ((x) << 7)

#       define PLL_POWER_STATE_IN_TXS2_2_MASK             (0x7 << 7)

#       define PLL_POWER_STATE_IN_TXS2_2_SHIFT            7

#       define PLL_POWER_STATE_IN_OFF_2(x)                ((x) << 10)

#       define PLL_POWER_STATE_IN_OFF_2_MASK              (0x7 << 10)

#       define PLL_POWER_STATE_IN_OFF_2_SHIFT             10

#       define PLL_RAMP_UP_TIME_2(x)                      ((x) << 24)

#       define PLL_RAMP_UP_TIME_2_MASK                    (0x7 << 24)

#       define PLL_RAMP_UP_TIME_2_SHIFT                   24

#define PB0_PIF_PWRDOWN_3                                 0x18

#       define PLL_POWER_STATE_IN_TXS2_3(x)               ((x) << 7)

#       define PLL_POWER_STATE_IN_TXS2_3_MASK             (0x7 << 7)

#       define PLL_POWER_STATE_IN_TXS2_3_SHIFT            7

#       define PLL_POWER_STATE_IN_OFF_3(x)                ((x) << 10)

#       define PLL_POWER_STATE_IN_OFF_3_MASK              (0x7 << 10)

#       define PLL_POWER_STATE_IN_OFF_3_SHIFT             10

#       define PLL_RAMP_UP_TIME_3(x)                      ((x) << 24)

#       define PLL_RAMP_UP_TIME_3_MASK                    (0x7 << 24)

#       define PLL_RAMP_UP_TIME_3_SHIFT                   24

/* PIF PHY1 registers idx/data 0x10/0x14 */

#define PB1_PIF_CNTL                                      0x10

#define PB1_PIF_PAIRING                                   0x11

#define PB1_PIF_PWRDOWN_0                                 0x12

#define PB1_PIF_PWRDOWN_1                                 0x13

#define PB1_PIF_PWRDOWN_2                                 0x17

#define PB1_PIF_PWRDOWN_3                                 0x18

/* PCIE registers idx/data 0x30/0x34 */

#define PCIE_CNTL2                                        0x1c /* PCIE */

#       define SLV_MEM_LS_EN                              (1 << 16)

#       define SLV_MEM_AGGRESSIVE_LS_EN                   (1 << 17)

#       define MST_MEM_LS_EN                              (1 << 18)

#       define REPLAY_MEM_LS_EN                           (1 << 19)

#define PCIE_LC_STATUS1                                   0x28 /* PCIE */

#       define LC_REVERSE_RCVR                            (1 << 0)

#       define LC_REVERSE_XMIT                            (1 << 1)

#       define LC_OPERATING_LINK_WIDTH_MASK               (0x7 << 2)

#       define LC_OPERATING_LINK_WIDTH_SHIFT              2

#       define LC_DETECTED_LINK_WIDTH_MASK                (0x7 << 5)

#       define LC_DETECTED_LINK_WIDTH_SHIFT               5

#define PCIE_P_CNTL                                       0x40 /* PCIE */

#       define P_IGNORE_EDB_ERR                           (1 << 6)

/* PCIE PORT registers idx/data 0x38/0x3c */

#define PCIE_LC_CNTL                                      0xa0

#       define LC_L0S_INACTIVITY(x)                       ((x) << 8)

#       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)

#       define LC_L0S_INACTIVITY_SHIFT                    8

#       define LC_L1_INACTIVITY(x)                        ((x) << 12)

#       define LC_L1_INACTIVITY_MASK                      (0xf << 12)

#       define LC_L1_INACTIVITY_SHIFT                     12

#       define LC_PMI_TO_L1_DIS                           (1 << 16)

#       define LC_ASPM_TO_L1_DIS                          (1 << 24)

#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */

#       define LC_LINK_WIDTH_SHIFT                        0

#       define LC_LINK_WIDTH_MASK                         0x7

#       define LC_LINK_WIDTH_X0                           0

#       define LC_LINK_WIDTH_X1                           1

#       define LC_LINK_WIDTH_X2                           2

#       define LC_LINK_WIDTH_X4                           3

#       define LC_LINK_WIDTH_X8                           4

#       define LC_LINK_WIDTH_X16                          6

#       define LC_LINK_WIDTH_RD_SHIFT                     4

#       define LC_LINK_WIDTH_RD_MASK                      0x70

#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)

#       define LC_RECONFIG_NOW                            (1 << 8)

#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)

#       define LC_RENEGOTIATE_EN                          (1 << 10)

#       define LC_SHORT_RECONFIG_EN                       (1 << 11)

#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)

#       define LC_UPCONFIGURE_DIS                         (1 << 13)

#       define LC_DYN_LANES_PWR_STATE(x)                  ((x) << 21)

#       define LC_DYN_LANES_PWR_STATE_MASK                (0x3 << 21)

#       define LC_DYN_LANES_PWR_STATE_SHIFT               21

#define PCIE_LC_N_FTS_CNTL                                0xa3 /* PCIE_P */

#       define LC_XMIT_N_FTS(x)                           ((x) << 0)

#       define LC_XMIT_N_FTS_MASK                         (0xff << 0)

#       define LC_XMIT_N_FTS_SHIFT                        0

#       define LC_XMIT_N_FTS_OVERRIDE_EN                  (1 << 8)

#       define LC_N_FTS_MASK                              (0xff << 24)

#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */

#       define LC_GEN2_EN_STRAP                           (1 << 0)

#       define LC_GEN3_EN_STRAP                           (1 << 1)

#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 2)

#       define LC_TARGET_LINK_SPEED_OVERRIDE_MASK         (0x3 << 3)

#       define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT        3

#       define LC_FORCE_EN_SW_SPEED_CHANGE                (1 << 5)

#       define LC_FORCE_DIS_SW_SPEED_CHANGE               (1 << 6)

#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 7)

#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 8)

#       define LC_INITIATE_LINK_SPEED_CHANGE              (1 << 9)

#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 10)

#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     10

#       define LC_CURRENT_DATA_RATE_MASK                  (0x3 << 13) /* 0/1/2 = gen1/2/3 */

#       define LC_CURRENT_DATA_RATE_SHIFT                 13

#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 16)

#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 18)

#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 19)

#       define LC_OTHER_SIDE_EVER_SENT_GEN3               (1 << 20)

#       define LC_OTHER_SIDE_SUPPORTS_GEN3                (1 << 21)

#define PCIE_LC_CNTL2                                     0xb1

#       define LC_ALLOW_PDWN_IN_L1                        (1 << 17)

#       define LC_ALLOW_PDWN_IN_L23                       (1 << 18)

#define PCIE_LC_CNTL3                                     0xb5 /* PCIE_P */

#       define LC_GO_TO_RECOVERY                          (1 << 30)

#define PCIE_LC_CNTL4                                     0xb6 /* PCIE_P */

#       define LC_REDO_EQ                                 (1 << 5)

#       define LC_SET_QUIESCE                             (1 << 13)

#define UVD_RBC_RB_WPTR					0xF694

#define	UVD_CGC_CTRL					0xF4B0

#	define DCM					(1 << 0)

#	define CG_DT(x)					((x) << 2)

#	define CG_DT_MASK				(0xf << 2)

#	define CLK_OD(x)				((x) << 6)

#	define CLK_OD_MASK				(0x1f << 6)

 /* UVD CTX indirect */

#define	UVD_CGC_MEM_CTRL				0xC0

#define	UVD_CGC_CTRL2					0xC1

#	define DYN_OR_EN				(1 << 0)

#	define DYN_RR_EN				(1 << 1)

#	define G_DIV_ID(x)				((x) << 2)

#define	DMA_POWER_CNTL					0xd0bc

#       define MEM_POWER_OVERRIDE                       (1 << 8)

#define	DMA_CLK_CTRL					0xd0c0

#define	DMA_PG						0xd0d4

#	define PG_CNTL_ENABLE				(1 << 0)

#define	DMA_PGFSM_CONFIG				0xd0d8

#define	DMA_PGFSM_WRITE					0xd0dc

#define VCE_STATUS					0x20004

#define VCE_VCPU_CNTL					0x20014

#define		VCE_CLK_EN				(1 << 0)

#define VCE_VCPU_CACHE_OFFSET0				0x20024

#define VCE_VCPU_CACHE_SIZE0				0x20028

#define VCE_VCPU_CACHE_OFFSET1				0x2002c

#define VCE_VCPU_CACHE_SIZE1				0x20030

#define VCE_VCPU_CACHE_OFFSET2				0x20034

#define VCE_VCPU_CACHE_SIZE2				0x20038

#define VCE_SOFT_RESET					0x20120

#define 	VCE_ECPU_SOFT_RESET			(1 << 0)

#define 	VCE_FME_SOFT_RESET			(1 << 2)

#define VCE_RB_BASE_LO2					0x2016c

#define VCE_RB_BASE_HI2					0x20170

#define VCE_RB_SIZE2					0x20174

#define VCE_RB_RPTR2					0x20178

#define VCE_RB_WPTR2					0x2017c

#define VCE_RB_BASE_LO					0x20180

#define VCE_RB_BASE_HI					0x20184

#define VCE_RB_SIZE					0x20188

#define VCE_RB_RPTR					0x2018c

#define VCE_RB_WPTR					0x20190

#define VCE_CLOCK_GATING_A				0x202f8

#define VCE_CLOCK_GATING_B				0x202fc

#define VCE_UENC_CLOCK_GATING				0x205bc

#define VCE_UENC_REG_CLOCK_GATING			0x205c0

#define VCE_FW_REG_STATUS				0x20e10

#	define VCE_FW_REG_STATUS_BUSY			(1 << 0)

#	define VCE_FW_REG_STATUS_PASS			(1 << 3)

#	define VCE_FW_REG_STATUS_DONE			(1 << 11)

#define VCE_LMI_FW_START_KEYSEL				0x20e18

#define VCE_LMI_FW_PERIODIC_CTRL			0x20e20

#define VCE_LMI_CTRL2					0x20e74

#define VCE_LMI_CTRL					0x20e98

#define VCE_LMI_VM_CTRL					0x20ea0

#define VCE_LMI_SWAP_CNTL				0x20eb4

#define VCE_LMI_SWAP_CNTL1				0x20eb8

#define VCE_LMI_CACHE_CTRL				0x20ef4

#define VCE_CMD_NO_OP					0x00000000

#define VCE_CMD_END					0x00000001

#define VCE_CMD_IB					0x00000002

#define VCE_CMD_FENCE					0x00000003

#define VCE_CMD_TRAP					0x00000004

#define VCE_CMD_IB_AUTO					0x00000005

#define VCE_CMD_SEMAPHORE				0x00000006