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#define	SRBM_STATUS				        0xE50

#define	SRBM_SOFT_RESET				        0x0E60

#define		SOFT_RESET_BIF				(1 << 1)

#define		SOFT_RESET_DC				(1 << 5)

#define		SOFT_RESET_DMA1				(1 << 6)

#define		SOFT_RESET_GRBM				(1 << 8)

#define		SOFT_RESET_HDP				(1 << 9)

#define		SOFT_RESET_IH				(1 << 10)

#define		SOFT_RESET_MC				(1 << 11)

#define		SOFT_RESET_ROM				(1 << 14)

#define		SOFT_RESET_SEM				(1 << 15)

#define		SOFT_RESET_VMC				(1 << 17)

#define		SOFT_RESET_DMA				(1 << 20)

#define		SOFT_RESET_TST				(1 << 21)

#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)

#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)

#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)

#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)

#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)

#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)

#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)

#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)

#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)

#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)

#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)

#define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x14FC

#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC

#define	PACKET3_CP_DMA					0x41

/* 1. header

 * 2. SRC_ADDR_LO or DATA [31:0]

 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |

 *    SRC_ADDR_HI [7:0]

 * 4. DST_ADDR_LO [31:0]

 * 5. DST_ADDR_HI [7:0]

 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]

 */

#              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)

                /* 0 - SRC_ADDR

		 * 1 - GDS

		 */

#              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)

                /* 0 - ME

		 * 1 - PFP

		 */

#              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)

                /* 0 - SRC_ADDR

		 * 1 - GDS

		 * 2 - DATA

		 */

#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)

/* COMMAND */

#              define PACKET3_CP_DMA_DIS_WC        (1 << 21)

#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)

#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)

#              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 << 30)

/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */

#define DMA0_REGISTER_OFFSET                              0x0 /* not a register */

#define DMA1_REGISTER_OFFSET                              0x800 /* not a register */

#define DMA_RB_CNTL                                       0xd000

#       define DMA_RB_ENABLE                              (1 << 0)

#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */

#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */

#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)

#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */

#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */

#define DMA_RB_BASE                                       0xd004

#define DMA_RB_RPTR                                       0xd008

#define DMA_RB_WPTR                                       0xd00c

#define DMA_RB_RPTR_ADDR_HI                               0xd01c

#define DMA_RB_RPTR_ADDR_LO                               0xd020

#define DMA_IB_CNTL                                       0xd024

#       define DMA_IB_ENABLE                              (1 << 0)

#       define DMA_IB_SWAP_ENABLE                         (1 << 4)

#define DMA_IB_RPTR                                       0xd028

#define DMA_CNTL                                          0xd02c

#       define TRAP_ENABLE                                (1 << 0)

#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)

#       define SEM_WAIT_INT_ENABLE                        (1 << 2)

#       define DATA_SWAP_ENABLE                           (1 << 3)

#       define FENCE_SWAP_ENABLE                          (1 << 4)

#       define CTXEMPTY_INT_ENABLE                        (1 << 28)

#define DMA_STATUS_REG                                    0xd034

#       define DMA_IDLE                                   (1 << 0)

#define DMA_TILING_CONFIG  				  0xd0b8

#define DMA_PACKET(cmd, b, t, s, n)	((((cmd) & 0xF) << 28) |	\

					 (((b) & 0x1) << 26) |		\

					 (((t) & 0x1) << 23) |		\

					 (((s) & 0x1) << 22) |		\

					 (((n) & 0xFFFFF) << 0))

#define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\

					 (((vmid) & 0xF) << 20) |	\

					 (((n) & 0xFFFFF) << 0))

#define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\

					 (1 << 26) |			\

					 (1 << 21) |			\

					 (((n) & 0xFFFFF) << 0))

/* async DMA Packet types */

#define	DMA_PACKET_WRITE				  0x2

#define	DMA_PACKET_COPY					  0x3

#define	DMA_PACKET_INDIRECT_BUFFER			  0x4

#define	DMA_PACKET_SEMAPHORE				  0x5

#define	DMA_PACKET_FENCE				  0x6

#define	DMA_PACKET_TRAP					  0x7

#define	DMA_PACKET_SRBM_WRITE				  0x9

#define	DMA_PACKET_CONSTANT_FILL			  0xd

#define	DMA_PACKET_NOP					  0xf