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Rev 5078 Rev 5271
Line 183... Line 183...
183
			addr += (ndw / 2) * incr;
183
			addr += (ndw / 2) * incr;
184
			count -= ndw / 2;
184
			count -= ndw / 2;
185
		}
185
		}
186
}
186
}
Line 187... Line 187...
187
 
187
 
188
void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
-
 
189
{
188
void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
190
	struct radeon_ring *ring = &rdev->ring[ridx];
-
 
191
 
-
 
192
	if (vm == NULL)
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Line -... Line 189...
-
 
189
		     unsigned vm_id, uint64_t pd_addr)
193
		return;
190
 
194
 
191
{
195
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
192
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
196
	if (vm->id < 8) {
193
	if (vm_id < 8) {
197
		radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
194
		radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));
198
	} else {
195
	} else {
199
		radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
196
		radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2));
Line 200... Line 197...
200
	}
197
	}
201
	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
198
	radeon_ring_write(ring, pd_addr >> 12);
202
 
199
 
203
	/* flush hdp cache */
200
	/* flush hdp cache */
Line 204... Line 201...
204
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
201
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
205
	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
202
	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
206
	radeon_ring_write(ring, 1);
203
	radeon_ring_write(ring, 1);
207
 
204
 
208
	/* bits 0-7 are the VM contexts0-7 */
205
	/* bits 0-7 are the VM contexts0-7 */
Line 209... Line 206...
209
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
206
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
210
	radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
207
	radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
211
	radeon_ring_write(ring, 1 << vm->id);
208
	radeon_ring_write(ring, 1 << vm_id);
212
}
209
}
213
 
210
 
214
/**
211
/**
215
 * si_copy_dma - copy pages using the DMA engine
212
 * si_copy_dma - copy pages using the DMA engine
216
 *
213
 *
217
 * @rdev: radeon_device pointer
214
 * @rdev: radeon_device pointer
218
 * @src_offset: src GPU address
215
 * @src_offset: src GPU address
219
 * @dst_offset: dst GPU address
216
 * @dst_offset: dst GPU address
220
 * @num_gpu_pages: number of GPU pages to xfer
217
 * @num_gpu_pages: number of GPU pages to xfer
221
 * @fence: radeon fence object
218
 * @resv: reservation object to sync to
222
 *
219
 *
223
 * Copy GPU paging using the DMA engine (SI).
220
 * Copy GPU paging using the DMA engine (SI).
224
 * Used by the radeon ttm implementation to move pages if
221
 * Used by the radeon ttm implementation to move pages if
225
 * registered as the asic copy callback.
222
 * registered as the asic copy callback.
226
 */
223
 */
227
int si_copy_dma(struct radeon_device *rdev,
224
struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
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225
		uint64_t src_offset, uint64_t dst_offset,
228
		uint64_t src_offset, uint64_t dst_offset,
226
		unsigned num_gpu_pages,
229
		unsigned num_gpu_pages,
227
				 struct reservation_object *resv)
230
		struct radeon_fence **fence)
228
{
231
{
229
	struct radeon_fence *fence;
232
	struct radeon_semaphore *sem = NULL;
230
	struct radeon_sync sync;
Line 233... Line 231...
233
	int ring_index = rdev->asic->copy.dma_ring_index;
231
	int ring_index = rdev->asic->copy.dma_ring_index;
234
	struct radeon_ring *ring = &rdev->ring[ring_index];
-
 
235
	u32 size_in_bytes, cur_size_in_bytes;
-
 
236
	int i, num_loops;
-
 
237
	int r = 0;
-
 
Line 238... Line 232...
238
 
232
	struct radeon_ring *ring = &rdev->ring[ring_index];
239
	r = radeon_semaphore_create(rdev, &sem);
233
	u32 size_in_bytes, cur_size_in_bytes;
240
	if (r) {
234
	int i, num_loops;
241
		DRM_ERROR("radeon: moving bo (%d).\n", r);
235
	int r = 0;
242
		return r;
236
 
243
	}
237
	radeon_sync_create(&sync);
244
 
238
 
245
	size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
239
	size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
Line 246... Line 240...
246
	num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
240
	num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
247
	r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
241
	r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
Line 248... Line 242...
248
	if (r) {
242
	if (r) {
249
		DRM_ERROR("radeon: moving bo (%d).\n", r);
243
		DRM_ERROR("radeon: moving bo (%d).\n", r);
250
		radeon_semaphore_free(rdev, &sem, NULL);
244
		radeon_sync_free(rdev, &sync, NULL);
251
		return r;
245
		return ERR_PTR(r);
Line 266... Line 260...
266
		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
260
		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
267
		src_offset += cur_size_in_bytes;
261
		src_offset += cur_size_in_bytes;
268
		dst_offset += cur_size_in_bytes;
262
		dst_offset += cur_size_in_bytes;
269
	}
263
	}
Line 270... Line 264...
270
 
264
 
271
	r = radeon_fence_emit(rdev, fence, ring->idx);
265
	r = radeon_fence_emit(rdev, &fence, ring->idx);
272
	if (r) {
266
	if (r) {
273
		radeon_ring_unlock_undo(rdev, ring);
267
		radeon_ring_unlock_undo(rdev, ring);
274
		radeon_semaphore_free(rdev, &sem, NULL);
268
		radeon_sync_free(rdev, &sync, NULL);
275
		return r;
269
		return ERR_PTR(r);
Line 276... Line 270...
276
	}
270
	}
277
 
271
 
Line 278... Line 272...
278
	radeon_ring_unlock_commit(rdev, ring, false);
272
	radeon_ring_unlock_commit(rdev, ring, false);
279
	radeon_semaphore_free(rdev, &sem, *fence);
273
	radeon_sync_free(rdev, &sync, fence);