Rev 6104 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 6104 | Rev 7146 | ||
|---|---|---|---|
| Line 1305... | Line 1305... | ||
| 1305 | * Returns the reference clock used by the gfx engine |
1305 | * Returns the reference clock used by the gfx engine |
| 1306 | * (SI). |
1306 | * (SI). |
| 1307 | */ |
1307 | */ |
| 1308 | u32 si_get_xclk(struct radeon_device *rdev) |
1308 | u32 si_get_xclk(struct radeon_device *rdev) |
| 1309 | { |
1309 | { |
| 1310 | u32 reference_clock = rdev->clock.spll.reference_freq; |
1310 | u32 reference_clock = rdev->clock.spll.reference_freq; |
| 1311 | u32 tmp; |
1311 | u32 tmp; |
| Line 1312... | Line 1312... | ||
| 1312 | 1312 | ||
| 1313 | tmp = RREG32(CG_CLKPIN_CNTL_2); |
1313 | tmp = RREG32(CG_CLKPIN_CNTL_2); |
| 1314 | if (tmp & MUX_TCLK_TO_XCLK) |
1314 | if (tmp & MUX_TCLK_TO_XCLK) |
| Line 2440... | Line 2440... | ||
| 2440 | /* |
2440 | /* |
| 2441 | * Core functions |
2441 | * Core functions |
| 2442 | */ |
2442 | */ |
| 2443 | static void si_tiling_mode_table_init(struct radeon_device *rdev) |
2443 | static void si_tiling_mode_table_init(struct radeon_device *rdev) |
| 2444 | { |
2444 | { |
| - | 2445 | u32 *tile = rdev->config.si.tile_mode_array; |
|
| 2445 | const u32 num_tile_mode_states = 32; |
2446 | const u32 num_tile_mode_states = |
| - | 2447 | ARRAY_SIZE(rdev->config.si.tile_mode_array); |
|
| 2446 | u32 reg_offset, gb_tile_moden, split_equal_to_row_size; |
2448 | u32 reg_offset, split_equal_to_row_size; |
| Line 2447... | Line 2449... | ||
| 2447 | 2449 | ||
| 2448 | switch (rdev->config.si.mem_row_size_in_kb) { |
2450 | switch (rdev->config.si.mem_row_size_in_kb) { |
| 2449 | case 1: |
2451 | case 1: |
| 2450 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; |
2452 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; |
| Line 2456... | Line 2458... | ||
| 2456 | case 4: |
2458 | case 4: |
| 2457 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; |
2459 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; |
| 2458 | break; |
2460 | break; |
| 2459 | } |
2461 | } |
| Line 2944... | Line 2896... | ||
| 2944 | } else |
2896 | default: |
| - | 2897 | DRM_ERROR("unknown asic: 0x%x\n", rdev->family); |
|
| 2945 | DRM_ERROR("unknown asic: 0x%x\n", rdev->family); |
2898 | } |
| Line 2946... | Line 2899... | ||
| 2946 | } |
2899 | } |
| 2947 | 2900 | ||
| 2948 | static void si_select_se_sh(struct radeon_device *rdev, |
2901 | static void si_select_se_sh(struct radeon_device *rdev, |
| Line 7286... | Line 7239... | ||
| 7286 | uint64_t clock; |
7239 | uint64_t clock; |
| Line 7287... | Line 7240... | ||
| 7287 | 7240 | ||
| 7288 | mutex_lock(&rdev->gpu_clock_mutex); |
7241 | mutex_lock(&rdev->gpu_clock_mutex); |
| 7289 | WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); |
7242 | WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); |
| 7290 | clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | |
7243 | clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | |
| 7291 | ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); |
7244 | ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); |
| 7292 | mutex_unlock(&rdev->gpu_clock_mutex); |
7245 | mutex_unlock(&rdev->gpu_clock_mutex); |
| 7293 | return clock; |
7246 | return clock; |
| Line 7294... | Line 7247... | ||
| 7294 | } |
7247 | } |
| Line 7743... | Line 7696... | ||
| 7743 | } |
7696 | } |
| 7744 | } |
7697 | } |
| Line 7745... | Line 7698... | ||
| 7745 | 7698 | ||
| 7746 | int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev) |
7699 | int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev) |
| 7747 | { |
7700 | { |
| Line 7748... | Line 7701... | ||
| 7748 | unsigned i; |
7701 | unsigned i; |
| 7749 | 7702 | ||
| Line 7750... | Line 7703... | ||
| 7750 | /* make sure VCEPLL_CTLREQ is deasserted */ |
7703 | /* make sure VCEPLL_CTLREQ is deasserted */ |
| Line 7751... | Line 7704... | ||
| 7751 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); |
7704 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); |
| 7752 | 7705 | ||
| Line 7753... | Line 7706... | ||
| 7753 | mdelay(10); |
7706 | mdelay(10); |
| 7754 | 7707 | ||
| 7755 | /* assert UPLL_CTLREQ */ |
7708 | /* assert UPLL_CTLREQ */ |
| 7756 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); |
7709 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); |
| 7757 | 7710 | ||
| 7758 | /* wait for CTLACK and CTLACK2 to get asserted */ |
7711 | /* wait for CTLACK and CTLACK2 to get asserted */ |
| 7759 | for (i = 0; i < 100; ++i) { |
7712 | for (i = 0; i < 100; ++i) { |
| Line 7760... | Line 7713... | ||
| 7760 | uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; |
7713 | uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; |
| 7761 | if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) |
7714 | if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) |
| Line 7762... | Line 7715... | ||
| 7762 | break; |
7715 | break; |
| 7763 | mdelay(10); |
7716 | mdelay(10); |
| 7764 | } |
7717 | } |
| 7765 | 7718 | ||
| Line 7766... | Line 7719... | ||
| 7766 | /* deassert UPLL_CTLREQ */ |
7719 | /* deassert UPLL_CTLREQ */ |
| 7767 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); |
7720 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); |
| Line 7768... | Line 7721... | ||
| 7768 | 7721 | ||
| 7769 | if (i == 100) { |
7722 | if (i == 100) { |
| 7770 | DRM_ERROR("Timeout setting UVD clocks!\n"); |
7723 | DRM_ERROR("Timeout setting UVD clocks!\n"); |