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Line 2440... Line 2440...
2440 
/*
 2440 
/*
2441 
 * Core functions
 2441 
 * Core functions
2442 
 */
 2442 
 */
2443 
static void si_tiling_mode_table_init(struct radeon_device *rdev)
 2443 
static void si_tiling_mode_table_init(struct radeon_device *rdev)
2444 
{
 2444 
{
- 
 
 2445 
	u32 *tile = rdev->config.si.tile_mode_array;
2445 
	const u32 num_tile_mode_states = 32;
 2446 
	const u32 num_tile_mode_states =
- 
 
 2447 
			ARRAY_SIZE(rdev->config.si.tile_mode_array);
2446 
	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 2448 
	u32 reg_offset, split_equal_to_row_size;
Line 2447... Line 2449...
2447 
 
 2449 
 
2448 
	switch (rdev->config.si.mem_row_size_in_kb) {
 2450 
	switch (rdev->config.si.mem_row_size_in_kb) {
2449 
	case 1:
 2451 
	case 1:
2450 
		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 2452 
		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
Line 2456... Line 2458...
2456 
	case 4:
 2458 
	case 4:
2457 
		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 2459 
		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2458 
		break;
 2460 
		break;
2459 
	}
 2461 
	}
Line 2460... Line -...
2460 
 
 - 
 
2461 
	if ((rdev->family == CHIP_TAHITI) ||
 - 
 
2462 
	    (rdev->family == CHIP_PITCAIRN)) {
 2462 
 
- 
 
 2463 
	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
- 
 
 2464 
		tile[reg_offset] = 0;
2463 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 2465 
 
- 
 
 2466 
	switch(rdev->family) {
- 
 
 2467 
	case CHIP_TAHITI:
2464 
			switch (reg_offset) {
 2468 
	case CHIP_PITCAIRN:
2465 
			case 0:  /* non-AA compressed depth or any compressed stencil */
 2469 
		/* non-AA compressed depth or any compressed stencil */
2466 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2470 
		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2467 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2471 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2468 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2472 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2469 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2473 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2470 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2474 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2471 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2475 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2472 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2476 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2473 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2474 
				break;
 2477 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2475 
			case 1:  /* 2xAA/4xAA compressed depth only */
 2478 
		/* 2xAA/4xAA compressed depth only */
2476 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2479 
		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2477 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2480 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2478 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2481 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2479 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 2482 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2480 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2483 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2481 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2484 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2485 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2483 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2484 
				break;
 2486 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2485 
			case 2:  /* 8xAA compressed depth only */
 2487 
		/* 8xAA compressed depth only */
2486 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2488 
		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2487 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2489 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2488 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2490 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2489 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2491 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2490 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2492 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2491 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2493 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2492 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2494 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2493 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2494 
				break;
 2495 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2495 
			case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
 2496 
		/* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2496 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2497 
		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2497 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2498 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2498 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2499 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2499 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 2500 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2500 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2501 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2501 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2502 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2502 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2503 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2503 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2504 
				break;
 2504 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2505 
			case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
 2505 
		/* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2506 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2506 
		tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2507 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2507 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2508 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2508 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2509 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2509 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2510 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2510 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2511 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2511 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2512 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2512 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2513 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2514 
				break;
 2513 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2515 
			case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
 2514 
		/* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2516 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2515 
		tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2517 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2516 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2518 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2517 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2519 
						 TILE_SPLIT(split_equal_to_row_size) |
 2518 
			   TILE_SPLIT(split_equal_to_row_size) |
2520 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2519 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2521 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2520 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2522 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2521 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2523 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2524 
				break;
 2522 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2525 
			case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
 2523 
		/* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2526 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2524 
		tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2527 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2525 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2528 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2526 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2529 
						 TILE_SPLIT(split_equal_to_row_size) |
 2527 
			   TILE_SPLIT(split_equal_to_row_size) |
2530 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2528 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2531 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2529 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2532 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2530 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2533 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 - 
 
2534 
				break;
 2531 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2535 
			case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
 2532 
		/* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2536 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2533 
		tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2537 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2534 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2538 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2535 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2539 
						 TILE_SPLIT(split_equal_to_row_size) |
 2536 
			   TILE_SPLIT(split_equal_to_row_size) |
2540 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2537 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2541 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2538 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2542 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2539 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2543 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2544 
				break;
 2540 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2545 
			case 8:  /* 1D and 1D Array Surfaces */
 2541 
		/* 1D and 1D Array Surfaces */
2546 
				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 2542 
		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2547 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2543 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2548 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2544 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2549 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2545 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2550 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2546 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2551 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2547 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2552 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2548 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2553 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2554 
				break;
 2549 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2555 
			case 9:  /* Displayable maps. */
 2550 
		/* Displayable maps. */
2556 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2551 
		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2557 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2552 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2558 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2553 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2559 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2554 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2560 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2555 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2561 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2556 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2562 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2557 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2563 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2564 
				break;
 2558 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2565 
			case 10:  /* Display 8bpp. */
 2559 
		/* Display 8bpp. */
2566 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2560 
		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2567 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2561 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2568 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2562 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2569 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2563 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2570 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2564 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2571 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2565 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2572 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2566 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2573 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2574 
				break;
 2567 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2575 
			case 11:  /* Display 16bpp. */
 2568 
		/* Display 16bpp. */
2576 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2569 
		tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2577 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2570 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2578 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2571 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2579 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2572 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2580 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2573 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2581 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2574 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2582 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2575 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2583 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2584 
				break;
 2576 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2585 
			case 12:  /* Display 32bpp. */
 2577 
		/* Display 32bpp. */
2586 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2578 
		tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2587 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2579 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2588 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2580 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2589 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 2581 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2590 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2582 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2591 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2583 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2592 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2584 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2593 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 - 
 
2594 
				break;
 2585 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2595 
			case 13:  /* Thin. */
 2586 
		/* Thin. */
2596 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2587 
		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2597 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2588 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2598 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2589 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2599 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2590 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2600 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2591 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2601 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2592 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2602 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2593 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2603 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2604 
				break;
 2594 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2605 
			case 14:  /* Thin 8 bpp. */
 2595 
		/* Thin 8 bpp. */
2606 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2596 
		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2607 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2597 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2608 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2598 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2609 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2599 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2610 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2600 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2611 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2601 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2612 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2602 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2613 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 - 
 
2614 
				break;
 2603 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2615 
			case 15:  /* Thin 16 bpp. */
 2604 
		/* Thin 16 bpp. */
2616 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2605 
		tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2617 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2606 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2618 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2607 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2619 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2608 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2620 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2609 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2621 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2610 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2622 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2611 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2623 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 - 
 
2624 
				break;
 2612 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2625 
			case 16:  /* Thin 32 bpp. */
 2613 
		/* Thin 32 bpp. */
2626 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2614 
		tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2627 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2615 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2628 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2616 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2629 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 2617 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2630 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2618 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2631 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2619 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2632 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2620 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2633 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 - 
 
2634 
				break;
 2621 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2635 
			case 17:  /* Thin 64 bpp. */
 2622 
		/* Thin 64 bpp. */
2636 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2623 
		tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2637 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2624 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2638 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2625 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2639 
						 TILE_SPLIT(split_equal_to_row_size) |
 2626 
			   TILE_SPLIT(split_equal_to_row_size) |
2640 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2627 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2641 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2628 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2642 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2629 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2643 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 - 
 
2644 
				break;
 2630 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2645 
			case 21:  /* 8 bpp PRT. */
 2631 
		/* 8 bpp PRT. */
2646 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2632 
		tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2647 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2633 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2648 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2634 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2649 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2635 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2650 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2636 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2651 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 2637 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2652 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2638 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2653 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2654 
				break;
 2639 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2655 
			case 22:  /* 16 bpp PRT */
 2640 
		/* 16 bpp PRT */
2656 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2641 
		tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2657 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2642 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2658 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2643 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2659 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2644 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2660 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2645 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2661 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2646 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2662 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2647 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2663 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 - 
 
2664 
				break;
 2648 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2665 
			case 23:  /* 32 bpp PRT */
 2649 
		/* 32 bpp PRT */
2666 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2650 
		tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2667 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2651 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2668 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2652 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2669 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2653 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2670 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2654 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2671 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2655 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2672 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2656 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2673 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2674 
				break;
 2657 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2675 
			case 24:  /* 64 bpp PRT */
 2658 
		/* 64 bpp PRT */
2676 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2659 
		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2677 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2660 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2678 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2661 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2679 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 2662 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2680 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2663 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2681 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2664 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2682 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2665 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2683 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2684 
				break;
 2666 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2685 
			case 25:  /* 128 bpp PRT */
 2667 
		/* 128 bpp PRT */
2686 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2668 
		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2687 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2669 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2688 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2670 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2689 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 2671 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2690 
						 NUM_BANKS(ADDR_SURF_8_BANK) |
 2672 
			   NUM_BANKS(ADDR_SURF_8_BANK) |
2691 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2673 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2692 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2674 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- 
 
 2675 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- 
 
 2676 
 
- 
 
 2677 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2693 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 2678 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2694 
				break;
 - 
 
2695 
			default:
 - 
 
2696 
				gb_tile_moden = 0;
 - 
 
2697 
				break;
 - 
 
2698 
			}
 - 
 
2699 
			rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
 - 
 
2700 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 2679 
		break;
2701 
		}
 2680 
 
2702 
	} else if ((rdev->family == CHIP_VERDE) ||
 2681 
	case CHIP_VERDE:
2703 
		   (rdev->family == CHIP_OLAND) ||
 2682 
	case CHIP_OLAND:
2704 
		   (rdev->family == CHIP_HAINAN)) {
 - 
 
2705 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 - 
 
2706 
			switch (reg_offset) {
 2683 
	case CHIP_HAINAN:
2707 
			case 0:  /* non-AA compressed depth or any compressed stencil */
 2684 
		/* non-AA compressed depth or any compressed stencil */
2708 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2685 
		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2709 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2686 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2710 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2687 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2711 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2688 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2712 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2689 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2713 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2690 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2714 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2691 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2715 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 - 
 
2716 
				break;
 2692 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2717 
			case 1:  /* 2xAA/4xAA compressed depth only */
 2693 
		/* 2xAA/4xAA compressed depth only */
2718 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2694 
		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2719 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2695 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2720 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2696 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2721 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 2697 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2722 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2698 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2723 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2699 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2724 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2700 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2725 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 - 
 
2726 
				break;
 2701 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2727 
			case 2:  /* 8xAA compressed depth only */
 2702 
		/* 8xAA compressed depth only */
2728 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2703 
		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2729 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2704 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2730 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2705 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2731 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2706 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2732 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2707 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2733 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2708 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2734 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2709 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2735 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 - 
 
2736 
				break;
 2710 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2737 
			case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
 2711 
		/* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2738 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2712 
		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2739 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2713 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2740 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2714 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2741 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 2715 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2742 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2716 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2743 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2717 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2744 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2718 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2745 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 - 
 
2746 
				break;
 2719 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2747 
			case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
 2720 
		/* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2748 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2721 
		tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2749 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2722 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2750 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2723 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2751 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2724 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2752 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2725 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2753 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2726 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2754 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2727 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2755 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2756 
				break;
 2728 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2757 
			case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
 2729 
		/* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2758 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2730 
		tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2759 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2731 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2760 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2732 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2761 
						 TILE_SPLIT(split_equal_to_row_size) |
 2733 
			   TILE_SPLIT(split_equal_to_row_size) |
2762 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2734 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2763 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2735 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2764 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2736 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2765 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2766 
				break;
 2737 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2767 
			case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
 2738 
		/* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2768 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2739 
		tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2769 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2740 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2770 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2741 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2771 
						 TILE_SPLIT(split_equal_to_row_size) |
 2742 
			   TILE_SPLIT(split_equal_to_row_size) |
2772 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2743 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2773 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2744 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2774 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2745 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2775 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2776 
				break;
 2746 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2777 
			case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
 2747 
		/* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2778 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2748 
		tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2779 
						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 2749 
			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2780 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2750 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2781 
						 TILE_SPLIT(split_equal_to_row_size) |
 2751 
			   TILE_SPLIT(split_equal_to_row_size) |
2782 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2752 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2783 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2753 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2784 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2754 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2785 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 - 
 
2786 
				break;
 2755 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2787 
			case 8:  /* 1D and 1D Array Surfaces */
 2756 
		/* 1D and 1D Array Surfaces */
2788 
				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 2757 
		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2789 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2758 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2790 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2759 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2791 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2760 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2792 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2761 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2793 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2762 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2794 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2763 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2795 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2796 
				break;
 2764 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2797 
			case 9:  /* Displayable maps. */
 2765 
		/* Displayable maps. */
2798 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2766 
		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2799 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2767 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2800 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2768 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2801 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2769 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2802 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2770 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2803 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2771 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2804 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2772 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2805 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2806 
				break;
 2773 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2807 
			case 10:  /* Display 8bpp. */
 2774 
		/* Display 8bpp. */
2808 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2775 
		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2809 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2776 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2810 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2777 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2811 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2778 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2812 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2779 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2813 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2780 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2814 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2781 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2815 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 - 
 
2816 
				break;
 2782 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2817 
			case 11:  /* Display 16bpp. */
 2783 
		/* Display 16bpp. */
2818 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2784 
		tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2819 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2785 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2820 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2786 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2821 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2787 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2822 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2788 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2823 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2789 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2824 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2790 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2825 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2826 
				break;
 2791 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2827 
			case 12:  /* Display 32bpp. */
 2792 
		/* Display 32bpp. */
2828 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2793 
		tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2829 
						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 2794 
			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2830 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2795 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2831 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 2796 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2832 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2797 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2833 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2798 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2834 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2799 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2835 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2836 
				break;
 2800 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2837 
			case 13:  /* Thin. */
 2801 
		/* Thin. */
2838 
				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 2802 
		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2839 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2803 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2840 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2804 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2841 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 2805 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2842 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2806 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2843 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2807 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2844 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2808 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2845 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2846 
				break;
 2809 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2847 
			case 14:  /* Thin 8 bpp. */
 2810 
		/* Thin 8 bpp. */
2848 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2811 
		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2849 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2812 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2850 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2813 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2851 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2814 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2852 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2815 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2853 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2816 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2817 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2855 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2856 
				break;
 2818 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2857 
			case 15:  /* Thin 16 bpp. */
 2819 
		/* Thin 16 bpp. */
2858 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2820 
		tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2859 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2821 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2860 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2822 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2861 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2823 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2862 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2824 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2863 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2825 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2864 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2826 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2865 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2866 
				break;
 2827 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2867 
			case 16:  /* Thin 32 bpp. */
 2828 
		/* Thin 32 bpp. */
2868 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2829 
		tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2869 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2830 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2870 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2831 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2871 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 2832 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2872 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2833 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2873 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2834 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2874 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2835 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2875 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2876 
				break;
 2836 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2877 
			case 17:  /* Thin 64 bpp. */
 2837 
		/* Thin 64 bpp. */
2878 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2838 
		tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2879 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2839 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2880 
						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 2840 
			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2881 
						 TILE_SPLIT(split_equal_to_row_size) |
 2841 
			   TILE_SPLIT(split_equal_to_row_size) |
2882 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2842 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2883 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2843 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2884 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2844 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2885 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2886 
				break;
 2845 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2887 
			case 21:  /* 8 bpp PRT. */
 2846 
		/* 8 bpp PRT. */
2888 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2847 
		tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2889 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2848 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2890 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2849 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2891 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2850 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2892 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2851 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2893 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 2852 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2894 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2853 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2895 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2896 
				break;
 2854 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2897 
			case 22:  /* 16 bpp PRT */
 2855 
		/* 16 bpp PRT */
2898 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2856 
		tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2899 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2857 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2900 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2858 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2901 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2859 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2902 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2860 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2903 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2861 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2904 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 2862 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2905 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 - 
 
2906 
				break;
 2863 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2907 
			case 23:  /* 32 bpp PRT */
 2864 
		/* 32 bpp PRT */
2908 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2865 
		tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2909 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2866 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2910 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2867 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2911 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 2868 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2912 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2869 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2913 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2870 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2914 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 2871 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2915 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2916 
				break;
 2872 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2917 
			case 24:  /* 64 bpp PRT */
 2873 
		/* 64 bpp PRT */
2918 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2874 
		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2919 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2875 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2920 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2876 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2921 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 2877 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2922 
						 NUM_BANKS(ADDR_SURF_16_BANK) |
 2878 
			   NUM_BANKS(ADDR_SURF_16_BANK) |
2923 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2879 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2924 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2880 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2925 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 - 
 
2926 
				break;
 2881 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2927 
			case 25:  /* 128 bpp PRT */
 2882 
		/* 128 bpp PRT */
2928 
				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 2883 
		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2929 
						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 2884 
			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2930 
						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 2885 
			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2931 
						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 2886 
			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2932 
						 NUM_BANKS(ADDR_SURF_8_BANK) |
 2887 
			   NUM_BANKS(ADDR_SURF_8_BANK) |
2933 
						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 2888 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2934 
						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 2889 
			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- 
 
 2890 
			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- 
 
 2891 
 
- 
 
 2892 
		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2935 
						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 2893 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
- 
 
 2894 
		break;
2936 
				break;
 2895 
 
2937 
			default:
 - 
 
2938 
				gb_tile_moden = 0;
 - 
 
2939 
				break;
 - 
 
2940 
			}
 - 
 
2941 
			rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
 - 
 
2942 
			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 - 
 
2943 
		}
 - 
 
2944 
	} else
 2896 
	default:
2945 
		DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
 2897 
		DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
- 
 
 2898 
	}
Line 2946... Line 2899...
2946 
}
 2899 
}
2947 
 
 2900 
 
2948 
static void si_select_se_sh(struct radeon_device *rdev,
 2901 
static void si_select_se_sh(struct radeon_device *rdev,
2949 
			    u32 se_num, u32 sh_num)
 2902 
			    u32 se_num, u32 sh_num)