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| Rev 5271 | Rev 6104 | ||
|---|---|---|---|
| Line 25... | Line 25... | ||
| 25 | #include |
25 | #include |
| 26 | #include |
26 | #include |
| 27 | #include |
27 | #include |
| 28 | #include "radeon.h" |
28 | #include "radeon.h" |
| 29 | #include "radeon_asic.h" |
29 | #include "radeon_asic.h" |
| - | 30 | #include "radeon_audio.h" |
|
| 30 | #include |
31 | #include |
| 31 | #include "sid.h" |
32 | #include "sid.h" |
| 32 | #include "atom.h" |
33 | #include "atom.h" |
| 33 | #include "si_blit_shaders.h" |
34 | #include "si_blit_shaders.h" |
| 34 | #include "clearstate_si.h" |
35 | #include "clearstate_si.h" |
| Line 1261... | Line 1262... | ||
| 1261 | default: |
1262 | default: |
| 1262 | break; |
1263 | break; |
| 1263 | } |
1264 | } |
| 1264 | } |
1265 | } |
| Line -... | Line 1266... | ||
| - | 1266 | ||
| - | 1267 | /** |
|
| - | 1268 | * si_get_allowed_info_register - fetch the register for the info ioctl |
|
| - | 1269 | * |
|
| - | 1270 | * @rdev: radeon_device pointer |
|
| - | 1271 | * @reg: register offset in bytes |
|
| - | 1272 | * @val: register value |
|
| - | 1273 | * |
|
| - | 1274 | * Returns 0 for success or -EINVAL for an invalid register |
|
| - | 1275 | * |
|
| - | 1276 | */ |
|
| - | 1277 | int si_get_allowed_info_register(struct radeon_device *rdev, |
|
| - | 1278 | u32 reg, u32 *val) |
|
| - | 1279 | { |
|
| - | 1280 | switch (reg) { |
|
| - | 1281 | case GRBM_STATUS: |
|
| - | 1282 | case GRBM_STATUS2: |
|
| - | 1283 | case GRBM_STATUS_SE0: |
|
| - | 1284 | case GRBM_STATUS_SE1: |
|
| - | 1285 | case SRBM_STATUS: |
|
| - | 1286 | case SRBM_STATUS2: |
|
| - | 1287 | case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): |
|
| - | 1288 | case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): |
|
| - | 1289 | case UVD_STATUS: |
|
| - | 1290 | *val = RREG32(reg); |
|
| - | 1291 | return 0; |
|
| - | 1292 | default: |
|
| - | 1293 | return -EINVAL; |
|
| - | 1294 | } |
|
| - | 1295 | } |
|
| 1265 | 1296 | ||
| 1266 | #define PCIE_BUS_CLK 10000 |
1297 | #define PCIE_BUS_CLK 10000 |
| Line 1267... | Line 1298... | ||
| 1267 | #define TCLK (PCIE_BUS_CLK / 10) |
1298 | #define TCLK (PCIE_BUS_CLK / 10) |
| 1268 | 1299 | ||
| Line 2343... | Line 2374... | ||
| 2343 | c.full = dfixed_div(c, a); |
2374 | c.full = dfixed_div(c, a); |
| 2344 | a.full = dfixed_const(16); |
2375 | a.full = dfixed_const(16); |
| 2345 | c.full = dfixed_div(c, a); |
2376 | c.full = dfixed_div(c, a); |
| 2346 | priority_b_mark = dfixed_trunc(c); |
2377 | priority_b_mark = dfixed_trunc(c); |
| 2347 | priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; |
2378 | priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; |
| - | 2379 | ||
| - | 2380 | /* Save number of lines the linebuffer leads before the scanout */ |
|
| - | 2381 | radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); |
|
| 2348 | } |
2382 | } |
| Line 2349... | Line 2383... | ||
| 2349 | 2383 | ||
| 2350 | /* select wm A */ |
2384 | /* select wm A */ |
| 2351 | arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); |
2385 | arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); |
| Line 3159... | Line 3193... | ||
| 3159 | WREG32((0x2c20 + j), 0x00000000); |
3193 | WREG32((0x2c20 + j), 0x00000000); |
| 3160 | WREG32((0x2c24 + j), 0x00000000); |
3194 | WREG32((0x2c24 + j), 0x00000000); |
| 3161 | } |
3195 | } |
| Line 3162... | Line 3196... | ||
| 3162 | 3196 | ||
| - | 3197 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
|
| - | 3198 | WREG32(SRBM_INT_CNTL, 1); |
|
| Line 3163... | Line 3199... | ||
| 3163 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
3199 | WREG32(SRBM_INT_ACK, 1); |
| Line 3164... | Line 3200... | ||
| 3164 | 3200 | ||
| Line 4283... | Line 4319... | ||
| 4283 | WREG32(0x15DC, 0); |
4319 | WREG32(0x15DC, 0); |
| Line 4284... | Line 4320... | ||
| 4284 | 4320 | ||
| 4285 | /* empty context1-15 */ |
4321 | /* empty context1-15 */ |
| 4286 | /* set vm size, must be a multiple of 4 */ |
4322 | /* set vm size, must be a multiple of 4 */ |
| 4287 | WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
4323 | WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
| 4288 | WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); |
4324 | WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); |
| 4289 | /* Assign the pt base to something valid for now; the pts used for |
4325 | /* Assign the pt base to something valid for now; the pts used for |
| 4290 | * the VMs are determined by the application and setup and assigned |
4326 | * the VMs are determined by the application and setup and assigned |
| 4291 | * on the fly in the vm part of radeon_gart.c |
4327 | * on the fly in the vm part of radeon_gart.c |
| 4292 | */ |
4328 | */ |
| Line 4358... | Line 4394... | ||
| 4358 | 4394 | ||
| 4359 | static void si_pcie_gart_fini(struct radeon_device *rdev) |
4395 | static void si_pcie_gart_fini(struct radeon_device *rdev) |
| 4360 | { |
4396 | { |
| 4361 | si_pcie_gart_disable(rdev); |
4397 | si_pcie_gart_disable(rdev); |
| 4362 | radeon_gart_table_vram_free(rdev); |
4398 | radeon_gart_table_vram_free(rdev); |
| 4363 | // radeon_gart_fini(rdev); |
4399 | radeon_gart_fini(rdev); |
| Line 4364... | Line 4400... | ||
| 4364 | } |
4400 | } |
| 4365 | 4401 | ||
| 4366 | /* vm parser */ |
4402 | /* vm parser */ |
| Line 4696... | Line 4732... | ||
| 4696 | pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); |
4732 | pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); |
| 4697 | pkt.one_reg_wr = 0; |
4733 | pkt.one_reg_wr = 0; |
| 4698 | switch (pkt.type) { |
4734 | switch (pkt.type) { |
| 4699 | case RADEON_PACKET_TYPE0: |
4735 | case RADEON_PACKET_TYPE0: |
| 4700 | dev_err(rdev->dev, "Packet0 not allowed!\n"); |
4736 | dev_err(rdev->dev, "Packet0 not allowed!\n"); |
| 4701 | for (i = 0; i < ib->length_dw; i++) { |
- | |
| 4702 | if (i == idx) |
- | |
| 4703 | printk("\t0x%08x <---\n", ib->ptr[i]); |
- | |
| 4704 | else |
- | |
| 4705 | printk("\t0x%08x\n", ib->ptr[i]); |
- | |
| 4706 | } |
- | |
| 4707 | ret = -EINVAL; |
4737 | ret = -EINVAL; |
| 4708 | break; |
4738 | break; |
| 4709 | case RADEON_PACKET_TYPE2: |
4739 | case RADEON_PACKET_TYPE2: |
| 4710 | idx += 1; |
4740 | idx += 1; |
| 4711 | break; |
4741 | break; |
| Line 4733... | Line 4763... | ||
| 4733 | default: |
4763 | default: |
| 4734 | dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); |
4764 | dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); |
| 4735 | ret = -EINVAL; |
4765 | ret = -EINVAL; |
| 4736 | break; |
4766 | break; |
| 4737 | } |
4767 | } |
| 4738 | if (ret) |
4768 | if (ret) { |
| - | 4769 | for (i = 0; i < ib->length_dw; i++) { |
|
| - | 4770 | if (i == idx) |
|
| - | 4771 | printk("\t0x%08x <---\n", ib->ptr[i]); |
|
| - | 4772 | else |
|
| - | 4773 | printk("\t0x%08x\n", ib->ptr[i]); |
|
| - | 4774 | } |
|
| 4739 | break; |
4775 | break; |
| - | 4776 | } |
|
| 4740 | } while (idx < ib->length_dw); |
4777 | } while (idx < ib->length_dw); |
| Line 4741... | Line 4778... | ||
| 4741 | 4778 | ||
| 4742 | return ret; |
4779 | return ret; |
| Line 5055... | Line 5092... | ||
| 5055 | WRITE_DATA_DST_SEL(0))); |
5092 | WRITE_DATA_DST_SEL(0))); |
| 5056 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
5093 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
| 5057 | radeon_ring_write(ring, 0); |
5094 | radeon_ring_write(ring, 0); |
| 5058 | radeon_ring_write(ring, 1 << vm_id); |
5095 | radeon_ring_write(ring, 1 << vm_id); |
| Line -... | Line 5096... | ||
| - | 5096 | ||
| - | 5097 | /* wait for the invalidate to complete */ |
|
| - | 5098 | radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); |
|
| - | 5099 | radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ |
|
| - | 5100 | WAIT_REG_MEM_ENGINE(0))); /* me */ |
|
| - | 5101 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
|
| - | 5102 | radeon_ring_write(ring, 0); |
|
| - | 5103 | radeon_ring_write(ring, 0); /* ref */ |
|
| - | 5104 | radeon_ring_write(ring, 0); /* mask */ |
|
| - | 5105 | radeon_ring_write(ring, 0x20); /* poll interval */ |
|
| 5059 | 5106 | ||
| 5060 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
5107 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
| 5061 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
5108 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
| 5062 | radeon_ring_write(ring, 0x0); |
5109 | radeon_ring_write(ring, 0x0); |
| Line 5897... | Line 5944... | ||
| 5897 | tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; |
5944 | tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; |
| 5898 | WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); |
5945 | WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); |
| 5899 | tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
5946 | tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
| 5900 | WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); |
5947 | WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); |
| 5901 | WREG32(GRBM_INT_CNTL, 0); |
5948 | WREG32(GRBM_INT_CNTL, 0); |
| - | 5949 | WREG32(SRBM_INT_CNTL, 0); |
|
| 5902 | if (rdev->num_crtc >= 2) { |
5950 | if (rdev->num_crtc >= 2) { |
| 5903 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
5951 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
| 5904 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
5952 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
| 5905 | } |
5953 | } |
| 5906 | if (rdev->num_crtc >= 4) { |
5954 | if (rdev->num_crtc >= 4) { |
| Line 6038... | Line 6086... | ||
| 6038 | 6086 | ||
| 6039 | cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & |
6087 | cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & |
| Line 6040... | Line 6088... | ||
| 6040 | (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
6088 | (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
| 6041 | 6089 | ||
| 6042 | if (!ASIC_IS_NODCE(rdev)) { |
6090 | if (!ASIC_IS_NODCE(rdev)) { |
| 6043 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
6091 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 6044 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
6092 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 6045 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
6093 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 6046 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
6094 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 6047 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
6095 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| Line 6048... | Line 6096... | ||
| 6048 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
6096 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); |
| 6049 | } |
6097 | } |
| Line 6106... | Line 6154... | ||
| 6106 | DRM_DEBUG("si_irq_set: vblank 5\n"); |
6154 | DRM_DEBUG("si_irq_set: vblank 5\n"); |
| 6107 | crtc6 |= VBLANK_INT_MASK; |
6155 | crtc6 |= VBLANK_INT_MASK; |
| 6108 | } |
6156 | } |
| 6109 | if (rdev->irq.hpd[0]) { |
6157 | if (rdev->irq.hpd[0]) { |
| 6110 | DRM_DEBUG("si_irq_set: hpd 1\n"); |
6158 | DRM_DEBUG("si_irq_set: hpd 1\n"); |
| 6111 | hpd1 |= DC_HPDx_INT_EN; |
6159 | hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 6112 | } |
6160 | } |
| 6113 | if (rdev->irq.hpd[1]) { |
6161 | if (rdev->irq.hpd[1]) { |
| 6114 | DRM_DEBUG("si_irq_set: hpd 2\n"); |
6162 | DRM_DEBUG("si_irq_set: hpd 2\n"); |
| 6115 | hpd2 |= DC_HPDx_INT_EN; |
6163 | hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 6116 | } |
6164 | } |
| 6117 | if (rdev->irq.hpd[2]) { |
6165 | if (rdev->irq.hpd[2]) { |
| 6118 | DRM_DEBUG("si_irq_set: hpd 3\n"); |
6166 | DRM_DEBUG("si_irq_set: hpd 3\n"); |
| 6119 | hpd3 |= DC_HPDx_INT_EN; |
6167 | hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 6120 | } |
6168 | } |
| 6121 | if (rdev->irq.hpd[3]) { |
6169 | if (rdev->irq.hpd[3]) { |
| 6122 | DRM_DEBUG("si_irq_set: hpd 4\n"); |
6170 | DRM_DEBUG("si_irq_set: hpd 4\n"); |
| 6123 | hpd4 |= DC_HPDx_INT_EN; |
6171 | hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 6124 | } |
6172 | } |
| 6125 | if (rdev->irq.hpd[4]) { |
6173 | if (rdev->irq.hpd[4]) { |
| 6126 | DRM_DEBUG("si_irq_set: hpd 5\n"); |
6174 | DRM_DEBUG("si_irq_set: hpd 5\n"); |
| 6127 | hpd5 |= DC_HPDx_INT_EN; |
6175 | hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 6128 | } |
6176 | } |
| 6129 | if (rdev->irq.hpd[5]) { |
6177 | if (rdev->irq.hpd[5]) { |
| 6130 | DRM_DEBUG("si_irq_set: hpd 6\n"); |
6178 | DRM_DEBUG("si_irq_set: hpd 6\n"); |
| 6131 | hpd6 |= DC_HPDx_INT_EN; |
6179 | hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; |
| 6132 | } |
6180 | } |
| Line 6133... | Line 6181... | ||
| 6133 | 6181 | ||
| 6134 | WREG32(CP_INT_CNTL_RING0, cp_int_cntl); |
6182 | WREG32(CP_INT_CNTL_RING0, cp_int_cntl); |
| 6135 | WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); |
6183 | WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); |
| Line 6186... | Line 6234... | ||
| 6186 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
6234 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
| 6187 | } |
6235 | } |
| Line 6188... | Line 6236... | ||
| 6188 | 6236 | ||
| Line -... | Line 6237... | ||
| - | 6237 | WREG32(CG_THERMAL_INT, thermal_int); |
|
| - | 6238 | ||
| - | 6239 | /* posting read */ |
|
| 6189 | WREG32(CG_THERMAL_INT, thermal_int); |
6240 | RREG32(SRBM_STATUS); |
| 6190 | 6241 | ||
| Line 6191... | Line 6242... | ||
| 6191 | return 0; |
6242 | return 0; |
| 6192 | } |
6243 | } |
| Line 6286... | Line 6337... | ||
| 6286 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
6337 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
| 6287 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
6338 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 6288 | tmp |= DC_HPDx_INT_ACK; |
6339 | tmp |= DC_HPDx_INT_ACK; |
| 6289 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
6340 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
| 6290 | } |
6341 | } |
| - | 6342 | ||
| - | 6343 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { |
|
| - | 6344 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
|
| - | 6345 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 6346 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
|
| - | 6347 | } |
|
| - | 6348 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { |
|
| - | 6349 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
|
| - | 6350 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 6351 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
|
| - | 6352 | } |
|
| - | 6353 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { |
|
| - | 6354 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
|
| - | 6355 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 6356 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
|
| - | 6357 | } |
|
| - | 6358 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { |
|
| - | 6359 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
|
| - | 6360 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 6361 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
|
| - | 6362 | } |
|
| - | 6363 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { |
|
| - | 6364 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
|
| - | 6365 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 6366 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
|
| - | 6367 | } |
|
| - | 6368 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { |
|
| - | 6369 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
|
| - | 6370 | tmp |= DC_HPDx_RX_INT_ACK; |
|
| - | 6371 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
|
| - | 6372 | } |
|
| 6291 | } |
6373 | } |
| Line 6292... | Line 6374... | ||
| 6292 | 6374 | ||
| 6293 | static void si_irq_disable(struct radeon_device *rdev) |
6375 | static void si_irq_disable(struct radeon_device *rdev) |
| 6294 | { |
6376 | { |
| Line 6351... | Line 6433... | ||
| 6351 | u32 wptr; |
6433 | u32 wptr; |
| 6352 | u32 rptr; |
6434 | u32 rptr; |
| 6353 | u32 src_id, src_data, ring_id; |
6435 | u32 src_id, src_data, ring_id; |
| 6354 | u32 ring_index; |
6436 | u32 ring_index; |
| 6355 | bool queue_hotplug = false; |
6437 | bool queue_hotplug = false; |
| - | 6438 | bool queue_dp = false; |
|
| 6356 | bool queue_thermal = false; |
6439 | bool queue_thermal = false; |
| 6357 | u32 status, addr; |
6440 | u32 status, addr; |
| Line 6358... | Line 6441... | ||
| 6358 | 6441 | ||
| 6359 | if (!rdev->ih.enabled || rdev->shutdown) |
6442 | if (!rdev->ih.enabled || rdev->shutdown) |
| Line 6384... | Line 6467... | ||
| 6384 | 6467 | ||
| 6385 | switch (src_id) { |
6468 | switch (src_id) { |
| 6386 | case 1: /* D1 vblank/vline */ |
6469 | case 1: /* D1 vblank/vline */ |
| 6387 | switch (src_data) { |
6470 | switch (src_data) { |
| 6388 | case 0: /* D1 vblank */ |
6471 | case 0: /* D1 vblank */ |
| - | 6472 | if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) |
|
| - | 6473 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6389 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { |
6474 | |
| 6390 | if (rdev->irq.crtc_vblank_int[0]) { |
6475 | if (rdev->irq.crtc_vblank_int[0]) { |
| 6391 | // drm_handle_vblank(rdev->ddev, 0); |
6476 | drm_handle_vblank(rdev->ddev, 0); |
| 6392 | rdev->pm.vblank_sync = true; |
6477 | rdev->pm.vblank_sync = true; |
| 6393 | // wake_up(&rdev->irq.vblank_queue); |
6478 | wake_up(&rdev->irq.vblank_queue); |
| 6394 | } |
6479 | } |
| 6395 | // if (atomic_read(&rdev->irq.pflip[0])) |
6480 | if (atomic_read(&rdev->irq.pflip[0])) |
| 6396 | // radeon_crtc_handle_flip(rdev, 0); |
6481 | radeon_crtc_handle_vblank(rdev, 0); |
| 6397 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
6482 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
| 6398 | DRM_DEBUG("IH: D1 vblank\n"); |
6483 | DRM_DEBUG("IH: D1 vblank\n"); |
| 6399 | } |
6484 | |
| 6400 | break; |
6485 | break; |
| 6401 | case 1: /* D1 vline */ |
6486 | case 1: /* D1 vline */ |
| - | 6487 | if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) |
|
| - | 6488 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6402 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { |
6489 | |
| 6403 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
6490 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
| 6404 | DRM_DEBUG("IH: D1 vline\n"); |
6491 | DRM_DEBUG("IH: D1 vline\n"); |
| 6405 | } |
6492 | |
| 6406 | break; |
6493 | break; |
| 6407 | default: |
6494 | default: |
| 6408 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
6495 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 6409 | break; |
6496 | break; |
| 6410 | } |
6497 | } |
| 6411 | break; |
6498 | break; |
| 6412 | case 2: /* D2 vblank/vline */ |
6499 | case 2: /* D2 vblank/vline */ |
| 6413 | switch (src_data) { |
6500 | switch (src_data) { |
| 6414 | case 0: /* D2 vblank */ |
6501 | case 0: /* D2 vblank */ |
| - | 6502 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) |
|
| - | 6503 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6415 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { |
6504 | |
| 6416 | if (rdev->irq.crtc_vblank_int[1]) { |
6505 | if (rdev->irq.crtc_vblank_int[1]) { |
| 6417 | // drm_handle_vblank(rdev->ddev, 1); |
6506 | drm_handle_vblank(rdev->ddev, 1); |
| 6418 | rdev->pm.vblank_sync = true; |
6507 | rdev->pm.vblank_sync = true; |
| 6419 | // wake_up(&rdev->irq.vblank_queue); |
6508 | wake_up(&rdev->irq.vblank_queue); |
| 6420 | } |
6509 | } |
| 6421 | // if (atomic_read(&rdev->irq.pflip[1])) |
6510 | if (atomic_read(&rdev->irq.pflip[1])) |
| 6422 | // radeon_crtc_handle_flip(rdev, 1); |
6511 | radeon_crtc_handle_vblank(rdev, 1); |
| 6423 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
6512 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
| 6424 | DRM_DEBUG("IH: D2 vblank\n"); |
6513 | DRM_DEBUG("IH: D2 vblank\n"); |
| 6425 | } |
6514 | |
| 6426 | break; |
6515 | break; |
| 6427 | case 1: /* D2 vline */ |
6516 | case 1: /* D2 vline */ |
| - | 6517 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) |
|
| - | 6518 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6428 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { |
6519 | |
| 6429 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; |
6520 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; |
| 6430 | DRM_DEBUG("IH: D2 vline\n"); |
6521 | DRM_DEBUG("IH: D2 vline\n"); |
| 6431 | } |
6522 | |
| 6432 | break; |
6523 | break; |
| 6433 | default: |
6524 | default: |
| 6434 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
6525 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 6435 | break; |
6526 | break; |
| 6436 | } |
6527 | } |
| 6437 | break; |
6528 | break; |
| 6438 | case 3: /* D3 vblank/vline */ |
6529 | case 3: /* D3 vblank/vline */ |
| 6439 | switch (src_data) { |
6530 | switch (src_data) { |
| 6440 | case 0: /* D3 vblank */ |
6531 | case 0: /* D3 vblank */ |
| - | 6532 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) |
|
| - | 6533 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6441 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { |
6534 | |
| 6442 | if (rdev->irq.crtc_vblank_int[2]) { |
6535 | if (rdev->irq.crtc_vblank_int[2]) { |
| 6443 | // drm_handle_vblank(rdev->ddev, 2); |
6536 | drm_handle_vblank(rdev->ddev, 2); |
| 6444 | rdev->pm.vblank_sync = true; |
6537 | rdev->pm.vblank_sync = true; |
| 6445 | // wake_up(&rdev->irq.vblank_queue); |
6538 | wake_up(&rdev->irq.vblank_queue); |
| 6446 | } |
6539 | } |
| 6447 | // if (atomic_read(&rdev->irq.pflip[2])) |
6540 | if (atomic_read(&rdev->irq.pflip[2])) |
| 6448 | // radeon_crtc_handle_flip(rdev, 2); |
6541 | radeon_crtc_handle_vblank(rdev, 2); |
| 6449 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; |
6542 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; |
| 6450 | DRM_DEBUG("IH: D3 vblank\n"); |
6543 | DRM_DEBUG("IH: D3 vblank\n"); |
| 6451 | } |
6544 | |
| 6452 | break; |
6545 | break; |
| 6453 | case 1: /* D3 vline */ |
6546 | case 1: /* D3 vline */ |
| - | 6547 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) |
|
| - | 6548 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6454 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { |
6549 | |
| 6455 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; |
6550 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; |
| 6456 | DRM_DEBUG("IH: D3 vline\n"); |
6551 | DRM_DEBUG("IH: D3 vline\n"); |
| 6457 | } |
6552 | |
| 6458 | break; |
6553 | break; |
| 6459 | default: |
6554 | default: |
| 6460 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
6555 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 6461 | break; |
6556 | break; |
| 6462 | } |
6557 | } |
| 6463 | break; |
6558 | break; |
| 6464 | case 4: /* D4 vblank/vline */ |
6559 | case 4: /* D4 vblank/vline */ |
| 6465 | switch (src_data) { |
6560 | switch (src_data) { |
| 6466 | case 0: /* D4 vblank */ |
6561 | case 0: /* D4 vblank */ |
| - | 6562 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) |
|
| - | 6563 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6467 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { |
6564 | |
| 6468 | if (rdev->irq.crtc_vblank_int[3]) { |
6565 | if (rdev->irq.crtc_vblank_int[3]) { |
| 6469 | // drm_handle_vblank(rdev->ddev, 3); |
6566 | drm_handle_vblank(rdev->ddev, 3); |
| 6470 | rdev->pm.vblank_sync = true; |
6567 | rdev->pm.vblank_sync = true; |
| 6471 | // wake_up(&rdev->irq.vblank_queue); |
6568 | wake_up(&rdev->irq.vblank_queue); |
| 6472 | } |
6569 | } |
| 6473 | // if (atomic_read(&rdev->irq.pflip[3])) |
6570 | if (atomic_read(&rdev->irq.pflip[3])) |
| 6474 | // radeon_crtc_handle_flip(rdev, 3); |
6571 | radeon_crtc_handle_vblank(rdev, 3); |
| 6475 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; |
6572 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; |
| 6476 | DRM_DEBUG("IH: D4 vblank\n"); |
6573 | DRM_DEBUG("IH: D4 vblank\n"); |
| 6477 | } |
6574 | |
| 6478 | break; |
6575 | break; |
| 6479 | case 1: /* D4 vline */ |
6576 | case 1: /* D4 vline */ |
| - | 6577 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) |
|
| - | 6578 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6480 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { |
6579 | |
| 6481 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; |
6580 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; |
| 6482 | DRM_DEBUG("IH: D4 vline\n"); |
6581 | DRM_DEBUG("IH: D4 vline\n"); |
| 6483 | } |
6582 | |
| 6484 | break; |
6583 | break; |
| 6485 | default: |
6584 | default: |
| 6486 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
6585 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 6487 | break; |
6586 | break; |
| 6488 | } |
6587 | } |
| 6489 | break; |
6588 | break; |
| 6490 | case 5: /* D5 vblank/vline */ |
6589 | case 5: /* D5 vblank/vline */ |
| 6491 | switch (src_data) { |
6590 | switch (src_data) { |
| 6492 | case 0: /* D5 vblank */ |
6591 | case 0: /* D5 vblank */ |
| - | 6592 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) |
|
| - | 6593 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6493 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { |
6594 | |
| 6494 | if (rdev->irq.crtc_vblank_int[4]) { |
6595 | if (rdev->irq.crtc_vblank_int[4]) { |
| 6495 | // drm_handle_vblank(rdev->ddev, 4); |
6596 | drm_handle_vblank(rdev->ddev, 4); |
| 6496 | rdev->pm.vblank_sync = true; |
6597 | rdev->pm.vblank_sync = true; |
| 6497 | // wake_up(&rdev->irq.vblank_queue); |
6598 | wake_up(&rdev->irq.vblank_queue); |
| 6498 | } |
6599 | } |
| 6499 | // if (atomic_read(&rdev->irq.pflip[4])) |
6600 | if (atomic_read(&rdev->irq.pflip[4])) |
| 6500 | // radeon_crtc_handle_flip(rdev, 4); |
6601 | radeon_crtc_handle_vblank(rdev, 4); |
| 6501 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; |
6602 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; |
| 6502 | DRM_DEBUG("IH: D5 vblank\n"); |
6603 | DRM_DEBUG("IH: D5 vblank\n"); |
| 6503 | } |
6604 | |
| 6504 | break; |
6605 | break; |
| 6505 | case 1: /* D5 vline */ |
6606 | case 1: /* D5 vline */ |
| - | 6607 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) |
|
| - | 6608 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6506 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { |
6609 | |
| 6507 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; |
6610 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; |
| 6508 | DRM_DEBUG("IH: D5 vline\n"); |
6611 | DRM_DEBUG("IH: D5 vline\n"); |
| 6509 | } |
6612 | |
| 6510 | break; |
6613 | break; |
| 6511 | default: |
6614 | default: |
| 6512 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
6615 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 6513 | break; |
6616 | break; |
| 6514 | } |
6617 | } |
| 6515 | break; |
6618 | break; |
| 6516 | case 6: /* D6 vblank/vline */ |
6619 | case 6: /* D6 vblank/vline */ |
| 6517 | switch (src_data) { |
6620 | switch (src_data) { |
| 6518 | case 0: /* D6 vblank */ |
6621 | case 0: /* D6 vblank */ |
| - | 6622 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) |
|
| - | 6623 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6519 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { |
6624 | |
| 6520 | if (rdev->irq.crtc_vblank_int[5]) { |
6625 | if (rdev->irq.crtc_vblank_int[5]) { |
| 6521 | // drm_handle_vblank(rdev->ddev, 5); |
6626 | drm_handle_vblank(rdev->ddev, 5); |
| 6522 | rdev->pm.vblank_sync = true; |
6627 | rdev->pm.vblank_sync = true; |
| 6523 | // wake_up(&rdev->irq.vblank_queue); |
6628 | wake_up(&rdev->irq.vblank_queue); |
| 6524 | } |
6629 | } |
| 6525 | // if (atomic_read(&rdev->irq.pflip[5])) |
6630 | if (atomic_read(&rdev->irq.pflip[5])) |
| 6526 | // radeon_crtc_handle_flip(rdev, 5); |
6631 | radeon_crtc_handle_vblank(rdev, 5); |
| 6527 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; |
6632 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; |
| 6528 | DRM_DEBUG("IH: D6 vblank\n"); |
6633 | DRM_DEBUG("IH: D6 vblank\n"); |
| 6529 | } |
6634 | |
| 6530 | break; |
6635 | break; |
| 6531 | case 1: /* D6 vline */ |
6636 | case 1: /* D6 vline */ |
| - | 6637 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) |
|
| - | 6638 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| 6532 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { |
6639 | |
| 6533 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; |
6640 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; |
| 6534 | DRM_DEBUG("IH: D6 vline\n"); |
6641 | DRM_DEBUG("IH: D6 vline\n"); |
| 6535 | } |
6642 | |
| 6536 | break; |
6643 | break; |
| 6537 | default: |
6644 | default: |
| 6538 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
6645 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 6539 | break; |
6646 | break; |
| Line 6548... | Line 6655... | ||
| 6548 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); |
6655 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); |
| 6549 | break; |
6656 | break; |
| 6550 | case 42: /* HPD hotplug */ |
6657 | case 42: /* HPD hotplug */ |
| 6551 | switch (src_data) { |
6658 | switch (src_data) { |
| 6552 | case 0: |
6659 | case 0: |
| 6553 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { |
6660 | if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) |
| - | 6661 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6662 | ||
| 6554 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; |
6663 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; |
| 6555 | queue_hotplug = true; |
6664 | queue_hotplug = true; |
| 6556 | DRM_DEBUG("IH: HPD1\n"); |
6665 | DRM_DEBUG("IH: HPD1\n"); |
| 6557 | } |
6666 | |
| 6558 | break; |
6667 | break; |
| 6559 | case 1: |
6668 | case 1: |
| 6560 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { |
6669 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) |
| - | 6670 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6671 | ||
| 6561 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; |
6672 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; |
| 6562 | queue_hotplug = true; |
6673 | queue_hotplug = true; |
| 6563 | DRM_DEBUG("IH: HPD2\n"); |
6674 | DRM_DEBUG("IH: HPD2\n"); |
| 6564 | } |
6675 | |
| 6565 | break; |
6676 | break; |
| 6566 | case 2: |
6677 | case 2: |
| 6567 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
6678 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) |
| - | 6679 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6680 | ||
| 6568 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; |
6681 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; |
| 6569 | queue_hotplug = true; |
6682 | queue_hotplug = true; |
| 6570 | DRM_DEBUG("IH: HPD3\n"); |
6683 | DRM_DEBUG("IH: HPD3\n"); |
| 6571 | } |
6684 | |
| 6572 | break; |
6685 | break; |
| 6573 | case 3: |
6686 | case 3: |
| 6574 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
6687 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) |
| - | 6688 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6689 | ||
| 6575 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; |
6690 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; |
| 6576 | queue_hotplug = true; |
6691 | queue_hotplug = true; |
| 6577 | DRM_DEBUG("IH: HPD4\n"); |
6692 | DRM_DEBUG("IH: HPD4\n"); |
| 6578 | } |
6693 | |
| 6579 | break; |
6694 | break; |
| 6580 | case 4: |
6695 | case 4: |
| 6581 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
6696 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) |
| - | 6697 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6698 | ||
| 6582 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; |
6699 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; |
| 6583 | queue_hotplug = true; |
6700 | queue_hotplug = true; |
| 6584 | DRM_DEBUG("IH: HPD5\n"); |
6701 | DRM_DEBUG("IH: HPD5\n"); |
| 6585 | } |
6702 | |
| 6586 | break; |
6703 | break; |
| 6587 | case 5: |
6704 | case 5: |
| 6588 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
6705 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) |
| - | 6706 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6707 | ||
| 6589 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; |
6708 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; |
| 6590 | queue_hotplug = true; |
6709 | queue_hotplug = true; |
| 6591 | DRM_DEBUG("IH: HPD6\n"); |
6710 | DRM_DEBUG("IH: HPD6\n"); |
| - | 6711 | ||
| - | 6712 | break; |
|
| - | 6713 | case 6: |
|
| - | 6714 | if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) |
|
| - | 6715 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6716 | ||
| - | 6717 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; |
|
| - | 6718 | queue_dp = true; |
|
| - | 6719 | DRM_DEBUG("IH: HPD_RX 1\n"); |
|
| - | 6720 | ||
| - | 6721 | break; |
|
| - | 6722 | case 7: |
|
| - | 6723 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) |
|
| - | 6724 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6725 | ||
| - | 6726 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; |
|
| - | 6727 | queue_dp = true; |
|
| - | 6728 | DRM_DEBUG("IH: HPD_RX 2\n"); |
|
| - | 6729 | ||
| - | 6730 | break; |
|
| - | 6731 | case 8: |
|
| - | 6732 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) |
|
| - | 6733 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6734 | ||
| - | 6735 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; |
|
| - | 6736 | queue_dp = true; |
|
| - | 6737 | DRM_DEBUG("IH: HPD_RX 3\n"); |
|
| - | 6738 | ||
| - | 6739 | break; |
|
| - | 6740 | case 9: |
|
| - | 6741 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) |
|
| - | 6742 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6743 | ||
| - | 6744 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; |
|
| - | 6745 | queue_dp = true; |
|
| - | 6746 | DRM_DEBUG("IH: HPD_RX 4\n"); |
|
| - | 6747 | ||
| - | 6748 | break; |
|
| - | 6749 | case 10: |
|
| - | 6750 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) |
|
| - | 6751 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6752 | ||
| - | 6753 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; |
|
| - | 6754 | queue_dp = true; |
|
| - | 6755 | DRM_DEBUG("IH: HPD_RX 5\n"); |
|
| - | 6756 | ||
| 6592 | } |
6757 | break; |
| - | 6758 | case 11: |
|
| - | 6759 | if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) |
|
| - | 6760 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); |
|
| - | 6761 | ||
| - | 6762 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; |
|
| - | 6763 | queue_dp = true; |
|
| - | 6764 | DRM_DEBUG("IH: HPD_RX 6\n"); |
|
| - | 6765 | ||
| 6593 | break; |
6766 | break; |
| 6594 | default: |
6767 | default: |
| 6595 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
6768 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| 6596 | break; |
6769 | break; |
| 6597 | } |
6770 | } |
| 6598 | break; |
6771 | break; |
| - | 6772 | case 96: |
|
| - | 6773 | DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); |
|
| - | 6774 | WREG32(SRBM_INT_ACK, 0x1); |
|
| - | 6775 | break; |
|
| 6599 | case 124: /* UVD */ |
6776 | case 124: /* UVD */ |
| 6600 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); |
6777 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); |
| 6601 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); |
6778 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); |
| 6602 | break; |
6779 | break; |
| 6603 | case 146: |
6780 | case 146: |
| Line 6773... | Line 6950... | ||
| 6773 | } |
6950 | } |
| 6774 | if (r) |
6951 | if (r) |
| 6775 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
6952 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
| 6776 | } |
6953 | } |
| Line -... | Line 6954... | ||
| - | 6954 | ||
| - | 6955 | r = radeon_vce_resume(rdev); |
|
| - | 6956 | if (!r) { |
|
| - | 6957 | r = vce_v1_0_resume(rdev); |
|
| - | 6958 | if (!r) |
|
| - | 6959 | r = radeon_fence_driver_start_ring(rdev, |
|
| - | 6960 | TN_RING_TYPE_VCE1_INDEX); |
|
| - | 6961 | if (!r) |
|
| - | 6962 | r = radeon_fence_driver_start_ring(rdev, |
|
| - | 6963 | TN_RING_TYPE_VCE2_INDEX); |
|
| - | 6964 | } |
|
| - | 6965 | if (r) { |
|
| - | 6966 | dev_err(rdev->dev, "VCE init error (%d).\n", r); |
|
| - | 6967 | rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; |
|
| - | 6968 | rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; |
|
| - | 6969 | } |
|
| 6777 | 6970 | ||
| 6778 | /* Enable IRQ */ |
6971 | /* Enable IRQ */ |
| 6779 | if (!rdev->irq.installed) { |
6972 | if (!rdev->irq.installed) { |
| 6780 | r = radeon_irq_kms_init(rdev); |
6973 | r = radeon_irq_kms_init(rdev); |
| 6781 | if (r) |
6974 | if (r) |
| Line 6841... | Line 7034... | ||
| 6841 | if (r) |
7034 | if (r) |
| 6842 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
7035 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
| 6843 | } |
7036 | } |
| 6844 | } |
7037 | } |
| Line -... | Line 7038... | ||
| - | 7038 | ||
| - | 7039 | r = -ENOENT; |
|
| - | 7040 | ||
| - | 7041 | ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; |
|
| - | 7042 | if (ring->ring_size) |
|
| - | 7043 | r = radeon_ring_init(rdev, ring, ring->ring_size, 0, |
|
| - | 7044 | VCE_CMD_NO_OP); |
|
| - | 7045 | ||
| - | 7046 | ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; |
|
| - | 7047 | if (ring->ring_size) |
|
| - | 7048 | r = radeon_ring_init(rdev, ring, ring->ring_size, 0, |
|
| - | 7049 | VCE_CMD_NO_OP); |
|
| - | 7050 | ||
| - | 7051 | if (!r) |
|
| - | 7052 | r = vce_v1_0_init(rdev); |
|
| - | 7053 | else if (r != -ENOENT) |
|
| - | 7054 | DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); |
|
| 6845 | 7055 | ||
| 6846 | r = radeon_ib_pool_init(rdev); |
7056 | r = radeon_ib_pool_init(rdev); |
| 6847 | if (r) { |
7057 | if (r) { |
| 6848 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
7058 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 6849 | return r; |
7059 | return r; |
| Line 6853... | Line 7063... | ||
| 6853 | if (r) { |
7063 | if (r) { |
| 6854 | dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); |
7064 | dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); |
| 6855 | return r; |
7065 | return r; |
| 6856 | } |
7066 | } |
| Line 6857... | Line 7067... | ||
| 6857 | 7067 | ||
| 6858 | r = dce6_audio_init(rdev); |
7068 | r = radeon_audio_init(rdev); |
| 6859 | if (r) |
7069 | if (r) |
| Line 6860... | Line 7070... | ||
| 6860 | return r; |
7070 | return r; |
| 6861 | 7071 | ||
| Line -... | Line 7072... | ||
| - | 7072 | return 0; |
|
| - | 7073 | } |
|
| - | 7074 | ||
| - | 7075 | int si_resume(struct radeon_device *rdev) |
|
| - | 7076 | { |
|
| - | 7077 | int r; |
|
| - | 7078 | ||
| - | 7079 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
|
| - | 7080 | * posting will perform necessary task to bring back GPU into good |
|
| - | 7081 | * shape. |
|
| - | 7082 | */ |
|
| - | 7083 | /* post card */ |
|
| - | 7084 | atom_asic_init(rdev->mode_info.atom_context); |
|
| - | 7085 | ||
| - | 7086 | /* init golden registers */ |
|
| - | 7087 | si_init_golden_registers(rdev); |
|
| - | 7088 | ||
| - | 7089 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
|
| - | 7090 | radeon_pm_resume(rdev); |
|
| - | 7091 | ||
| - | 7092 | rdev->accel_working = true; |
|
| - | 7093 | r = si_startup(rdev); |
|
| - | 7094 | if (r) { |
|
| - | 7095 | DRM_ERROR("si startup failed on resume\n"); |
|
| Line -... | Line 7096... | ||
| - | 7096 | rdev->accel_working = false; |
|
| Line -... | Line 7097... | ||
| - | 7097 | return r; |
|
| Line 6862... | Line 7098... | ||
| 6862 | return 0; |
7098 | } |
| 6863 | } |
7099 | |
| 6864 | 7100 | return r; |
|
| 6865 | 7101 | ||
| Line 6961... | Line 7197... | ||
| 6961 | ring->ring_obj = NULL; |
7197 | ring->ring_obj = NULL; |
| 6962 | r600_ring_init(rdev, ring, 4096); |
7198 | r600_ring_init(rdev, ring, 4096); |
| 6963 | } |
7199 | } |
| 6964 | } |
7200 | } |
| Line -... | Line 7201... | ||
| - | 7201 | ||
| - | 7202 | r = radeon_vce_init(rdev); |
|
| - | 7203 | if (!r) { |
|
| - | 7204 | ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; |
|
| - | 7205 | ring->ring_obj = NULL; |
|
| - | 7206 | r600_ring_init(rdev, ring, 4096); |
|
| - | 7207 | ||
| - | 7208 | ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; |
|
| - | 7209 | ring->ring_obj = NULL; |
|
| - | 7210 | r600_ring_init(rdev, ring, 4096); |
|
| - | 7211 | } |
|
| 6965 | 7212 | ||
| 6966 | rdev->ih.ring_obj = NULL; |
7213 | rdev->ih.ring_obj = NULL; |
| Line 6967... | Line 7214... | ||
| 6967 | r600_ih_ring_init(rdev, 64 * 1024); |
7214 | r600_ih_ring_init(rdev, 64 * 1024); |
| 6968 | 7215 | ||
| Line 6973... | Line 7220... | ||
| 6973 | rdev->accel_working = true; |
7220 | rdev->accel_working = true; |
| 6974 | r = si_startup(rdev); |
7221 | r = si_startup(rdev); |
| 6975 | if (r) { |
7222 | if (r) { |
| 6976 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
7223 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
| 6977 | si_cp_fini(rdev); |
7224 | si_cp_fini(rdev); |
| - | 7225 | cayman_dma_fini(rdev); |
|
| 6978 | // si_irq_fini(rdev); |
7226 | si_irq_fini(rdev); |
| 6979 | // si_rlc_fini(rdev); |
7227 | sumo_rlc_fini(rdev); |
| 6980 | // radeon_wb_fini(rdev); |
7228 | radeon_wb_fini(rdev); |
| 6981 | // radeon_ib_pool_fini(rdev); |
7229 | radeon_ib_pool_fini(rdev); |
| 6982 | // radeon_vm_manager_fini(rdev); |
7230 | radeon_vm_manager_fini(rdev); |
| 6983 | // radeon_irq_kms_fini(rdev); |
7231 | radeon_irq_kms_fini(rdev); |
| 6984 | // si_pcie_gart_fini(rdev); |
7232 | si_pcie_gart_fini(rdev); |
| 6985 | rdev->accel_working = false; |
7233 | rdev->accel_working = false; |
| 6986 | } |
7234 | } |
| Line 6987... | Line 7235... | ||
| 6987 | 7235 | ||
| 6988 | /* Don't start up if the MC ucode is missing. |
7236 | /* Don't start up if the MC ucode is missing. |
| Line 6995... | Line 7243... | ||
| 6995 | } |
7243 | } |
| Line 6996... | Line 7244... | ||
| 6996 | 7244 | ||
| 6997 | return 0; |
7245 | return 0; |
| Line -... | Line 7246... | ||
| - | 7246 | } |
|
| - | 7247 | ||
| - | 7248 | void si_fini(struct radeon_device *rdev) |
|
| - | 7249 | { |
|
| - | 7250 | radeon_pm_fini(rdev); |
|
| - | 7251 | si_cp_fini(rdev); |
|
| - | 7252 | cayman_dma_fini(rdev); |
|
| - | 7253 | si_fini_pg(rdev); |
|
| - | 7254 | si_fini_cg(rdev); |
|
| - | 7255 | si_irq_fini(rdev); |
|
| - | 7256 | sumo_rlc_fini(rdev); |
|
| - | 7257 | radeon_wb_fini(rdev); |
|
| - | 7258 | radeon_vm_manager_fini(rdev); |
|
| - | 7259 | radeon_ib_pool_fini(rdev); |
|
| - | 7260 | radeon_irq_kms_fini(rdev); |
|
| - | 7261 | if (rdev->has_uvd) { |
|
| - | 7262 | uvd_v1_0_fini(rdev); |
|
| - | 7263 | radeon_uvd_fini(rdev); |
|
| - | 7264 | radeon_vce_fini(rdev); |
|
| - | 7265 | } |
|
| - | 7266 | si_pcie_gart_fini(rdev); |
|
| - | 7267 | r600_vram_scratch_fini(rdev); |
|
| - | 7268 | radeon_gem_fini(rdev); |
|
| - | 7269 | radeon_fence_driver_fini(rdev); |
|
| - | 7270 | radeon_bo_fini(rdev); |
|
| - | 7271 | radeon_atombios_fini(rdev); |
|
| - | 7272 | kfree(rdev->bios); |
|
| - | 7273 | rdev->bios = NULL; |
|
| 6998 | } |
7274 | } |
| 6999 | 7275 | ||
| 7000 | /** |
7276 | /** |
| 7001 | * si_get_gpu_clock_counter - return GPU clock counter snapshot |
7277 | * si_get_gpu_clock_counter - return GPU clock counter snapshot |
| 7002 | * |
7278 | * |
| Line 7029... | Line 7305... | ||
| 7029 | 7305 | ||
| 7030 | /* put PLL in bypass mode */ |
7306 | /* put PLL in bypass mode */ |
| Line 7031... | Line 7307... | ||
| 7031 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); |
7307 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); |
| 7032 | 7308 | ||
| 7033 | if (!vclk || !dclk) { |
- | |
| 7034 | /* keep the Bypass mode, put PLL to sleep */ |
7309 | if (!vclk || !dclk) { |
| 7035 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
7310 | /* keep the Bypass mode */ |
| Line 7036... | Line 7311... | ||
| 7036 | return 0; |
7311 | return 0; |
| 7037 | } |
7312 | } |
| Line 7046... | Line 7321... | ||
| 7046 | WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); |
7321 | WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); |
| Line 7047... | Line 7322... | ||
| 7047 | 7322 | ||
| 7048 | /* set VCO_MODE to 1 */ |
7323 | /* set VCO_MODE to 1 */ |
| Line 7049... | Line 7324... | ||
| 7049 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); |
7324 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); |
| 7050 | - | ||
| 7051 | /* toggle UPLL_SLEEP to 1 then back to 0 */ |
7325 | |
| Line 7052... | Line 7326... | ||
| 7052 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
7326 | /* disable sleep mode */ |
| 7053 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); |
7327 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); |
| Line 7466... | Line 7740... | ||
| 7466 | WREG32_PCIE_PORT(PCIE_LC_CNTL, data); |
7740 | WREG32_PCIE_PORT(PCIE_LC_CNTL, data); |
| 7467 | } |
7741 | } |
| 7468 | } |
7742 | } |
| 7469 | } |
7743 | } |
| 7470 | } |
7744 | } |
| - | 7745 | ||
| - | 7746 | int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev) |
|
| - | 7747 | { |
|
| - | 7748 | unsigned i; |
|
| - | 7749 | ||
| - | 7750 | /* make sure VCEPLL_CTLREQ is deasserted */ |
|
| - | 7751 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); |
|
| - | 7752 | ||
| - | 7753 | mdelay(10); |
|
| - | 7754 | ||
| - | 7755 | /* assert UPLL_CTLREQ */ |
|
| - | 7756 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); |
|
| - | 7757 | ||
| - | 7758 | /* wait for CTLACK and CTLACK2 to get asserted */ |
|
| - | 7759 | for (i = 0; i < 100; ++i) { |
|
| - | 7760 | uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; |
|
| - | 7761 | if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) |
|
| - | 7762 | break; |
|
| - | 7763 | mdelay(10); |
|
| - | 7764 | } |
|
| - | 7765 | ||
| - | 7766 | /* deassert UPLL_CTLREQ */ |
|
| - | 7767 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); |
|
| - | 7768 | ||
| - | 7769 | if (i == 100) { |
|
| - | 7770 | DRM_ERROR("Timeout setting UVD clocks!\n"); |
|
| - | 7771 | return -ETIMEDOUT; |
|
| - | 7772 | } |
|
| - | 7773 | ||
| - | 7774 | return 0; |
|
| - | 7775 | } |
|
| - | 7776 | ||
| - | 7777 | int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) |
|
| - | 7778 | { |
|
| - | 7779 | unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; |
|
| - | 7780 | int r; |
|
| - | 7781 | ||
| - | 7782 | /* bypass evclk and ecclk with bclk */ |
|
| - | 7783 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, |
|
| - | 7784 | EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1), |
|
| - | 7785 | ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK)); |
|
| - | 7786 | ||
| - | 7787 | /* put PLL in bypass mode */ |
|
| - | 7788 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK, |
|
| - | 7789 | ~VCEPLL_BYPASS_EN_MASK); |
|
| - | 7790 | ||
| - | 7791 | if (!evclk || !ecclk) { |
|
| - | 7792 | /* keep the Bypass mode, put PLL to sleep */ |
|
| - | 7793 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, |
|
| - | 7794 | ~VCEPLL_SLEEP_MASK); |
|
| - | 7795 | return 0; |
|
| - | 7796 | } |
|
| - | 7797 | ||
| - | 7798 | r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000, |
|
| - | 7799 | 16384, 0x03FFFFFF, 0, 128, 5, |
|
| - | 7800 | &fb_div, &evclk_div, &ecclk_div); |
|
| - | 7801 | if (r) |
|
| - | 7802 | return r; |
|
| - | 7803 | ||
| - | 7804 | /* set RESET_ANTI_MUX to 0 */ |
|
| - | 7805 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); |
|
| - | 7806 | ||
| - | 7807 | /* set VCO_MODE to 1 */ |
|
| - | 7808 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK, |
|
| - | 7809 | ~VCEPLL_VCO_MODE_MASK); |
|
| - | 7810 | ||
| - | 7811 | /* toggle VCEPLL_SLEEP to 1 then back to 0 */ |
|
| - | 7812 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, |
|
| - | 7813 | ~VCEPLL_SLEEP_MASK); |
|
| - | 7814 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); |
|
| - | 7815 | ||
| - | 7816 | /* deassert VCEPLL_RESET */ |
|
| - | 7817 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); |
|
| - | 7818 | ||
| - | 7819 | mdelay(1); |
|
| - | 7820 | ||
| - | 7821 | r = si_vce_send_vcepll_ctlreq(rdev); |
|
| - | 7822 | if (r) |
|
| - | 7823 | return r; |
|
| - | 7824 | ||
| - | 7825 | /* assert VCEPLL_RESET again */ |
|
| - | 7826 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK); |
|
| - | 7827 | ||
| - | 7828 | /* disable spread spectrum. */ |
|
| - | 7829 | WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); |
|
| - | 7830 | ||
| - | 7831 | /* set feedback divider */ |
|
| - | 7832 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK); |
|
| - | 7833 | ||
| - | 7834 | /* set ref divider to 0 */ |
|
| - | 7835 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); |
|
| - | 7836 | ||
| - | 7837 | /* set PDIV_A and PDIV_B */ |
|
| - | 7838 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, |
|
| - | 7839 | VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div), |
|
| - | 7840 | ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK)); |
|
| - | 7841 | ||
| - | 7842 | /* give the PLL some time to settle */ |
|
| - | 7843 | mdelay(15); |
|
| - | 7844 | ||
| - | 7845 | /* deassert PLL_RESET */ |
|
| - | 7846 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); |
|
| - | 7847 | ||
| - | 7848 | mdelay(15); |
|
| - | 7849 | ||
| - | 7850 | /* switch from bypass mode to normal mode */ |
|
| - | 7851 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); |
|
| - | 7852 | ||
| - | 7853 | r = si_vce_send_vcepll_ctlreq(rdev); |
|
| - | 7854 | if (r) |
|
| - | 7855 | return r; |
|
| - | 7856 | ||
| - | 7857 | /* switch VCLK and DCLK selection */ |
|
| - | 7858 | WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, |
|
| - | 7859 | EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16), |
|
| - | 7860 | ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK)); |
|
| - | 7861 | ||
| - | 7862 | mdelay(100); |
|
| - | 7863 | ||
| - | 7864 | return 0; |
|
| - | 7865 | } |
|