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Rev 3120 | Rev 3192 | ||
---|---|---|---|
Line 1658... | Line 1658... | ||
1658 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
1658 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
Line 1659... | Line 1659... | ||
1659 | 1659 | ||
1660 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
1660 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
1661 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
1661 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
- | 1662 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
|
- | 1663 | WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); |
|
Line 1662... | Line 1664... | ||
1662 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
1664 | WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); |
Line 1663... | Line 1665... | ||
1663 | 1665 | ||
1664 | si_tiling_mode_table_init(rdev); |
1666 | si_tiling_mode_table_init(rdev); |
Line 1831... | Line 1833... | ||
1831 | static void si_cp_enable(struct radeon_device *rdev, bool enable) |
1833 | static void si_cp_enable(struct radeon_device *rdev, bool enable) |
1832 | { |
1834 | { |
1833 | if (enable) |
1835 | if (enable) |
1834 | WREG32(CP_ME_CNTL, 0); |
1836 | WREG32(CP_ME_CNTL, 0); |
1835 | else { |
1837 | else { |
1836 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
1838 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
1837 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); |
1839 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); |
1838 | WREG32(SCRATCH_UMSK, 0); |
1840 | WREG32(SCRATCH_UMSK, 0); |
- | 1841 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
|
- | 1842 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; |
|
- | 1843 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; |
|
1839 | } |
1844 | } |
1840 | udelay(50); |
1845 | udelay(50); |
1841 | } |
1846 | } |
Line 1842... | Line 1847... | ||
1842 | 1847 | ||
Line 2119... | Line 2124... | ||
2119 | /* force CP activities */ |
2124 | /* force CP activities */ |
2120 | radeon_ring_force_activity(rdev, ring); |
2125 | radeon_ring_force_activity(rdev, ring); |
2121 | return radeon_ring_test_lockup(rdev, ring); |
2126 | return radeon_ring_test_lockup(rdev, ring); |
2122 | } |
2127 | } |
Line 2123... | Line 2128... | ||
2123 | 2128 | ||
2124 | static int si_gpu_soft_reset(struct radeon_device *rdev) |
2129 | static void si_gpu_soft_reset_gfx(struct radeon_device *rdev) |
2125 | { |
- | |
2126 | struct evergreen_mc_save save; |
2130 | { |
Line 2127... | Line 2131... | ||
2127 | u32 grbm_reset = 0; |
2131 | u32 grbm_reset = 0; |
2128 | 2132 | ||
Line 2129... | Line -... | ||
2129 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
- | |
2130 | return 0; |
2133 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
2131 | 2134 | return; |
|
2132 | dev_info(rdev->dev, "GPU softreset \n"); |
2135 | |
2133 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
2136 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
2134 | RREG32(GRBM_STATUS)); |
2137 | RREG32(GRBM_STATUS)); |
2135 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", |
2138 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", |
2136 | RREG32(GRBM_STATUS2)); |
2139 | RREG32(GRBM_STATUS2)); |
2137 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
2140 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
2138 | RREG32(GRBM_STATUS_SE0)); |
2141 | RREG32(GRBM_STATUS_SE0)); |
2139 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
2142 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
2140 | RREG32(GRBM_STATUS_SE1)); |
- | |
2141 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
- | |
2142 | RREG32(SRBM_STATUS)); |
- | |
2143 | evergreen_mc_stop(rdev, &save); |
2143 | RREG32(GRBM_STATUS_SE1)); |
2144 | if (radeon_mc_wait_for_idle(rdev)) { |
2144 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
2145 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
2145 | RREG32(SRBM_STATUS)); |
Line 2146... | Line 2146... | ||
2146 | } |
2146 | |
2147 | /* Disable CP parsing/prefetching */ |
2147 | /* Disable CP parsing/prefetching */ |
Line 2166... | Line 2166... | ||
2166 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
2166 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
2167 | (void)RREG32(GRBM_SOFT_RESET); |
2167 | (void)RREG32(GRBM_SOFT_RESET); |
2168 | udelay(50); |
2168 | udelay(50); |
2169 | WREG32(GRBM_SOFT_RESET, 0); |
2169 | WREG32(GRBM_SOFT_RESET, 0); |
2170 | (void)RREG32(GRBM_SOFT_RESET); |
2170 | (void)RREG32(GRBM_SOFT_RESET); |
2171 | /* Wait a little for things to settle down */ |
- | |
2172 | udelay(50); |
2171 | |
2173 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
2172 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
2174 | RREG32(GRBM_STATUS)); |
2173 | RREG32(GRBM_STATUS)); |
2175 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", |
2174 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", |
2176 | RREG32(GRBM_STATUS2)); |
2175 | RREG32(GRBM_STATUS2)); |
2177 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
2176 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
2178 | RREG32(GRBM_STATUS_SE0)); |
2177 | RREG32(GRBM_STATUS_SE0)); |
2179 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
2178 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
2180 | RREG32(GRBM_STATUS_SE1)); |
2179 | RREG32(GRBM_STATUS_SE1)); |
2181 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
2180 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
2182 | RREG32(SRBM_STATUS)); |
2181 | RREG32(SRBM_STATUS)); |
- | 2182 | } |
|
- | 2183 | ||
- | 2184 | static void si_gpu_soft_reset_dma(struct radeon_device *rdev) |
|
- | 2185 | { |
|
- | 2186 | u32 tmp; |
|
- | 2187 | ||
- | 2188 | if (RREG32(DMA_STATUS_REG) & DMA_IDLE) |
|
- | 2189 | return; |
|
- | 2190 | ||
- | 2191 | dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", |
|
- | 2192 | RREG32(DMA_STATUS_REG)); |
|
- | 2193 | ||
- | 2194 | /* dma0 */ |
|
- | 2195 | tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); |
|
- | 2196 | tmp &= ~DMA_RB_ENABLE; |
|
- | 2197 | WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); |
|
- | 2198 | ||
- | 2199 | /* dma1 */ |
|
- | 2200 | tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); |
|
- | 2201 | tmp &= ~DMA_RB_ENABLE; |
|
- | 2202 | WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); |
|
- | 2203 | ||
- | 2204 | /* Reset dma */ |
|
- | 2205 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); |
|
- | 2206 | RREG32(SRBM_SOFT_RESET); |
|
- | 2207 | udelay(50); |
|
- | 2208 | WREG32(SRBM_SOFT_RESET, 0); |
|
- | 2209 | ||
- | 2210 | dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", |
|
- | 2211 | RREG32(DMA_STATUS_REG)); |
|
- | 2212 | } |
|
- | 2213 | ||
- | 2214 | static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) |
|
- | 2215 | { |
|
- | 2216 | struct evergreen_mc_save save; |
|
- | 2217 | ||
- | 2218 | if (reset_mask == 0) |
|
- | 2219 | return 0; |
|
- | 2220 | ||
- | 2221 | dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); |
|
- | 2222 | ||
- | 2223 | dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
|
- | 2224 | RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); |
|
- | 2225 | dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", |
|
- | 2226 | RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); |
|
- | 2227 | ||
- | 2228 | evergreen_mc_stop(rdev, &save); |
|
- | 2229 | if (radeon_mc_wait_for_idle(rdev)) { |
|
- | 2230 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
|
- | 2231 | } |
|
- | 2232 | ||
- | 2233 | if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) |
|
- | 2234 | si_gpu_soft_reset_gfx(rdev); |
|
- | 2235 | ||
- | 2236 | if (reset_mask & RADEON_RESET_DMA) |
|
- | 2237 | si_gpu_soft_reset_dma(rdev); |
|
- | 2238 | ||
- | 2239 | /* Wait a little for things to settle down */ |
|
- | 2240 | udelay(50); |
|
- | 2241 | ||
2183 | evergreen_mc_resume(rdev, &save); |
2242 | evergreen_mc_resume(rdev, &save); |
2184 | return 0; |
2243 | return 0; |
2185 | } |
2244 | } |
Line 2186... | Line 2245... | ||
2186 | 2245 | ||
2187 | int si_asic_reset(struct radeon_device *rdev) |
2246 | int si_asic_reset(struct radeon_device *rdev) |
2188 | { |
2247 | { |
- | 2248 | return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX | |
|
- | 2249 | RADEON_RESET_COMPUTE | |
|
2189 | return si_gpu_soft_reset(rdev); |
2250 | RADEON_RESET_DMA)); |
Line 2190... | Line 2251... | ||
2190 | } |
2251 | } |
2191 | 2252 | ||
2192 | /* MC */ |
2253 | /* MC */ |
Line 2424... | Line 2485... | ||
2424 | } |
2485 | } |
Line 2425... | Line 2486... | ||
2425 | 2486 | ||
2426 | /* enable context1-15 */ |
2487 | /* enable context1-15 */ |
2427 | WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
2488 | WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
2428 | (u32)(rdev->dummy_page.addr >> 12)); |
2489 | (u32)(rdev->dummy_page.addr >> 12)); |
2429 | WREG32(VM_CONTEXT1_CNTL2, 0); |
2490 | WREG32(VM_CONTEXT1_CNTL2, 4); |
- | 2491 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
|
2430 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
2492 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
- | 2493 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
|
- | 2494 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
|
- | 2495 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
|
- | 2496 | PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | |
|
- | 2497 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | |
|
- | 2498 | VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | |
|
- | 2499 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT | |
|
- | 2500 | READ_PROTECTION_FAULT_ENABLE_INTERRUPT | |
|
- | 2501 | READ_PROTECTION_FAULT_ENABLE_DEFAULT | |
|
- | 2502 | WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
|
Line 2431... | Line 2503... | ||
2431 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
2503 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); |
2432 | 2504 | ||
2433 | si_pcie_gart_tlb_flush(rdev); |
2505 | si_pcie_gart_tlb_flush(rdev); |
2434 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
2506 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
Line 2532... | Line 2604... | ||
2532 | u32 *ib, struct radeon_cs_packet *pkt) |
2604 | u32 *ib, struct radeon_cs_packet *pkt) |
2533 | { |
2605 | { |
2534 | u32 idx = pkt->idx + 1; |
2606 | u32 idx = pkt->idx + 1; |
2535 | u32 idx_value = ib[idx]; |
2607 | u32 idx_value = ib[idx]; |
2536 | u32 start_reg, end_reg, reg, i; |
2608 | u32 start_reg, end_reg, reg, i; |
- | 2609 | u32 command, info; |
|
Line 2537... | Line 2610... | ||
2537 | 2610 | ||
2538 | switch (pkt->opcode) { |
2611 | switch (pkt->opcode) { |
2539 | case PACKET3_NOP: |
2612 | case PACKET3_NOP: |
2540 | case PACKET3_SET_BASE: |
2613 | case PACKET3_SET_BASE: |
Line 2631... | Line 2704... | ||
2631 | reg = start_reg + (4 * i); |
2704 | reg = start_reg + (4 * i); |
2632 | if (!si_vm_reg_valid(reg)) |
2705 | if (!si_vm_reg_valid(reg)) |
2633 | return -EINVAL; |
2706 | return -EINVAL; |
2634 | } |
2707 | } |
2635 | break; |
2708 | break; |
- | 2709 | case PACKET3_CP_DMA: |
|
- | 2710 | command = ib[idx + 4]; |
|
- | 2711 | info = ib[idx + 1]; |
|
- | 2712 | if (command & PACKET3_CP_DMA_CMD_SAS) { |
|
- | 2713 | /* src address space is register */ |
|
- | 2714 | if (((info & 0x60000000) >> 29) == 0) { |
|
- | 2715 | start_reg = idx_value << 2; |
|
- | 2716 | if (command & PACKET3_CP_DMA_CMD_SAIC) { |
|
- | 2717 | reg = start_reg; |
|
- | 2718 | if (!si_vm_reg_valid(reg)) { |
|
- | 2719 | DRM_ERROR("CP DMA Bad SRC register\n"); |
|
- | 2720 | return -EINVAL; |
|
- | 2721 | } |
|
- | 2722 | } else { |
|
- | 2723 | for (i = 0; i < (command & 0x1fffff); i++) { |
|
- | 2724 | reg = start_reg + (4 * i); |
|
- | 2725 | if (!si_vm_reg_valid(reg)) { |
|
- | 2726 | DRM_ERROR("CP DMA Bad SRC register\n"); |
|
- | 2727 | return -EINVAL; |
|
- | 2728 | } |
|
- | 2729 | } |
|
- | 2730 | } |
|
- | 2731 | } |
|
- | 2732 | } |
|
- | 2733 | if (command & PACKET3_CP_DMA_CMD_DAS) { |
|
- | 2734 | /* dst address space is register */ |
|
- | 2735 | if (((info & 0x00300000) >> 20) == 0) { |
|
- | 2736 | start_reg = ib[idx + 2]; |
|
- | 2737 | if (command & PACKET3_CP_DMA_CMD_DAIC) { |
|
- | 2738 | reg = start_reg; |
|
- | 2739 | if (!si_vm_reg_valid(reg)) { |
|
- | 2740 | DRM_ERROR("CP DMA Bad DST register\n"); |
|
- | 2741 | return -EINVAL; |
|
- | 2742 | } |
|
- | 2743 | } else { |
|
- | 2744 | for (i = 0; i < (command & 0x1fffff); i++) { |
|
- | 2745 | reg = start_reg + (4 * i); |
|
- | 2746 | if (!si_vm_reg_valid(reg)) { |
|
- | 2747 | DRM_ERROR("CP DMA Bad DST register\n"); |
|
- | 2748 | return -EINVAL; |
|
- | 2749 | } |
|
- | 2750 | } |
|
- | 2751 | } |
|
- | 2752 | } |
|
- | 2753 | } |
|
- | 2754 | break; |
|
2636 | default: |
2755 | default: |
2637 | DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); |
2756 | DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); |
2638 | return -EINVAL; |
2757 | return -EINVAL; |
2639 | } |
2758 | } |
2640 | return 0; |
2759 | return 0; |
Line 2807... | Line 2926... | ||
2807 | uint64_t addr, unsigned count, |
2926 | uint64_t addr, unsigned count, |
2808 | uint32_t incr, uint32_t flags) |
2927 | uint32_t incr, uint32_t flags) |
2809 | { |
2928 | { |
2810 | struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; |
2929 | struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; |
2811 | uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); |
2930 | uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); |
- | 2931 | uint64_t value; |
|
- | 2932 | unsigned ndw; |
|
Line -... | Line 2933... | ||
- | 2933 | ||
2812 | 2934 | if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) { |
|
2813 | while (count) { |
2935 | while (count) { |
2814 | unsigned ndw = 2 + count * 2; |
2936 | ndw = 2 + count * 2; |
2815 | if (ndw > 0x3FFE) |
2937 | if (ndw > 0x3FFE) |
Line 2816... | Line 2938... | ||
2816 | ndw = 0x3FFE; |
2938 | ndw = 0x3FFE; |
2817 | 2939 | ||
2818 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw)); |
2940 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw)); |
2819 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | |
2941 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | |
2820 | WRITE_DATA_DST_SEL(1))); |
2942 | WRITE_DATA_DST_SEL(1))); |
2821 | radeon_ring_write(ring, pe); |
2943 | radeon_ring_write(ring, pe); |
2822 | radeon_ring_write(ring, upper_32_bits(pe)); |
- | |
2823 | for (; ndw > 2; ndw -= 2, --count, pe += 8) { |
2944 | radeon_ring_write(ring, upper_32_bits(pe)); |
2824 | uint64_t value; |
2945 | for (; ndw > 2; ndw -= 2, --count, pe += 8) { |
2825 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
2946 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
2826 | value = radeon_vm_map_gart(rdev, addr); |
2947 | value = radeon_vm_map_gart(rdev, addr); |
2827 | value &= 0xFFFFFFFFFFFFF000ULL; |
2948 | value &= 0xFFFFFFFFFFFFF000ULL; |
2828 | } else if (flags & RADEON_VM_PAGE_VALID) |
2949 | } else if (flags & RADEON_VM_PAGE_VALID) { |
2829 | value = addr; |
2950 | value = addr; |
- | 2951 | } else { |
|
2830 | else |
2952 | value = 0; |
2831 | value = 0; |
2953 | } |
2832 | addr += incr; |
2954 | addr += incr; |
2833 | value |= r600_flags; |
2955 | value |= r600_flags; |
2834 | radeon_ring_write(ring, value); |
2956 | radeon_ring_write(ring, value); |
2835 | radeon_ring_write(ring, upper_32_bits(value)); |
2957 | radeon_ring_write(ring, upper_32_bits(value)); |
- | 2958 | } |
|
- | 2959 | } |
|
- | 2960 | } else { |
|
- | 2961 | /* DMA */ |
|
- | 2962 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
|
- | 2963 | while (count) { |
|
- | 2964 | ndw = count * 2; |
|
- | 2965 | if (ndw > 0xFFFFE) |
|
- | 2966 | ndw = 0xFFFFE; |
|
- | 2967 | ||
- | 2968 | /* for non-physically contiguous pages (system) */ |
|
- | 2969 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw)); |
|
- | 2970 | radeon_ring_write(ring, pe); |
|
- | 2971 | radeon_ring_write(ring, upper_32_bits(pe) & 0xff); |
|
- | 2972 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
|
- | 2973 | if (flags & RADEON_VM_PAGE_SYSTEM) { |
|
- | 2974 | value = radeon_vm_map_gart(rdev, addr); |
|
- | 2975 | value &= 0xFFFFFFFFFFFFF000ULL; |
|
- | 2976 | } else if (flags & RADEON_VM_PAGE_VALID) { |
|
- | 2977 | value = addr; |
|
- | 2978 | } else { |
|
- | 2979 | value = 0; |
|
- | 2980 | } |
|
- | 2981 | addr += incr; |
|
- | 2982 | value |= r600_flags; |
|
- | 2983 | radeon_ring_write(ring, value); |
|
- | 2984 | radeon_ring_write(ring, upper_32_bits(value)); |
|
- | 2985 | } |
|
- | 2986 | } |
|
- | 2987 | } else { |
|
- | 2988 | while (count) { |
|
- | 2989 | ndw = count * 2; |
|
- | 2990 | if (ndw > 0xFFFFE) |
|
- | 2991 | ndw = 0xFFFFE; |
|
- | 2992 | ||
- | 2993 | if (flags & RADEON_VM_PAGE_VALID) |
|
- | 2994 | value = addr; |
|
- | 2995 | else |
|
- | 2996 | value = 0; |
|
- | 2997 | /* for physically contiguous pages (vram) */ |
|
- | 2998 | radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw)); |
|
- | 2999 | radeon_ring_write(ring, pe); /* dst addr */ |
|
- | 3000 | radeon_ring_write(ring, upper_32_bits(pe) & 0xff); |
|
- | 3001 | radeon_ring_write(ring, r600_flags); /* mask */ |
|
- | 3002 | radeon_ring_write(ring, 0); |
|
- | 3003 | radeon_ring_write(ring, value); /* value */ |
|
- | 3004 | radeon_ring_write(ring, upper_32_bits(value)); |
|
- | 3005 | radeon_ring_write(ring, incr); /* increment size */ |
|
- | 3006 | radeon_ring_write(ring, 0); |
|
- | 3007 | pe += ndw * 4; |
|
- | 3008 | addr += (ndw / 2) * incr; |
|
- | 3009 | count -= ndw / 2; |
|
- | 3010 | } |
|
2836 | } |
3011 | } |
Line 2837... | Line 3012... | ||
2837 | } |
3012 | } |
2838 | } |
3013 | } |
2839 | 3014 | ||
Line 2878... | Line 3053... | ||
2878 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
3053 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
2879 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
3054 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
2880 | radeon_ring_write(ring, 0x0); |
3055 | radeon_ring_write(ring, 0x0); |
2881 | } |
3056 | } |
Line -... | Line 3057... | ||
- | 3057 | ||
- | 3058 | void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) |
|
- | 3059 | { |
|
- | 3060 | struct radeon_ring *ring = &rdev->ring[ridx]; |
|
- | 3061 | ||
- | 3062 | if (vm == NULL) |
|
- | 3063 | return; |
|
- | 3064 | ||
- | 3065 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); |
|
- | 3066 | if (vm->id < 8) { |
|
- | 3067 | radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2)); |
|
- | 3068 | } else { |
|
- | 3069 | radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2)); |
|
- | 3070 | } |
|
- | 3071 | radeon_ring_write(ring, vm->pd_gpu_addr >> 12); |
|
- | 3072 | ||
- | 3073 | /* flush hdp cache */ |
|
- | 3074 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); |
|
- | 3075 | radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); |
|
- | 3076 | radeon_ring_write(ring, 1); |
|
- | 3077 | ||
- | 3078 | /* bits 0-7 are the VM contexts0-7 */ |
|
- | 3079 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); |
|
- | 3080 | radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); |
|
- | 3081 | radeon_ring_write(ring, 1 << vm->id); |
|
- | 3082 | } |
|
2882 | 3083 | ||
2883 | /* |
3084 | /* |
2884 | * RLC |
3085 | * RLC |
2885 | */ |
3086 | */ |
2886 | void si_rlc_fini(struct radeon_device *rdev) |
3087 | void si_rlc_fini(struct radeon_device *rdev) |
Line 3046... | Line 3247... | ||
3046 | u32 tmp; |
3247 | u32 tmp; |
Line 3047... | Line 3248... | ||
3047 | 3248 | ||
3048 | WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
3249 | WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
3049 | WREG32(CP_INT_CNTL_RING1, 0); |
3250 | WREG32(CP_INT_CNTL_RING1, 0); |
- | 3251 | WREG32(CP_INT_CNTL_RING2, 0); |
|
- | 3252 | tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; |
|
- | 3253 | WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); |
|
- | 3254 | tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
|
3050 | WREG32(CP_INT_CNTL_RING2, 0); |
3255 | WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); |
3051 | WREG32(GRBM_INT_CNTL, 0); |
3256 | WREG32(GRBM_INT_CNTL, 0); |
3052 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
3257 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
3053 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
3258 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
3054 | if (rdev->num_crtc >= 4) { |
3259 | if (rdev->num_crtc >= 4) { |
Line 3165... | Line 3370... | ||
3165 | u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; |
3370 | u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; |
3166 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
3371 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
3167 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
3372 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
3168 | u32 grbm_int_cntl = 0; |
3373 | u32 grbm_int_cntl = 0; |
3169 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
3374 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
- | 3375 | u32 dma_cntl, dma_cntl1; |
|
Line 3170... | Line 3376... | ||
3170 | 3376 | ||
3171 | if (!rdev->irq.installed) { |
3377 | if (!rdev->irq.installed) { |
3172 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
3378 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
3173 | return -EINVAL; |
3379 | return -EINVAL; |
Line 3185... | Line 3391... | ||
3185 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3391 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3186 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3392 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3187 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3393 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3188 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3394 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
Line -... | Line 3395... | ||
- | 3395 | ||
- | 3396 | dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; |
|
- | 3397 | dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
|
3189 | 3398 | ||
3190 | /* enable CP interrupts on all rings */ |
3399 | /* enable CP interrupts on all rings */ |
3191 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
3400 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
3192 | DRM_DEBUG("si_irq_set: sw int gfx\n"); |
3401 | DRM_DEBUG("si_irq_set: sw int gfx\n"); |
3193 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
3402 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
Line 3198... | Line 3407... | ||
3198 | } |
3407 | } |
3199 | if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { |
3408 | if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { |
3200 | DRM_DEBUG("si_irq_set: sw int cp2\n"); |
3409 | DRM_DEBUG("si_irq_set: sw int cp2\n"); |
3201 | cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; |
3410 | cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; |
3202 | } |
3411 | } |
- | 3412 | if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { |
|
- | 3413 | DRM_DEBUG("si_irq_set: sw int dma\n"); |
|
- | 3414 | dma_cntl |= TRAP_ENABLE; |
|
- | 3415 | } |
|
- | 3416 | ||
- | 3417 | if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { |
|
- | 3418 | DRM_DEBUG("si_irq_set: sw int dma1\n"); |
|
- | 3419 | dma_cntl1 |= TRAP_ENABLE; |
|
- | 3420 | } |
|
3203 | if (rdev->irq.crtc_vblank_int[0] || |
3421 | if (rdev->irq.crtc_vblank_int[0] || |
3204 | atomic_read(&rdev->irq.pflip[0])) { |
3422 | atomic_read(&rdev->irq.pflip[0])) { |
3205 | DRM_DEBUG("si_irq_set: vblank 0\n"); |
3423 | DRM_DEBUG("si_irq_set: vblank 0\n"); |
3206 | crtc1 |= VBLANK_INT_MASK; |
3424 | crtc1 |= VBLANK_INT_MASK; |
3207 | } |
3425 | } |
Line 3257... | Line 3475... | ||
3257 | 3475 | ||
3258 | WREG32(CP_INT_CNTL_RING0, cp_int_cntl); |
3476 | WREG32(CP_INT_CNTL_RING0, cp_int_cntl); |
3259 | WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); |
3477 | WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); |
Line -... | Line 3478... | ||
- | 3478 | WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); |
|
- | 3479 | ||
- | 3480 | WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); |
|
3260 | WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); |
3481 | WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); |
Line 3261... | Line 3482... | ||
3261 | 3482 | ||
3262 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
3483 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
3263 | 3484 | ||
Line 3682... | Line 3903... | ||
3682 | default: |
3903 | default: |
3683 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
3904 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
3684 | break; |
3905 | break; |
3685 | } |
3906 | } |
3686 | break; |
3907 | break; |
- | 3908 | case 146: |
|
- | 3909 | case 147: |
|
- | 3910 | dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); |
|
- | 3911 | dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
|
- | 3912 | RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); |
|
- | 3913 | dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", |
|
- | 3914 | RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); |
|
- | 3915 | /* reset addr and status */ |
|
- | 3916 | WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); |
|
- | 3917 | break; |
|
3687 | case 176: /* RINGID0 CP_INT */ |
3918 | case 176: /* RINGID0 CP_INT */ |
3688 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3919 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3689 | break; |
3920 | break; |
3690 | case 177: /* RINGID1 CP_INT */ |
3921 | case 177: /* RINGID1 CP_INT */ |
3691 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); |
3922 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); |
Line 3705... | Line 3936... | ||
3705 | case 2: |
3936 | case 2: |
3706 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); |
3937 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); |
3707 | break; |
3938 | break; |
3708 | } |
3939 | } |
3709 | break; |
3940 | break; |
- | 3941 | case 224: /* DMA trap event */ |
|
- | 3942 | DRM_DEBUG("IH: DMA trap\n"); |
|
- | 3943 | radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); |
|
- | 3944 | break; |
|
3710 | case 233: /* GUI IDLE */ |
3945 | case 233: /* GUI IDLE */ |
3711 | DRM_DEBUG("IH: GUI idle\n"); |
3946 | DRM_DEBUG("IH: GUI idle\n"); |
3712 | break; |
3947 | break; |
- | 3948 | case 244: /* DMA trap event */ |
|
- | 3949 | DRM_DEBUG("IH: DMA1 trap\n"); |
|
- | 3950 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); |
|
- | 3951 | break; |
|
3713 | default: |
3952 | default: |
3714 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
3953 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
3715 | break; |
3954 | break; |
3716 | } |
3955 | } |
Line 3731... | Line 3970... | ||
3731 | goto restart_ih; |
3970 | goto restart_ih; |
Line 3732... | Line 3971... | ||
3732 | 3971 | ||
3733 | return IRQ_HANDLED; |
3972 | return IRQ_HANDLED; |
Line -... | Line 3973... | ||
- | 3973 | } |
|
- | 3974 | ||
- | 3975 | /** |
|
- | 3976 | * si_copy_dma - copy pages using the DMA engine |
|
- | 3977 | * |
|
- | 3978 | * @rdev: radeon_device pointer |
|
- | 3979 | * @src_offset: src GPU address |
|
- | 3980 | * @dst_offset: dst GPU address |
|
- | 3981 | * @num_gpu_pages: number of GPU pages to xfer |
|
- | 3982 | * @fence: radeon fence object |
|
- | 3983 | * |
|
- | 3984 | * Copy GPU paging using the DMA engine (SI). |
|
- | 3985 | * Used by the radeon ttm implementation to move pages if |
|
- | 3986 | * registered as the asic copy callback. |
|
- | 3987 | */ |
|
- | 3988 | int si_copy_dma(struct radeon_device *rdev, |
|
- | 3989 | uint64_t src_offset, uint64_t dst_offset, |
|
- | 3990 | unsigned num_gpu_pages, |
|
- | 3991 | struct radeon_fence **fence) |
|
- | 3992 | { |
|
- | 3993 | struct radeon_semaphore *sem = NULL; |
|
- | 3994 | int ring_index = rdev->asic->copy.dma_ring_index; |
|
- | 3995 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
|
- | 3996 | u32 size_in_bytes, cur_size_in_bytes; |
|
- | 3997 | int i, num_loops; |
|
- | 3998 | int r = 0; |
|
- | 3999 | ||
- | 4000 | r = radeon_semaphore_create(rdev, &sem); |
|
- | 4001 | if (r) { |
|
- | 4002 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
|
- | 4003 | return r; |
|
- | 4004 | } |
|
- | 4005 | ||
- | 4006 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); |
|
- | 4007 | num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff); |
|
- | 4008 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); |
|
- | 4009 | if (r) { |
|
- | 4010 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
|
- | 4011 | radeon_semaphore_free(rdev, &sem, NULL); |
|
- | 4012 | return r; |
|
- | 4013 | } |
|
- | 4014 | ||
- | 4015 | if (radeon_fence_need_sync(*fence, ring->idx)) { |
|
- | 4016 | radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, |
|
- | 4017 | ring->idx); |
|
- | 4018 | radeon_fence_note_sync(*fence, ring->idx); |
|
- | 4019 | } else { |
|
- | 4020 | radeon_semaphore_free(rdev, &sem, NULL); |
|
- | 4021 | } |
|
- | 4022 | ||
- | 4023 | for (i = 0; i < num_loops; i++) { |
|
- | 4024 | cur_size_in_bytes = size_in_bytes; |
|
- | 4025 | if (cur_size_in_bytes > 0xFFFFF) |
|
- | 4026 | cur_size_in_bytes = 0xFFFFF; |
|
- | 4027 | size_in_bytes -= cur_size_in_bytes; |
|
- | 4028 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); |
|
- | 4029 | radeon_ring_write(ring, dst_offset & 0xffffffff); |
|
- | 4030 | radeon_ring_write(ring, src_offset & 0xffffffff); |
|
- | 4031 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); |
|
- | 4032 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
|
- | 4033 | src_offset += cur_size_in_bytes; |
|
- | 4034 | dst_offset += cur_size_in_bytes; |
|
- | 4035 | } |
|
- | 4036 | ||
- | 4037 | r = radeon_fence_emit(rdev, fence, ring->idx); |
|
- | 4038 | if (r) { |
|
- | 4039 | radeon_ring_unlock_undo(rdev, ring); |
|
- | 4040 | return r; |
|
- | 4041 | } |
|
- | 4042 | ||
- | 4043 | radeon_ring_unlock_commit(rdev, ring); |
|
- | 4044 | radeon_semaphore_free(rdev, &sem, *fence); |
|
- | 4045 | ||
- | 4046 | return r; |
|
3734 | } |
4047 | } |
3735 | 4048 | ||
3736 | /* |
4049 | /* |
3737 | * startup/shutdown callbacks |
4050 | * startup/shutdown callbacks |
3738 | */ |
4051 | */ |
Line 3802... | Line 4115... | ||
3802 | if (r) { |
4115 | if (r) { |
3803 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
4116 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
3804 | return r; |
4117 | return r; |
3805 | } |
4118 | } |
Line -... | Line 4119... | ||
- | 4119 | ||
- | 4120 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
|
- | 4121 | if (r) { |
|
- | 4122 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
|
- | 4123 | return r; |
|
- | 4124 | } |
|
- | 4125 | ||
- | 4126 | r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); |
|
- | 4127 | if (r) { |
|
- | 4128 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
|
- | 4129 | return r; |
|
- | 4130 | } |
|
3806 | 4131 | ||
3807 | /* Enable IRQ */ |
4132 | /* Enable IRQ */ |
3808 | r = si_irq_init(rdev); |
4133 | r = si_irq_init(rdev); |
3809 | if (r) { |
4134 | if (r) { |
3810 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
4135 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
Line 3832... | Line 4157... | ||
3832 | CP_RB2_RPTR, CP_RB2_WPTR, |
4157 | CP_RB2_RPTR, CP_RB2_WPTR, |
3833 | 0, 0xfffff, RADEON_CP_PACKET2); |
4158 | 0, 0xfffff, RADEON_CP_PACKET2); |
3834 | if (r) |
4159 | if (r) |
3835 | return r; |
4160 | return r; |
Line -... | Line 4161... | ||
- | 4161 | ||
- | 4162 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
|
- | 4163 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
|
- | 4164 | DMA_RB_RPTR + DMA0_REGISTER_OFFSET, |
|
- | 4165 | DMA_RB_WPTR + DMA0_REGISTER_OFFSET, |
|
- | 4166 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); |
|
- | 4167 | if (r) |
|
- | 4168 | return r; |
|
- | 4169 | ||
- | 4170 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
|
- | 4171 | r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, |
|
- | 4172 | DMA_RB_RPTR + DMA1_REGISTER_OFFSET, |
|
- | 4173 | DMA_RB_WPTR + DMA1_REGISTER_OFFSET, |
|
- | 4174 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); |
|
- | 4175 | if (r) |
|
- | 4176 | return r; |
|
3836 | 4177 | ||
3837 | r = si_cp_load_microcode(rdev); |
4178 | r = si_cp_load_microcode(rdev); |
3838 | if (r) |
4179 | if (r) |
3839 | return r; |
4180 | return r; |
3840 | r = si_cp_resume(rdev); |
4181 | r = si_cp_resume(rdev); |
3841 | if (r) |
4182 | if (r) |
Line -... | Line 4183... | ||
- | 4183 | return r; |
|
- | 4184 | ||
- | 4185 | r = cayman_dma_resume(rdev); |
|
- | 4186 | if (r) |
|
3842 | return r; |
4187 | return r; |
3843 | 4188 | ||
3844 | r = radeon_ib_pool_init(rdev); |
4189 | r = radeon_ib_pool_init(rdev); |
3845 | if (r) { |
4190 | if (r) { |
3846 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
4191 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
Line 3930... | Line 4275... | ||
3930 | 4275 | ||
3931 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; |
4276 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; |
3932 | ring->ring_obj = NULL; |
4277 | ring->ring_obj = NULL; |
Line -... | Line 4278... | ||
- | 4278 | r600_ring_init(rdev, ring, 1024 * 1024); |
|
- | 4279 | ||
- | 4280 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
|
- | 4281 | ring->ring_obj = NULL; |
|
- | 4282 | r600_ring_init(rdev, ring, 64 * 1024); |
|
- | 4283 | ||
- | 4284 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
|
- | 4285 | ring->ring_obj = NULL; |
|
3933 | r600_ring_init(rdev, ring, 1024 * 1024); |
4286 | r600_ring_init(rdev, ring, 64 * 1024); |
3934 | 4287 | ||
Line 3935... | Line 4288... | ||
3935 | rdev->ih.ring_obj = NULL; |
4288 | rdev->ih.ring_obj = NULL; |
3936 | r600_ih_ring_init(rdev, 64 * 1024); |
4289 | r600_ih_ring_init(rdev, 64 * 1024); |