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Line 120... | Line 120... | ||
120 | #define GRBM_STATUS 0x8010 |
120 | #define GRBM_STATUS 0x8010 |
121 | #define CMDFIFO_AVAIL_MASK 0x0000000F |
121 | #define CMDFIFO_AVAIL_MASK 0x0000000F |
122 | #define GUI_ACTIVE (1<<31) |
122 | #define GUI_ACTIVE (1<<31) |
123 | #define GRBM_STATUS2 0x8014 |
123 | #define GRBM_STATUS2 0x8014 |
Line -... | Line 124... | ||
- | 124 | ||
- | 125 | #define CG_MULT_THERMAL_STATUS 0x740 |
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- | 126 | #define ASIC_T(x) ((x) << 16) |
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- | 127 | #define ASIC_T_MASK 0x3FF0000 |
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- | 128 | #define ASIC_T_SHIFT 16 |
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124 | 129 | ||
125 | #define HDP_HOST_PATH_CNTL 0x2C00 |
130 | #define HDP_HOST_PATH_CNTL 0x2C00 |
126 | #define HDP_NONSURFACE_BASE 0x2C04 |
131 | #define HDP_NONSURFACE_BASE 0x2C04 |
127 | #define HDP_NONSURFACE_INFO 0x2C08 |
132 | #define HDP_NONSURFACE_INFO 0x2C08 |
128 | #define HDP_NONSURFACE_SIZE 0x2C0C |
133 | #define HDP_NONSURFACE_SIZE 0x2C0C |
129 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
134 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
- | 135 | #define HDP_TILING_CONFIG 0x2F3C |
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Line 130... | Line 136... | ||
130 | #define HDP_TILING_CONFIG 0x2F3C |
136 | #define HDP_DEBUG1 0x2F34 |
131 | 137 | ||
132 | #define MC_SHARED_CHMAP 0x2004 |
138 | #define MC_SHARED_CHMAP 0x2004 |
- | 139 | #define NOOFCHAN_SHIFT 12 |
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Line 133... | Line 140... | ||
133 | #define NOOFCHAN_SHIFT 12 |
140 | #define NOOFCHAN_MASK 0x00003000 |
134 | #define NOOFCHAN_MASK 0x00003000 |
141 | #define MC_SHARED_CHREMAP 0x2008 |
135 | 142 | ||
136 | #define MC_ARB_RAMCFG 0x2760 |
143 | #define MC_ARB_RAMCFG 0x2760 |
Line 295... | Line 302... | ||
295 | #define SYNC_ALIGNER (1 << 26) |
302 | #define SYNC_ALIGNER (1 << 26) |
296 | #define BILINEAR_PRECISION_6_BIT (0 << 31) |
303 | #define BILINEAR_PRECISION_6_BIT (0 << 31) |
297 | #define BILINEAR_PRECISION_8_BIT (1 << 31) |
304 | #define BILINEAR_PRECISION_8_BIT (1 << 31) |
Line 298... | Line 305... | ||
298 | 305 | ||
- | 306 | #define TCP_CNTL 0x9610 |
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Line 299... | Line 307... | ||
299 | #define TCP_CNTL 0x9610 |
307 | #define TCP_CHAN_STEER 0x9614 |
300 | 308 | ||
301 | #define VGT_CACHE_INVALIDATION 0x88C4 |
309 | #define VGT_CACHE_INVALIDATION 0x88C4 |
302 | #define CACHE_INVALIDATION(x) ((x)<<0) |
310 | #define CACHE_INVALIDATION(x) ((x)<<0) |
Line 343... | Line 351... | ||
343 | 351 | ||
Line 344... | Line 352... | ||
344 | #define WAIT_UNTIL 0x8040 |
352 | #define WAIT_UNTIL 0x8040 |
Line -... | Line 353... | ||
- | 353 | ||
- | 354 | #define SRBM_STATUS 0x0E50 |
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- | 355 | ||
- | 356 | #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
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- | 357 | #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 |
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- | 358 | #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 |
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- | 359 | #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 |
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- | 360 | #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c |
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- | 361 | #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c |
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- | 362 | ||
- | 363 | /* PCIE link stuff */ |
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- | 364 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
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- | 365 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
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- | 366 | # define LC_LINK_WIDTH_SHIFT 0 |
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- | 367 | # define LC_LINK_WIDTH_MASK 0x7 |
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- | 368 | # define LC_LINK_WIDTH_X0 0 |
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- | 369 | # define LC_LINK_WIDTH_X1 1 |
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- | 370 | # define LC_LINK_WIDTH_X2 2 |
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- | 371 | # define LC_LINK_WIDTH_X4 3 |
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- | 372 | # define LC_LINK_WIDTH_X8 4 |
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- | 373 | # define LC_LINK_WIDTH_X16 6 |
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- | 374 | # define LC_LINK_WIDTH_RD_SHIFT 4 |
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- | 375 | # define LC_LINK_WIDTH_RD_MASK 0x70 |
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- | 376 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
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- | 377 | # define LC_RECONFIG_NOW (1 << 8) |
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- | 378 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
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- | 379 | # define LC_RENEGOTIATE_EN (1 << 10) |
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- | 380 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
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- | 381 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
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- | 382 | # define LC_UPCONFIGURE_DIS (1 << 13) |
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- | 383 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
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- | 384 | # define LC_GEN2_EN_STRAP (1 << 0) |
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- | 385 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
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- | 386 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
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- | 387 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
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- | 388 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
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- | 389 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
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- | 390 | # define LC_CURRENT_DATA_RATE (1 << 11) |
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- | 391 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
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- | 392 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
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- | 393 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
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- | 394 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
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- | 395 | #define MM_CFGREGS_CNTL 0x544c |
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- | 396 | # define MM_WR_TO_CFG_EN (1 << 3) |
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- | 397 | #define LINK_CNTL2 0x88 /* F0 */ |
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345 | 398 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |