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Rev 5271 | Rev 6104 | ||
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Line 28... | Line 28... | ||
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include "radeon.h" |
31 | #include "radeon.h" |
32 | #include "radeon_asic.h" |
32 | #include "radeon_asic.h" |
- | 33 | #include "radeon_audio.h" |
|
33 | #include |
34 | #include |
34 | #include "rv770d.h" |
35 | #include "rv770d.h" |
35 | #include "atom.h" |
36 | #include "atom.h" |
36 | #include "avivod.h" |
37 | #include "avivod.h" |
Line 61... | Line 62... | ||
61 | /* keep the Bypass mode, put PLL to sleep */ |
62 | /* keep the Bypass mode, put PLL to sleep */ |
62 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
63 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
63 | return 0; |
64 | return 0; |
64 | } |
65 | } |
Line 65... | Line 66... | ||
65 | 66 | ||
66 | // r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, |
67 | r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, |
67 | // 43663, 0x03FFFFFE, 1, 30, ~0, |
68 | 43663, 0x03FFFFFE, 1, 30, ~0, |
68 | // &fb_div, &vclk_div, &dclk_div); |
69 | &fb_div, &vclk_div, &dclk_div); |
69 | // if (r) |
70 | if (r) |
Line 70... | Line 71... | ||
70 | return r; |
71 | return r; |
71 | 72 | ||
72 | fb_div |= 1; |
73 | fb_div |= 1; |
Line 81... | Line 82... | ||
81 | 82 | ||
82 | /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ |
83 | /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ |
83 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); |
84 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); |
Line 84... | Line 85... | ||
84 | WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); |
85 | WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); |
85 | 86 | ||
86 | // r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
87 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
Line 87... | Line 88... | ||
87 | // if (r) |
88 | if (r) |
88 | return r; |
89 | return r; |
Line 112... | Line 113... | ||
112 | 113 | ||
113 | /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ |
114 | /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ |
114 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); |
115 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); |
Line 115... | Line 116... | ||
115 | WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); |
116 | WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); |
116 | 117 | ||
117 | // r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
118 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
Line 118... | Line 119... | ||
118 | // if (r) |
119 | if (r) |
119 | return r; |
120 | return r; |
120 | 121 | ||
Line 1118... | Line 1119... | ||
1118 | WREG32(CP_ME_RAM_WADDR, 0); |
1119 | WREG32(CP_ME_RAM_WADDR, 0); |
1119 | WREG32(CP_ME_RAM_RADDR, 0); |
1120 | WREG32(CP_ME_RAM_RADDR, 0); |
1120 | return 0; |
1121 | return 0; |
1121 | } |
1122 | } |
Line -... | Line 1123... | ||
- | 1123 | ||
- | 1124 | void r700_cp_fini(struct radeon_device *rdev) |
|
- | 1125 | { |
|
- | 1126 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
|
- | 1127 | r700_cp_stop(rdev); |
|
- | 1128 | radeon_ring_fini(rdev, ring); |
|
- | 1129 | radeon_scratch_free(rdev, ring->rptr_save_reg); |
|
- | 1130 | } |
|
1122 | 1131 | ||
1123 | void rv770_set_clk_bypass_mode(struct radeon_device *rdev) |
1132 | void rv770_set_clk_bypass_mode(struct radeon_device *rdev) |
1124 | { |
1133 | { |
Line 1125... | Line 1134... | ||
1125 | u32 tmp, i; |
1134 | u32 tmp, i; |
Line 1712... | Line 1721... | ||
1712 | if (r) { |
1721 | if (r) { |
1713 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
1722 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
1714 | return r; |
1723 | return r; |
1715 | } |
1724 | } |
Line 1716... | Line 1725... | ||
1716 | 1725 | ||
1717 | // r = rv770_uvd_resume(rdev); |
1726 | r = uvd_v2_2_resume(rdev); |
1718 | // if (!r) { |
1727 | if (!r) { |
1719 | // r = radeon_fence_driver_start_ring(rdev, |
1728 | r = radeon_fence_driver_start_ring(rdev, |
1720 | // R600_RING_TYPE_UVD_INDEX); |
1729 | R600_RING_TYPE_UVD_INDEX); |
1721 | // if (r) |
1730 | if (r) |
1722 | // dev_err(rdev->dev, "UVD fences init error (%d).\n", r); |
1731 | dev_err(rdev->dev, "UVD fences init error (%d).\n", r); |
Line 1723... | Line 1732... | ||
1723 | // } |
1732 | } |
1724 | 1733 | ||
Line 1725... | Line 1734... | ||
1725 | // if (r) |
1734 | if (r) |
1726 | // rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
1735 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
1727 | 1736 | ||
1728 | /* Enable IRQ */ |
1737 | /* Enable IRQ */ |
Line 1733... | Line 1742... | ||
1733 | } |
1742 | } |
Line 1734... | Line 1743... | ||
1734 | 1743 | ||
1735 | r = r600_irq_init(rdev); |
1744 | r = r600_irq_init(rdev); |
1736 | if (r) { |
1745 | if (r) { |
1737 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
1746 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
1738 | // radeon_irq_kms_fini(rdev); |
1747 | radeon_irq_kms_fini(rdev); |
1739 | return r; |
1748 | return r; |
1740 | } |
1749 | } |
Line 1741... | Line 1750... | ||
1741 | r600_irq_set(rdev); |
1750 | r600_irq_set(rdev); |
Line 1761... | Line 1770... | ||
1761 | 1770 | ||
1762 | r = r600_dma_resume(rdev); |
1771 | r = r600_dma_resume(rdev); |
1763 | if (r) |
1772 | if (r) |
Line 1764... | Line 1773... | ||
1764 | return r; |
1773 | return r; |
1765 | 1774 | ||
1766 | // ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
1775 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
1767 | // if (ring->ring_size) { |
- | |
1768 | // r = radeon_ring_init(rdev, ring, ring->ring_size, |
- | |
1769 | // R600_WB_UVD_RPTR_OFFSET, |
1776 | if (ring->ring_size) { |
1770 | // UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, |
1777 | r = radeon_ring_init(rdev, ring, ring->ring_size, 0, |
1771 | // 0, 0xfffff, RADEON_CP_PACKET2); |
1778 | RADEON_CP_PACKET2); |
1772 | // if (!r) |
1779 | if (!r) |
1773 | // r = r600_uvd_init(rdev); |
1780 | r = uvd_v1_0_init(rdev); |
1774 | 1781 | ||
1775 | // if (r) |
1782 | if (r) |
Line 1776... | Line 1783... | ||
1776 | // DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
1783 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
1777 | // } |
1784 | } |
1778 | 1785 | ||
1779 | r = radeon_ib_pool_init(rdev); |
1786 | r = radeon_ib_pool_init(rdev); |
1780 | if (r) { |
1787 | if (r) { |
Line 1781... | Line -... | ||
1781 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
- | |
1782 | return r; |
- | |
1783 | } |
- | |
1784 | - | ||
1785 | r = r600_audio_init(rdev); |
- | |
Line 1786... | Line 1788... | ||
1786 | if (r) { |
1788 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
1787 | DRM_ERROR("radeon: audio init failed\n"); |
1789 | return r; |
Line -... | Line 1790... | ||
- | 1790 | } |
|
- | 1791 | ||
- | 1792 | ||
Line -... | Line 1793... | ||
- | 1793 | return 0; |
|
- | 1794 | } |
|
- | 1795 | ||
- | 1796 | int rv770_resume(struct radeon_device *rdev) |
|
- | 1797 | { |
|
- | 1798 | int r; |
|
Line -... | Line 1799... | ||
- | 1799 | ||
- | 1800 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
|
Line -... | Line 1801... | ||
- | 1801 | * posting will perform necessary task to bring back GPU into good |
|
- | 1802 | * shape. |
|
- | 1803 | */ |
|
- | 1804 | /* post card */ |
|
- | 1805 | atom_asic_init(rdev->mode_info.atom_context); |
|
- | 1806 | ||
- | 1807 | /* init golden registers */ |
|
- | 1808 | rv770_init_golden_registers(rdev); |
|
- | 1809 | ||
- | 1810 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
|
- | 1811 | radeon_pm_resume(rdev); |
|
- | 1812 | ||
- | 1813 | rdev->accel_working = true; |
|
- | 1814 | r = rv770_startup(rdev); |
|
Line 1788... | Line 1815... | ||
1788 | return r; |
1815 | if (r) { |
1789 | } |
1816 | DRM_ERROR("r600 startup failed on resume\n"); |
Line 1870... | Line 1897... | ||
1870 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
1897 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
Line 1871... | Line 1898... | ||
1871 | 1898 | ||
1872 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
1899 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
Line 1873... | Line 1900... | ||
1873 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
1900 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
1874 | 1901 | ||
1875 | // r = radeon_uvd_init(rdev); |
1902 | r = radeon_uvd_init(rdev); |
1876 | // if (!r) { |
1903 | if (!r) { |
1877 | // rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; |
1904 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; |
1878 | // r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], |
1905 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], |
Line 1879... | Line 1906... | ||
1879 | // 4096); |
1906 | 4096); |
1880 | // } |
1907 | } |
Line 1881... | Line 1908... | ||
1881 | 1908 | ||
Line 1888... | Line 1915... | ||
1888 | 1915 | ||
1889 | rdev->accel_working = true; |
1916 | rdev->accel_working = true; |
1890 | r = rv770_startup(rdev); |
1917 | r = rv770_startup(rdev); |
1891 | if (r) { |
1918 | if (r) { |
- | 1919 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
|
- | 1920 | r700_cp_fini(rdev); |
|
- | 1921 | r600_dma_fini(rdev); |
|
- | 1922 | r600_irq_fini(rdev); |
|
- | 1923 | radeon_wb_fini(rdev); |
|
- | 1924 | radeon_ib_pool_fini(rdev); |
|
1892 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1925 | radeon_irq_kms_fini(rdev); |
1893 | rv770_pcie_gart_fini(rdev); |
1926 | rv770_pcie_gart_fini(rdev); |
1894 | rdev->accel_working = false; |
1927 | rdev->accel_working = false; |
Line 1895... | Line 1928... | ||
1895 | } |
1928 | } |
1896 | 1929 | ||
Line -... | Line 1930... | ||
- | 1930 | return 0; |
|
- | 1931 | } |
|
- | 1932 | ||
- | 1933 | void rv770_fini(struct radeon_device *rdev) |
|
- | 1934 | { |
|
- | 1935 | radeon_pm_fini(rdev); |
|
- | 1936 | r700_cp_fini(rdev); |
|
- | 1937 | r600_dma_fini(rdev); |
|
- | 1938 | r600_irq_fini(rdev); |
|
- | 1939 | radeon_wb_fini(rdev); |
|
- | 1940 | radeon_ib_pool_fini(rdev); |
|
- | 1941 | radeon_irq_kms_fini(rdev); |
|
- | 1942 | uvd_v1_0_fini(rdev); |
|
- | 1943 | radeon_uvd_fini(rdev); |
|
- | 1944 | rv770_pcie_gart_fini(rdev); |
|
- | 1945 | r600_vram_scratch_fini(rdev); |
|
- | 1946 | radeon_gem_fini(rdev); |
|
- | 1947 | radeon_fence_driver_fini(rdev); |
|
- | 1948 | radeon_agp_fini(rdev); |
|
- | 1949 | radeon_bo_fini(rdev); |
|
- | 1950 | radeon_atombios_fini(rdev); |
|
- | 1951 | kfree(rdev->bios); |
|
1897 | return 0; |
1952 | rdev->bios = NULL; |
1898 | } |
1953 | } |
1899 | 1954 | ||
1900 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) |
1955 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) |