WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rv770.c

 #include
 #include
 #include
 #include "radeon.h"
 #include "radeon_asic.h"
+#include "radeon_audio.h"
 #include
 #include "rv770d.h"
 #include "atom.h"
 #include "avivod.h"
 		/* keep the Bypass mode, put PLL to sleep */
 		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
 		return 0;
+	}
-//   r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
+	r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
-//                     43663, 0x03FFFFFE, 1, 30, ~0,
+, 0x03FFFFFE, 1, 30, ~0,
-//                     &fb_div, &vclk_div, &dclk_div);
+					  &fb_div, &vclk_div, &dclk_div);
-//   if (r)
+	if (r)
 		return r;
 	fb_div |= 1;
 	/* assert BYPASS EN and FB_DIV[0] <- ??? why? */
 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
 	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
-//   r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
+	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
-//   if (r)
+	if (r)
 		return r;
 	/* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 	WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
-//   r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
+	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
-//   if (r)
+	if (r)
 		return r;
 	WREG32(CP_ME_RAM_WADDR, 0);
 	WREG32(CP_ME_RAM_RADDR, 0);
 	return 0;
+}
+void r700_cp_fini(struct radeon_device *rdev)
+{
+	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
+	r700_cp_stop(rdev);
+	radeon_ring_fini(rdev, ring);
+	radeon_scratch_free(rdev, ring->rptr_save_reg);
+}
 void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
+{
 	u32 tmp, i;
 	if (r) {
 		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
 		return r;
+	}
-//   r = rv770_uvd_resume(rdev);
+	r = uvd_v2_2_resume(rdev);
-//   if (!r) {
+	if (!r) {
-//       r = radeon_fence_driver_start_ring(rdev,
+		r = radeon_fence_driver_start_ring(rdev,
-//                          R600_RING_TYPE_UVD_INDEX);
+						   R600_RING_TYPE_UVD_INDEX);
-//       if (r)
+		if (r)
-//           dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
+			dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
-//   }
+	}
-//   if (r)
+	if (r)
-//       rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
+		rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
 	/* Enable IRQ */
+	}
 	r = r600_irq_init(rdev);
 	if (r) {
 		DRM_ERROR("radeon: IH init failed (%d).\n", r);
-//		radeon_irq_kms_fini(rdev);
+		radeon_irq_kms_fini(rdev);
 		return r;
+	}
 	r600_irq_set(rdev);
 	r = r600_dma_resume(rdev);
 	if (r)
 		return r;
-//   ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
+	ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
-//   if (ring->ring_size) {
-//       r = radeon_ring_init(rdev, ring, ring->ring_size,
-//                    R600_WB_UVD_RPTR_OFFSET,
+	if (ring->ring_size) {
-//                    UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
+		r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
-//                    0, 0xfffff, RADEON_CP_PACKET2);
+				     RADEON_CP_PACKET2);
-//       if (!r)
+		if (!r)
-//           r = r600_uvd_init(rdev);
+			r = uvd_v1_0_init(rdev);
-//       if (r)
+		if (r)
-//           DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
+			DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
 //   }
 	r = radeon_ib_pool_init(rdev);
 	if (r) {
-		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
-		return r;
-	}
-	r = r600_audio_init(rdev);
-	if (r) {
+		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
-		DRM_ERROR("radeon: audio init failed\n");
+		return r;
+	}
+	return 0;
+}
+int rv770_resume(struct radeon_device *rdev)
+{
+	int r;
+	/* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
+	 * posting will perform necessary task to bring back GPU into good
+	 * shape.
+	 */
+	/* post card */
+	atom_asic_init(rdev->mode_info.atom_context);
+	/* init golden registers */
+	rv770_init_golden_registers(rdev);
+	if (rdev->pm.pm_method == PM_METHOD_DPM)
+		radeon_pm_resume(rdev);
+	rdev->accel_working = true;
+	r = rv770_startup(rdev);
-		return r;
+	if (r) {
 		DRM_ERROR("r600 startup failed on resume\n");
 	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
 	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
-//   r = radeon_uvd_init(rdev);
+	r = radeon_uvd_init(rdev);
-//   if (!r) {
+	if (!r) {
-//       rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
+		rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
-//       r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
+		r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
-//                  4096);
+);
 //   }
 	rdev->accel_working = true;
 	r = rv770_startup(rdev);
 	if (r) {
+		dev_err(rdev->dev, "disabling GPU acceleration\n");
+		r700_cp_fini(rdev);
+		r600_dma_fini(rdev);
+		r600_irq_fini(rdev);
+		radeon_wb_fini(rdev);
+		radeon_ib_pool_fini(rdev);
-		dev_err(rdev->dev, "disabling GPU acceleration\n");
+		radeon_irq_kms_fini(rdev);
 		rv770_pcie_gart_fini(rdev);
-        rdev->accel_working = false;
+		rdev->accel_working = false;
+	}
+	return 0;
+}
+void rv770_fini(struct radeon_device *rdev)
+{
+	radeon_pm_fini(rdev);
+	r700_cp_fini(rdev);
+	r600_dma_fini(rdev);
+	r600_irq_fini(rdev);
+	radeon_wb_fini(rdev);
+	radeon_ib_pool_fini(rdev);
+	radeon_irq_kms_fini(rdev);
+	uvd_v1_0_fini(rdev);
+	radeon_uvd_fini(rdev);
+	rv770_pcie_gart_fini(rdev);
+	r600_vram_scratch_fini(rdev);
+	radeon_gem_fini(rdev);
+	radeon_fence_driver_fini(rdev);
+	radeon_agp_fini(rdev);
+	radeon_bo_fini(rdev);
+	radeon_atombios_fini(rdev);
+	kfree(rdev->bios);
-	return 0;
+	rdev->bios = NULL;
+}
 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rv770.c – Rev 5271 → 6104