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Rev 3764 | Rev 5078 | ||
---|---|---|---|
Line 742... | Line 742... | ||
742 | radeon_program_register_sequence(rdev, |
742 | radeon_program_register_sequence(rdev, |
743 | r7xx_golden_dyn_gpr_registers, |
743 | r7xx_golden_dyn_gpr_registers, |
744 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
744 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
745 | radeon_program_register_sequence(rdev, |
745 | radeon_program_register_sequence(rdev, |
746 | rv730_golden_registers, |
746 | rv730_golden_registers, |
747 | (const u32)ARRAY_SIZE(rv770_golden_registers)); |
747 | (const u32)ARRAY_SIZE(rv730_golden_registers)); |
748 | radeon_program_register_sequence(rdev, |
748 | radeon_program_register_sequence(rdev, |
749 | rv730_mgcg_init, |
749 | rv730_mgcg_init, |
750 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); |
750 | (const u32)ARRAY_SIZE(rv730_mgcg_init)); |
751 | break; |
751 | break; |
752 | case CHIP_RV710: |
752 | case CHIP_RV710: |
753 | radeon_program_register_sequence(rdev, |
753 | radeon_program_register_sequence(rdev, |
754 | r7xx_golden_registers, |
754 | r7xx_golden_registers, |
755 | (const u32)ARRAY_SIZE(r7xx_golden_registers)); |
755 | (const u32)ARRAY_SIZE(r7xx_golden_registers)); |
756 | radeon_program_register_sequence(rdev, |
756 | radeon_program_register_sequence(rdev, |
757 | r7xx_golden_dyn_gpr_registers, |
757 | r7xx_golden_dyn_gpr_registers, |
758 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
758 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
759 | radeon_program_register_sequence(rdev, |
759 | radeon_program_register_sequence(rdev, |
760 | rv710_golden_registers, |
760 | rv710_golden_registers, |
761 | (const u32)ARRAY_SIZE(rv770_golden_registers)); |
761 | (const u32)ARRAY_SIZE(rv710_golden_registers)); |
762 | radeon_program_register_sequence(rdev, |
762 | radeon_program_register_sequence(rdev, |
763 | rv710_mgcg_init, |
763 | rv710_mgcg_init, |
764 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); |
764 | (const u32)ARRAY_SIZE(rv710_mgcg_init)); |
765 | break; |
765 | break; |
766 | case CHIP_RV740: |
766 | case CHIP_RV740: |
767 | radeon_program_register_sequence(rdev, |
767 | radeon_program_register_sequence(rdev, |
768 | rv740_golden_registers, |
768 | rv740_golden_registers, |
769 | (const u32)ARRAY_SIZE(rv770_golden_registers)); |
769 | (const u32)ARRAY_SIZE(rv740_golden_registers)); |
770 | radeon_program_register_sequence(rdev, |
770 | radeon_program_register_sequence(rdev, |
771 | rv740_mgcg_init, |
771 | rv740_mgcg_init, |
772 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); |
772 | (const u32)ARRAY_SIZE(rv740_mgcg_init)); |
773 | break; |
773 | break; |
774 | default: |
774 | default: |
775 | break; |
775 | break; |
776 | } |
776 | } |
777 | } |
777 | } |
Line 799... | Line 799... | ||
799 | return reference_clock / 4; |
799 | return reference_clock / 4; |
Line 800... | Line 800... | ||
800 | 800 | ||
801 | return reference_clock; |
801 | return reference_clock; |
Line 802... | Line 802... | ||
802 | } |
802 | } |
803 | 803 | ||
804 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
804 | void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
805 | { |
805 | { |
806 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
806 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
Line 833... | Line 833... | ||
833 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
833 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
Line 834... | Line 834... | ||
834 | 834 | ||
835 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
835 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
836 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
836 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
- | 837 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
|
- | 838 | } |
|
- | 839 | ||
- | 840 | bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id) |
|
- | 841 | { |
|
Line 837... | Line 842... | ||
837 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
842 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
838 | 843 | ||
- | 844 | /* Return current update_pending status: */ |
|
839 | /* Return current update_pending status: */ |
845 | return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & |
Line 840... | Line 846... | ||
840 | return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; |
846 | AVIVO_D1GRPH_SURFACE_UPDATE_PENDING); |
841 | } |
847 | } |
842 | 848 | ||
Line 892... | Line 898... | ||
892 | return -EINVAL; |
898 | return -EINVAL; |
893 | } |
899 | } |
894 | r = radeon_gart_table_vram_pin(rdev); |
900 | r = radeon_gart_table_vram_pin(rdev); |
895 | if (r) |
901 | if (r) |
896 | return r; |
902 | return r; |
897 | radeon_gart_restore(rdev); |
- | |
898 | /* Setup L2 cache */ |
903 | /* Setup L2 cache */ |
899 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
904 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
900 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
905 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
901 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
906 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
902 | WREG32(VM_L2_CNTL2, 0); |
907 | WREG32(VM_L2_CNTL2, 0); |
Line 1069... | Line 1074... | ||
1069 | /* |
1074 | /* |
1070 | * CP. |
1075 | * CP. |
1071 | */ |
1076 | */ |
1072 | void r700_cp_stop(struct radeon_device *rdev) |
1077 | void r700_cp_stop(struct radeon_device *rdev) |
1073 | { |
1078 | { |
- | 1079 | if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) |
|
1074 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
1080 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
1075 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
1081 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
1076 | WREG32(SCRATCH_UMSK, 0); |
1082 | WREG32(SCRATCH_UMSK, 0); |
1077 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
1083 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
1078 | } |
1084 | } |
Line 1113... | Line 1119... | ||
1113 | WREG32(CP_ME_RAM_WADDR, 0); |
1119 | WREG32(CP_ME_RAM_WADDR, 0); |
1114 | WREG32(CP_ME_RAM_RADDR, 0); |
1120 | WREG32(CP_ME_RAM_RADDR, 0); |
1115 | return 0; |
1121 | return 0; |
1116 | } |
1122 | } |
Line -... | Line 1123... | ||
- | 1123 | ||
- | 1124 | void rv770_set_clk_bypass_mode(struct radeon_device *rdev) |
|
- | 1125 | { |
|
- | 1126 | u32 tmp, i; |
|
- | 1127 | ||
- | 1128 | if (rdev->flags & RADEON_IS_IGP) |
|
- | 1129 | return; |
|
- | 1130 | ||
- | 1131 | tmp = RREG32(CG_SPLL_FUNC_CNTL_2); |
|
- | 1132 | tmp &= SCLK_MUX_SEL_MASK; |
|
- | 1133 | tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE; |
|
- | 1134 | WREG32(CG_SPLL_FUNC_CNTL_2, tmp); |
|
- | 1135 | ||
- | 1136 | for (i = 0; i < rdev->usec_timeout; i++) { |
|
- | 1137 | if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS) |
|
- | 1138 | break; |
|
- | 1139 | udelay(1); |
|
- | 1140 | } |
|
- | 1141 | ||
- | 1142 | tmp &= ~SCLK_MUX_UPDATE; |
|
- | 1143 | WREG32(CG_SPLL_FUNC_CNTL_2, tmp); |
|
- | 1144 | ||
- | 1145 | tmp = RREG32(MPLL_CNTL_MODE); |
|
- | 1146 | if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) |
|
- | 1147 | tmp &= ~RV730_MPLL_MCLK_SEL; |
|
- | 1148 | else |
|
- | 1149 | tmp &= ~MPLL_MCLK_SEL; |
|
- | 1150 | WREG32(MPLL_CNTL_MODE, tmp); |
|
Line 1117... | Line 1151... | ||
1117 | 1151 | } |
|
1118 | 1152 | ||
1119 | /* |
1153 | /* |
1120 | * Core functions |
1154 | * Core functions |
Line 1133... | Line 1167... | ||
1133 | u32 sq_config; |
1167 | u32 sq_config; |
1134 | u32 sq_thread_resource_mgmt; |
1168 | u32 sq_thread_resource_mgmt; |
1135 | u32 hdp_host_path_cntl; |
1169 | u32 hdp_host_path_cntl; |
1136 | u32 sq_dyn_gpr_size_simd_ab_0; |
1170 | u32 sq_dyn_gpr_size_simd_ab_0; |
1137 | u32 gb_tiling_config = 0; |
1171 | u32 gb_tiling_config = 0; |
1138 | u32 cc_rb_backend_disable = 0; |
- | |
1139 | u32 cc_gc_shader_pipe_config = 0; |
1172 | u32 cc_gc_shader_pipe_config = 0; |
1140 | u32 mc_arb_ramcfg; |
1173 | u32 mc_arb_ramcfg; |
1141 | u32 db_debug4, tmp; |
1174 | u32 db_debug4, tmp; |
1142 | u32 inactive_pipes, shader_pipe_config; |
1175 | u32 inactive_pipes, shader_pipe_config; |
1143 | u32 disabled_rb_mask; |
1176 | u32 disabled_rb_mask; |
Line 1267... | Line 1300... | ||
1267 | WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); |
1300 | WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); |
1268 | } else { |
1301 | } else { |
1269 | WREG32(SPI_CONFIG_CNTL, 0); |
1302 | WREG32(SPI_CONFIG_CNTL, 0); |
1270 | } |
1303 | } |
Line 1271... | Line -... | ||
1271 | - | ||
1272 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
- | |
1273 | tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); |
- | |
1274 | if (tmp < rdev->config.rv770.max_backends) { |
- | |
1275 | rdev->config.rv770.max_backends = tmp; |
- | |
1276 | } |
- | |
1277 | 1304 | ||
1278 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
- | |
1279 | tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); |
1305 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
1280 | if (tmp < rdev->config.rv770.max_pipes) { |
- | |
1281 | rdev->config.rv770.max_pipes = tmp; |
- | |
1282 | } |
1306 | tmp = rdev->config.rv770.max_simds - |
1283 | tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); |
- | |
1284 | if (tmp < rdev->config.rv770.max_simds) { |
1307 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); |
1285 | rdev->config.rv770.max_simds = tmp; |
- | |
Line 1286... | Line 1308... | ||
1286 | } |
1308 | rdev->config.rv770.active_simds = tmp; |
1287 | 1309 | ||
1288 | switch (rdev->config.rv770.max_tile_pipes) { |
1310 | switch (rdev->config.rv770.max_tile_pipes) { |
1289 | case 1: |
1311 | case 1: |
Line 1301... | Line 1323... | ||
1301 | break; |
1323 | break; |
1302 | } |
1324 | } |
1303 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
1325 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
Line 1304... | Line 1326... | ||
1304 | 1326 | ||
- | 1327 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; |
|
- | 1328 | tmp = 0; |
|
- | 1329 | for (i = 0; i < rdev->config.rv770.max_backends; i++) |
|
- | 1330 | tmp |= (1 << i); |
|
- | 1331 | /* if all the backends are disabled, fix it up here */ |
|
- | 1332 | if ((disabled_rb_mask & tmp) == tmp) { |
|
- | 1333 | for (i = 0; i < rdev->config.rv770.max_backends; i++) |
|
- | 1334 | disabled_rb_mask &= ~(1 << i); |
|
1305 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; |
1335 | } |
1306 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
1336 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
1307 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, |
1337 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, |
1308 | R7XX_MAX_BACKENDS, disabled_rb_mask); |
1338 | R7XX_MAX_BACKENDS, disabled_rb_mask); |
1309 | gb_tiling_config |= tmp << 16; |
1339 | gb_tiling_config |= tmp << 16; |
Line 1641... | Line 1671... | ||
1641 | radeon_update_bandwidth_info(rdev); |
1671 | radeon_update_bandwidth_info(rdev); |
Line 1642... | Line 1672... | ||
1642 | 1672 | ||
1643 | return 0; |
1673 | return 0; |
Line 1644... | Line -... | ||
1644 | } |
- | |
1645 | - | ||
1646 | /** |
- | |
1647 | * rv770_copy_dma - copy pages using the DMA engine |
- | |
1648 | * |
- | |
1649 | * @rdev: radeon_device pointer |
- | |
1650 | * @src_offset: src GPU address |
- | |
1651 | * @dst_offset: dst GPU address |
- | |
1652 | * @num_gpu_pages: number of GPU pages to xfer |
- | |
1653 | * @fence: radeon fence object |
- | |
1654 | * |
- | |
1655 | * Copy GPU paging using the DMA engine (r7xx). |
- | |
1656 | * Used by the radeon ttm implementation to move pages if |
- | |
1657 | * registered as the asic copy callback. |
- | |
1658 | */ |
- | |
1659 | int rv770_copy_dma(struct radeon_device *rdev, |
- | |
1660 | uint64_t src_offset, uint64_t dst_offset, |
- | |
1661 | unsigned num_gpu_pages, |
- | |
1662 | struct radeon_fence **fence) |
- | |
1663 | { |
- | |
1664 | struct radeon_semaphore *sem = NULL; |
- | |
1665 | int ring_index = rdev->asic->copy.dma_ring_index; |
- | |
1666 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
- | |
1667 | u32 size_in_dw, cur_size_in_dw; |
- | |
1668 | int i, num_loops; |
- | |
1669 | int r = 0; |
- | |
1670 | - | ||
1671 | r = radeon_semaphore_create(rdev, &sem); |
- | |
1672 | if (r) { |
- | |
1673 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
- | |
1674 | return r; |
- | |
1675 | } |
- | |
1676 | - | ||
1677 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
- | |
1678 | num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF); |
- | |
1679 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8); |
- | |
1680 | if (r) { |
- | |
1681 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
- | |
1682 | radeon_semaphore_free(rdev, &sem, NULL); |
- | |
1683 | return r; |
- | |
1684 | } |
- | |
1685 | - | ||
1686 | if (radeon_fence_need_sync(*fence, ring->idx)) { |
- | |
1687 | radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, |
- | |
1688 | ring->idx); |
- | |
1689 | radeon_fence_note_sync(*fence, ring->idx); |
- | |
1690 | } else { |
- | |
1691 | radeon_semaphore_free(rdev, &sem, NULL); |
- | |
1692 | } |
- | |
1693 | - | ||
1694 | for (i = 0; i < num_loops; i++) { |
- | |
1695 | cur_size_in_dw = size_in_dw; |
- | |
1696 | if (cur_size_in_dw > 0xFFFF) |
- | |
1697 | cur_size_in_dw = 0xFFFF; |
- | |
1698 | size_in_dw -= cur_size_in_dw; |
- | |
1699 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); |
- | |
1700 | radeon_ring_write(ring, dst_offset & 0xfffffffc); |
- | |
1701 | radeon_ring_write(ring, src_offset & 0xfffffffc); |
- | |
1702 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); |
- | |
1703 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
- | |
1704 | src_offset += cur_size_in_dw * 4; |
- | |
1705 | dst_offset += cur_size_in_dw * 4; |
- | |
1706 | } |
- | |
1707 | - | ||
1708 | r = radeon_fence_emit(rdev, fence, ring->idx); |
- | |
1709 | if (r) { |
- | |
1710 | radeon_ring_unlock_undo(rdev, ring); |
- | |
1711 | return r; |
- | |
1712 | } |
- | |
1713 | - | ||
1714 | radeon_ring_unlock_commit(rdev, ring); |
- | |
1715 | radeon_semaphore_free(rdev, &sem, *fence); |
- | |
1716 | - | ||
1717 | return r; |
- | |
1718 | } |
1674 | } |
1719 | 1675 | ||
1720 | static int rv770_startup(struct radeon_device *rdev) |
1676 | static int rv770_startup(struct radeon_device *rdev) |
1721 | { |
1677 | { |
Line 1722... | Line 1678... | ||
1722 | struct radeon_ring *ring; |
1678 | struct radeon_ring *ring; |
1723 | int r; |
1679 | int r; |
Line 1724... | Line 1680... | ||
1724 | 1680 | ||
1725 | /* enable pcie gen2 link */ |
- | |
1726 | rv770_pcie_gen2_enable(rdev); |
- | |
1727 | - | ||
1728 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
- | |
1729 | r = r600_init_microcode(rdev); |
- | |
1730 | if (r) { |
- | |
1731 | DRM_ERROR("Failed to load firmware!\n"); |
- | |
1732 | return r; |
1681 | /* enable pcie gen2 link */ |
1733 | } |
1682 | rv770_pcie_gen2_enable(rdev); |
1734 | } |
1683 | |
Line 1735... | Line 1684... | ||
1735 | 1684 | /* scratch needs to be initialized before MC */ |
|
- | 1685 | r = r600_vram_scratch_init(rdev); |
|
1736 | r = r600_vram_scratch_init(rdev); |
1686 | if (r) |
1737 | if (r) |
1687 | return r; |
1738 | return r; |
1688 | |
1739 | 1689 | rv770_mc_program(rdev); |
|
1740 | rv770_mc_program(rdev); |
1690 | |
1741 | if (rdev->flags & RADEON_IS_AGP) { |
1691 | if (rdev->flags & RADEON_IS_AGP) { |
1742 | rv770_agp_enable(rdev); |
1692 | rv770_agp_enable(rdev); |
Line 1743... | Line 1693... | ||
1743 | } else { |
1693 | } else { |
1744 | r = rv770_pcie_gart_enable(rdev); |
- | |
1745 | if (r) |
- | |
1746 | return r; |
- | |
1747 | } |
- | |
1748 | - | ||
1749 | rv770_gpu_init(rdev); |
- | |
Line 1750... | Line 1694... | ||
1750 | r = r600_blit_init(rdev); |
1694 | r = rv770_pcie_gart_enable(rdev); |
1751 | if (r) { |
1695 | if (r) |
1752 | r600_blit_fini(rdev); |
1696 | return r; |
1753 | rdev->asic->copy.copy = NULL; |
1697 | } |
Line 1797... | Line 1741... | ||
1797 | } |
1741 | } |
1798 | r600_irq_set(rdev); |
1742 | r600_irq_set(rdev); |
Line 1799... | Line 1743... | ||
1799 | 1743 | ||
1800 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
1744 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
1801 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
- | |
1802 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
1745 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
1803 | 0, 0xfffff, RADEON_CP_PACKET2); |
1746 | RADEON_CP_PACKET2); |
1804 | if (r) |
1747 | if (r) |
Line 1805... | Line 1748... | ||
1805 | return r; |
1748 | return r; |
1806 | 1749 | ||
1807 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
- | |
1808 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
1750 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
1809 | DMA_RB_RPTR, DMA_RB_WPTR, |
1751 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
1810 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
1752 | DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
Line 1811... | Line 1753... | ||
1811 | if (r) |
1753 | if (r) |
1812 | return r; |
1754 | return r; |
Line 1839... | Line 1781... | ||
1839 | if (r) { |
1781 | if (r) { |
1840 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
1782 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
1841 | return r; |
1783 | return r; |
1842 | } |
1784 | } |
Line -... | Line 1785... | ||
- | 1785 | ||
- | 1786 | r = r600_audio_init(rdev); |
|
- | 1787 | if (r) { |
|
- | 1788 | DRM_ERROR("radeon: audio init failed\n"); |
|
- | 1789 | return r; |
|
Line 1843... | Line 1790... | ||
1843 | 1790 | } |
|
1844 | 1791 | ||
Line 1907... | Line 1854... | ||
1907 | /* Memory manager */ |
1854 | /* Memory manager */ |
1908 | r = radeon_bo_init(rdev); |
1855 | r = radeon_bo_init(rdev); |
1909 | if (r) |
1856 | if (r) |
1910 | return r; |
1857 | return r; |
Line -... | Line 1858... | ||
- | 1858 | ||
- | 1859 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
|
- | 1860 | r = r600_init_microcode(rdev); |
|
- | 1861 | if (r) { |
|
- | 1862 | DRM_ERROR("Failed to load firmware!\n"); |
|
- | 1863 | return r; |
|
- | 1864 | } |
|
- | 1865 | } |
|
- | 1866 | ||
- | 1867 | /* Initialize power management */ |
|
- | 1868 | radeon_pm_init(rdev); |
|
1911 | 1869 | ||
1912 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
1870 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
Line 1913... | Line 1871... | ||
1913 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
1871 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
1914 | 1872 |