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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include |
28 | #include |
29 | //#include |
29 | //#include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include "radeon.h" |
32 | #include "radeon.h" |
33 | #include "radeon_asic.h" |
33 | #include "radeon_asic.h" |
34 | #include |
34 | #include |
35 | #include "rv770d.h" |
35 | #include "rv770d.h" |
36 | #include "atom.h" |
36 | #include "atom.h" |
37 | #include "avivod.h" |
37 | #include "avivod.h" |
38 | 38 | ||
39 | #define R700_PFP_UCODE_SIZE 848 |
39 | #define R700_PFP_UCODE_SIZE 848 |
40 | #define R700_PM4_UCODE_SIZE 1360 |
40 | #define R700_PM4_UCODE_SIZE 1360 |
41 | 41 | ||
42 | static void rv770_gpu_init(struct radeon_device *rdev); |
42 | static void rv770_gpu_init(struct radeon_device *rdev); |
43 | void rv770_fini(struct radeon_device *rdev); |
43 | void rv770_fini(struct radeon_device *rdev); |
44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
- | 45 | int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
|
- | 46 | ||
- | 47 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) |
|
- | 48 | { |
|
- | 49 | unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; |
|
- | 50 | int r; |
|
- | 51 | ||
- | 52 | /* RV740 uses evergreen uvd clk programming */ |
|
- | 53 | if (rdev->family == CHIP_RV740) |
|
- | 54 | return evergreen_set_uvd_clocks(rdev, vclk, dclk); |
|
- | 55 | ||
- | 56 | /* bypass vclk and dclk with bclk */ |
|
- | 57 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
|
- | 58 | VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), |
|
- | 59 | ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); |
|
- | 60 | ||
- | 61 | if (!vclk || !dclk) { |
|
- | 62 | /* keep the Bypass mode, put PLL to sleep */ |
|
- | 63 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
|
- | 64 | return 0; |
|
- | 65 | } |
|
- | 66 | ||
- | 67 | // r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, |
|
- | 68 | // 43663, 0x03FFFFFE, 1, 30, ~0, |
|
- | 69 | // &fb_div, &vclk_div, &dclk_div); |
|
- | 70 | // if (r) |
|
- | 71 | return r; |
|
- | 72 | ||
- | 73 | fb_div |= 1; |
|
- | 74 | vclk_div -= 1; |
|
- | 75 | dclk_div -= 1; |
|
- | 76 | ||
- | 77 | /* set UPLL_FB_DIV to 0x50000 */ |
|
- | 78 | WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); |
|
- | 79 | ||
- | 80 | /* deassert UPLL_RESET and UPLL_SLEEP */ |
|
- | 81 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); |
|
- | 82 | ||
- | 83 | /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ |
|
- | 84 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); |
|
- | 85 | WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); |
|
- | 86 | ||
- | 87 | // r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
|
- | 88 | // if (r) |
|
- | 89 | return r; |
|
- | 90 | ||
- | 91 | /* assert PLL_RESET */ |
|
- | 92 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); |
|
- | 93 | ||
- | 94 | /* set the required FB_DIV, REF_DIV, Post divder values */ |
|
- | 95 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); |
|
- | 96 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
|
- | 97 | UPLL_SW_HILEN(vclk_div >> 1) | |
|
- | 98 | UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | |
|
- | 99 | UPLL_SW_HILEN2(dclk_div >> 1) | |
|
- | 100 | UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), |
|
- | 101 | ~UPLL_SW_MASK); |
|
- | 102 | ||
- | 103 | WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), |
|
- | 104 | ~UPLL_FB_DIV_MASK); |
|
- | 105 | ||
- | 106 | /* give the PLL some time to settle */ |
|
- | 107 | mdelay(15); |
|
- | 108 | ||
- | 109 | /* deassert PLL_RESET */ |
|
- | 110 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); |
|
- | 111 | ||
- | 112 | mdelay(15); |
|
- | 113 | ||
- | 114 | /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ |
|
- | 115 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); |
|
- | 116 | WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); |
|
- | 117 | ||
- | 118 | // r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
|
- | 119 | // if (r) |
|
- | 120 | return r; |
|
- | 121 | ||
- | 122 | /* switch VCLK and DCLK selection */ |
|
- | 123 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
|
- | 124 | VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), |
|
- | 125 | ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); |
|
- | 126 | ||
- | 127 | mdelay(100); |
|
- | 128 | ||
- | 129 | return 0; |
|
- | 130 | } |
|
- | 131 | ||
- | 132 | static const u32 r7xx_golden_registers[] = |
|
- | 133 | { |
|
- | 134 | 0x8d00, 0xffffffff, 0x0e0e0074, |
|
- | 135 | 0x8d04, 0xffffffff, 0x013a2b34, |
|
- | 136 | 0x9508, 0xffffffff, 0x00000002, |
|
- | 137 | 0x8b20, 0xffffffff, 0, |
|
- | 138 | 0x88c4, 0xffffffff, 0x000000c2, |
|
- | 139 | 0x28350, 0xffffffff, 0, |
|
- | 140 | 0x9058, 0xffffffff, 0x0fffc40f, |
|
- | 141 | 0x240c, 0xffffffff, 0x00000380, |
|
- | 142 | 0x733c, 0xffffffff, 0x00000002, |
|
- | 143 | 0x2650, 0x00040000, 0, |
|
- | 144 | 0x20bc, 0x00040000, 0, |
|
- | 145 | 0x7300, 0xffffffff, 0x001000f0 |
|
- | 146 | }; |
|
- | 147 | ||
- | 148 | static const u32 r7xx_golden_dyn_gpr_registers[] = |
|
- | 149 | { |
|
- | 150 | 0x8db0, 0xffffffff, 0x98989898, |
|
- | 151 | 0x8db4, 0xffffffff, 0x98989898, |
|
- | 152 | 0x8db8, 0xffffffff, 0x98989898, |
|
- | 153 | 0x8dbc, 0xffffffff, 0x98989898, |
|
- | 154 | 0x8dc0, 0xffffffff, 0x98989898, |
|
- | 155 | 0x8dc4, 0xffffffff, 0x98989898, |
|
- | 156 | 0x8dc8, 0xffffffff, 0x98989898, |
|
- | 157 | 0x8dcc, 0xffffffff, 0x98989898, |
|
- | 158 | 0x88c4, 0xffffffff, 0x00000082 |
|
- | 159 | }; |
|
- | 160 | ||
- | 161 | static const u32 rv770_golden_registers[] = |
|
- | 162 | { |
|
- | 163 | 0x562c, 0xffffffff, 0, |
|
- | 164 | 0x3f90, 0xffffffff, 0, |
|
- | 165 | 0x9148, 0xffffffff, 0, |
|
- | 166 | 0x3f94, 0xffffffff, 0, |
|
- | 167 | 0x914c, 0xffffffff, 0, |
|
- | 168 | 0x9698, 0x18000000, 0x18000000 |
|
- | 169 | }; |
|
- | 170 | ||
- | 171 | static const u32 rv770ce_golden_registers[] = |
|
- | 172 | { |
|
- | 173 | 0x562c, 0xffffffff, 0, |
|
- | 174 | 0x3f90, 0xffffffff, 0x00cc0000, |
|
- | 175 | 0x9148, 0xffffffff, 0x00cc0000, |
|
- | 176 | 0x3f94, 0xffffffff, 0x00cc0000, |
|
- | 177 | 0x914c, 0xffffffff, 0x00cc0000, |
|
- | 178 | 0x9b7c, 0xffffffff, 0x00fa0000, |
|
- | 179 | 0x3f8c, 0xffffffff, 0x00fa0000, |
|
- | 180 | 0x9698, 0x18000000, 0x18000000 |
|
- | 181 | }; |
|
- | 182 | ||
- | 183 | static const u32 rv770_mgcg_init[] = |
|
- | 184 | { |
|
- | 185 | 0x8bcc, 0xffffffff, 0x130300f9, |
|
- | 186 | 0x5448, 0xffffffff, 0x100, |
|
- | 187 | 0x55e4, 0xffffffff, 0x100, |
|
- | 188 | 0x160c, 0xffffffff, 0x100, |
|
- | 189 | 0x5644, 0xffffffff, 0x100, |
|
- | 190 | 0xc164, 0xffffffff, 0x100, |
|
- | 191 | 0x8a18, 0xffffffff, 0x100, |
|
- | 192 | 0x897c, 0xffffffff, 0x8000100, |
|
- | 193 | 0x8b28, 0xffffffff, 0x3c000100, |
|
- | 194 | 0x9144, 0xffffffff, 0x100, |
|
- | 195 | 0x9a1c, 0xffffffff, 0x10000, |
|
- | 196 | 0x9a50, 0xffffffff, 0x100, |
|
- | 197 | 0x9a1c, 0xffffffff, 0x10001, |
|
- | 198 | 0x9a50, 0xffffffff, 0x100, |
|
- | 199 | 0x9a1c, 0xffffffff, 0x10002, |
|
- | 200 | 0x9a50, 0xffffffff, 0x100, |
|
- | 201 | 0x9a1c, 0xffffffff, 0x10003, |
|
- | 202 | 0x9a50, 0xffffffff, 0x100, |
|
- | 203 | 0x9a1c, 0xffffffff, 0x0, |
|
- | 204 | 0x9870, 0xffffffff, 0x100, |
|
- | 205 | 0x8d58, 0xffffffff, 0x100, |
|
- | 206 | 0x9500, 0xffffffff, 0x0, |
|
- | 207 | 0x9510, 0xffffffff, 0x100, |
|
- | 208 | 0x9500, 0xffffffff, 0x1, |
|
- | 209 | 0x9510, 0xffffffff, 0x100, |
|
- | 210 | 0x9500, 0xffffffff, 0x2, |
|
- | 211 | 0x9510, 0xffffffff, 0x100, |
|
- | 212 | 0x9500, 0xffffffff, 0x3, |
|
- | 213 | 0x9510, 0xffffffff, 0x100, |
|
- | 214 | 0x9500, 0xffffffff, 0x4, |
|
- | 215 | 0x9510, 0xffffffff, 0x100, |
|
- | 216 | 0x9500, 0xffffffff, 0x5, |
|
- | 217 | 0x9510, 0xffffffff, 0x100, |
|
- | 218 | 0x9500, 0xffffffff, 0x6, |
|
- | 219 | 0x9510, 0xffffffff, 0x100, |
|
- | 220 | 0x9500, 0xffffffff, 0x7, |
|
- | 221 | 0x9510, 0xffffffff, 0x100, |
|
- | 222 | 0x9500, 0xffffffff, 0x8, |
|
- | 223 | 0x9510, 0xffffffff, 0x100, |
|
- | 224 | 0x9500, 0xffffffff, 0x9, |
|
- | 225 | 0x9510, 0xffffffff, 0x100, |
|
- | 226 | 0x9500, 0xffffffff, 0x8000, |
|
- | 227 | 0x9490, 0xffffffff, 0x0, |
|
- | 228 | 0x949c, 0xffffffff, 0x100, |
|
- | 229 | 0x9490, 0xffffffff, 0x1, |
|
- | 230 | 0x949c, 0xffffffff, 0x100, |
|
- | 231 | 0x9490, 0xffffffff, 0x2, |
|
- | 232 | 0x949c, 0xffffffff, 0x100, |
|
- | 233 | 0x9490, 0xffffffff, 0x3, |
|
- | 234 | 0x949c, 0xffffffff, 0x100, |
|
- | 235 | 0x9490, 0xffffffff, 0x4, |
|
- | 236 | 0x949c, 0xffffffff, 0x100, |
|
- | 237 | 0x9490, 0xffffffff, 0x5, |
|
- | 238 | 0x949c, 0xffffffff, 0x100, |
|
- | 239 | 0x9490, 0xffffffff, 0x6, |
|
- | 240 | 0x949c, 0xffffffff, 0x100, |
|
- | 241 | 0x9490, 0xffffffff, 0x7, |
|
- | 242 | 0x949c, 0xffffffff, 0x100, |
|
- | 243 | 0x9490, 0xffffffff, 0x8, |
|
- | 244 | 0x949c, 0xffffffff, 0x100, |
|
- | 245 | 0x9490, 0xffffffff, 0x9, |
|
- | 246 | 0x949c, 0xffffffff, 0x100, |
|
- | 247 | 0x9490, 0xffffffff, 0x8000, |
|
- | 248 | 0x9604, 0xffffffff, 0x0, |
|
- | 249 | 0x9654, 0xffffffff, 0x100, |
|
- | 250 | 0x9604, 0xffffffff, 0x1, |
|
- | 251 | 0x9654, 0xffffffff, 0x100, |
|
- | 252 | 0x9604, 0xffffffff, 0x2, |
|
- | 253 | 0x9654, 0xffffffff, 0x100, |
|
- | 254 | 0x9604, 0xffffffff, 0x3, |
|
- | 255 | 0x9654, 0xffffffff, 0x100, |
|
- | 256 | 0x9604, 0xffffffff, 0x4, |
|
- | 257 | 0x9654, 0xffffffff, 0x100, |
|
- | 258 | 0x9604, 0xffffffff, 0x5, |
|
- | 259 | 0x9654, 0xffffffff, 0x100, |
|
- | 260 | 0x9604, 0xffffffff, 0x6, |
|
- | 261 | 0x9654, 0xffffffff, 0x100, |
|
- | 262 | 0x9604, 0xffffffff, 0x7, |
|
- | 263 | 0x9654, 0xffffffff, 0x100, |
|
- | 264 | 0x9604, 0xffffffff, 0x8, |
|
- | 265 | 0x9654, 0xffffffff, 0x100, |
|
- | 266 | 0x9604, 0xffffffff, 0x9, |
|
- | 267 | 0x9654, 0xffffffff, 0x100, |
|
- | 268 | 0x9604, 0xffffffff, 0x80000000, |
|
- | 269 | 0x9030, 0xffffffff, 0x100, |
|
- | 270 | 0x9034, 0xffffffff, 0x100, |
|
- | 271 | 0x9038, 0xffffffff, 0x100, |
|
- | 272 | 0x903c, 0xffffffff, 0x100, |
|
- | 273 | 0x9040, 0xffffffff, 0x100, |
|
- | 274 | 0xa200, 0xffffffff, 0x100, |
|
- | 275 | 0xa204, 0xffffffff, 0x100, |
|
- | 276 | 0xa208, 0xffffffff, 0x100, |
|
- | 277 | 0xa20c, 0xffffffff, 0x100, |
|
- | 278 | 0x971c, 0xffffffff, 0x100, |
|
- | 279 | 0x915c, 0xffffffff, 0x00020001, |
|
- | 280 | 0x9160, 0xffffffff, 0x00040003, |
|
- | 281 | 0x916c, 0xffffffff, 0x00060005, |
|
- | 282 | 0x9170, 0xffffffff, 0x00080007, |
|
- | 283 | 0x9174, 0xffffffff, 0x000a0009, |
|
- | 284 | 0x9178, 0xffffffff, 0x000c000b, |
|
- | 285 | 0x917c, 0xffffffff, 0x000e000d, |
|
- | 286 | 0x9180, 0xffffffff, 0x0010000f, |
|
- | 287 | 0x918c, 0xffffffff, 0x00120011, |
|
- | 288 | 0x9190, 0xffffffff, 0x00140013, |
|
- | 289 | 0x9194, 0xffffffff, 0x00020001, |
|
- | 290 | 0x9198, 0xffffffff, 0x00040003, |
|
- | 291 | 0x919c, 0xffffffff, 0x00060005, |
|
- | 292 | 0x91a8, 0xffffffff, 0x00080007, |
|
- | 293 | 0x91ac, 0xffffffff, 0x000a0009, |
|
- | 294 | 0x91b0, 0xffffffff, 0x000c000b, |
|
- | 295 | 0x91b4, 0xffffffff, 0x000e000d, |
|
- | 296 | 0x91b8, 0xffffffff, 0x0010000f, |
|
- | 297 | 0x91c4, 0xffffffff, 0x00120011, |
|
- | 298 | 0x91c8, 0xffffffff, 0x00140013, |
|
- | 299 | 0x91cc, 0xffffffff, 0x00020001, |
|
- | 300 | 0x91d0, 0xffffffff, 0x00040003, |
|
- | 301 | 0x91d4, 0xffffffff, 0x00060005, |
|
- | 302 | 0x91e0, 0xffffffff, 0x00080007, |
|
- | 303 | 0x91e4, 0xffffffff, 0x000a0009, |
|
- | 304 | 0x91e8, 0xffffffff, 0x000c000b, |
|
- | 305 | 0x91ec, 0xffffffff, 0x00020001, |
|
- | 306 | 0x91f0, 0xffffffff, 0x00040003, |
|
- | 307 | 0x91f4, 0xffffffff, 0x00060005, |
|
- | 308 | 0x9200, 0xffffffff, 0x00080007, |
|
- | 309 | 0x9204, 0xffffffff, 0x000a0009, |
|
- | 310 | 0x9208, 0xffffffff, 0x000c000b, |
|
- | 311 | 0x920c, 0xffffffff, 0x000e000d, |
|
- | 312 | 0x9210, 0xffffffff, 0x0010000f, |
|
- | 313 | 0x921c, 0xffffffff, 0x00120011, |
|
- | 314 | 0x9220, 0xffffffff, 0x00140013, |
|
- | 315 | 0x9224, 0xffffffff, 0x00020001, |
|
- | 316 | 0x9228, 0xffffffff, 0x00040003, |
|
- | 317 | 0x922c, 0xffffffff, 0x00060005, |
|
- | 318 | 0x9238, 0xffffffff, 0x00080007, |
|
- | 319 | 0x923c, 0xffffffff, 0x000a0009, |
|
- | 320 | 0x9240, 0xffffffff, 0x000c000b, |
|
- | 321 | 0x9244, 0xffffffff, 0x000e000d, |
|
- | 322 | 0x9248, 0xffffffff, 0x0010000f, |
|
- | 323 | 0x9254, 0xffffffff, 0x00120011, |
|
- | 324 | 0x9258, 0xffffffff, 0x00140013, |
|
- | 325 | 0x925c, 0xffffffff, 0x00020001, |
|
- | 326 | 0x9260, 0xffffffff, 0x00040003, |
|
- | 327 | 0x9264, 0xffffffff, 0x00060005, |
|
- | 328 | 0x9270, 0xffffffff, 0x00080007, |
|
- | 329 | 0x9274, 0xffffffff, 0x000a0009, |
|
- | 330 | 0x9278, 0xffffffff, 0x000c000b, |
|
- | 331 | 0x927c, 0xffffffff, 0x000e000d, |
|
- | 332 | 0x9280, 0xffffffff, 0x0010000f, |
|
- | 333 | 0x928c, 0xffffffff, 0x00120011, |
|
- | 334 | 0x9290, 0xffffffff, 0x00140013, |
|
- | 335 | 0x9294, 0xffffffff, 0x00020001, |
|
- | 336 | 0x929c, 0xffffffff, 0x00040003, |
|
- | 337 | 0x92a0, 0xffffffff, 0x00060005, |
|
- | 338 | 0x92a4, 0xffffffff, 0x00080007 |
|
- | 339 | }; |
|
- | 340 | ||
- | 341 | static const u32 rv710_golden_registers[] = |
|
- | 342 | { |
|
- | 343 | 0x3f90, 0x00ff0000, 0x00fc0000, |
|
- | 344 | 0x9148, 0x00ff0000, 0x00fc0000, |
|
- | 345 | 0x3f94, 0x00ff0000, 0x00fc0000, |
|
- | 346 | 0x914c, 0x00ff0000, 0x00fc0000, |
|
- | 347 | 0xb4c, 0x00000020, 0x00000020, |
|
- | 348 | 0xa180, 0xffffffff, 0x00003f3f |
|
- | 349 | }; |
|
- | 350 | ||
- | 351 | static const u32 rv710_mgcg_init[] = |
|
- | 352 | { |
|
- | 353 | 0x8bcc, 0xffffffff, 0x13030040, |
|
- | 354 | 0x5448, 0xffffffff, 0x100, |
|
- | 355 | 0x55e4, 0xffffffff, 0x100, |
|
- | 356 | 0x160c, 0xffffffff, 0x100, |
|
- | 357 | 0x5644, 0xffffffff, 0x100, |
|
- | 358 | 0xc164, 0xffffffff, 0x100, |
|
- | 359 | 0x8a18, 0xffffffff, 0x100, |
|
- | 360 | 0x897c, 0xffffffff, 0x8000100, |
|
- | 361 | 0x8b28, 0xffffffff, 0x3c000100, |
|
- | 362 | 0x9144, 0xffffffff, 0x100, |
|
- | 363 | 0x9a1c, 0xffffffff, 0x10000, |
|
- | 364 | 0x9a50, 0xffffffff, 0x100, |
|
- | 365 | 0x9a1c, 0xffffffff, 0x0, |
|
- | 366 | 0x9870, 0xffffffff, 0x100, |
|
- | 367 | 0x8d58, 0xffffffff, 0x100, |
|
- | 368 | 0x9500, 0xffffffff, 0x0, |
|
- | 369 | 0x9510, 0xffffffff, 0x100, |
|
- | 370 | 0x9500, 0xffffffff, 0x1, |
|
- | 371 | 0x9510, 0xffffffff, 0x100, |
|
- | 372 | 0x9500, 0xffffffff, 0x8000, |
|
- | 373 | 0x9490, 0xffffffff, 0x0, |
|
- | 374 | 0x949c, 0xffffffff, 0x100, |
|
- | 375 | 0x9490, 0xffffffff, 0x1, |
|
- | 376 | 0x949c, 0xffffffff, 0x100, |
|
- | 377 | 0x9490, 0xffffffff, 0x8000, |
|
- | 378 | 0x9604, 0xffffffff, 0x0, |
|
- | 379 | 0x9654, 0xffffffff, 0x100, |
|
- | 380 | 0x9604, 0xffffffff, 0x1, |
|
- | 381 | 0x9654, 0xffffffff, 0x100, |
|
- | 382 | 0x9604, 0xffffffff, 0x80000000, |
|
- | 383 | 0x9030, 0xffffffff, 0x100, |
|
- | 384 | 0x9034, 0xffffffff, 0x100, |
|
- | 385 | 0x9038, 0xffffffff, 0x100, |
|
- | 386 | 0x903c, 0xffffffff, 0x100, |
|
- | 387 | 0x9040, 0xffffffff, 0x100, |
|
- | 388 | 0xa200, 0xffffffff, 0x100, |
|
- | 389 | 0xa204, 0xffffffff, 0x100, |
|
- | 390 | 0xa208, 0xffffffff, 0x100, |
|
- | 391 | 0xa20c, 0xffffffff, 0x100, |
|
- | 392 | 0x971c, 0xffffffff, 0x100, |
|
- | 393 | 0x915c, 0xffffffff, 0x00020001, |
|
- | 394 | 0x9174, 0xffffffff, 0x00000003, |
|
- | 395 | 0x9178, 0xffffffff, 0x00050001, |
|
- | 396 | 0x917c, 0xffffffff, 0x00030002, |
|
- | 397 | 0x918c, 0xffffffff, 0x00000004, |
|
- | 398 | 0x9190, 0xffffffff, 0x00070006, |
|
- | 399 | 0x9194, 0xffffffff, 0x00050001, |
|
- | 400 | 0x9198, 0xffffffff, 0x00030002, |
|
- | 401 | 0x91a8, 0xffffffff, 0x00000004, |
|
- | 402 | 0x91ac, 0xffffffff, 0x00070006, |
|
- | 403 | 0x91e8, 0xffffffff, 0x00000001, |
|
- | 404 | 0x9294, 0xffffffff, 0x00000001, |
|
- | 405 | 0x929c, 0xffffffff, 0x00000002, |
|
- | 406 | 0x92a0, 0xffffffff, 0x00040003, |
|
- | 407 | 0x9150, 0xffffffff, 0x4d940000 |
|
- | 408 | }; |
|
- | 409 | ||
- | 410 | static const u32 rv730_golden_registers[] = |
|
- | 411 | { |
|
- | 412 | 0x3f90, 0x00ff0000, 0x00f00000, |
|
- | 413 | 0x9148, 0x00ff0000, 0x00f00000, |
|
- | 414 | 0x3f94, 0x00ff0000, 0x00f00000, |
|
- | 415 | 0x914c, 0x00ff0000, 0x00f00000, |
|
- | 416 | 0x900c, 0xffffffff, 0x003b033f, |
|
- | 417 | 0xb4c, 0x00000020, 0x00000020, |
|
- | 418 | 0xa180, 0xffffffff, 0x00003f3f |
|
- | 419 | }; |
|
- | 420 | ||
- | 421 | static const u32 rv730_mgcg_init[] = |
|
- | 422 | { |
|
- | 423 | 0x8bcc, 0xffffffff, 0x130300f9, |
|
- | 424 | 0x5448, 0xffffffff, 0x100, |
|
- | 425 | 0x55e4, 0xffffffff, 0x100, |
|
- | 426 | 0x160c, 0xffffffff, 0x100, |
|
- | 427 | 0x5644, 0xffffffff, 0x100, |
|
- | 428 | 0xc164, 0xffffffff, 0x100, |
|
- | 429 | 0x8a18, 0xffffffff, 0x100, |
|
- | 430 | 0x897c, 0xffffffff, 0x8000100, |
|
- | 431 | 0x8b28, 0xffffffff, 0x3c000100, |
|
- | 432 | 0x9144, 0xffffffff, 0x100, |
|
- | 433 | 0x9a1c, 0xffffffff, 0x10000, |
|
- | 434 | 0x9a50, 0xffffffff, 0x100, |
|
- | 435 | 0x9a1c, 0xffffffff, 0x10001, |
|
- | 436 | 0x9a50, 0xffffffff, 0x100, |
|
- | 437 | 0x9a1c, 0xffffffff, 0x0, |
|
- | 438 | 0x9870, 0xffffffff, 0x100, |
|
- | 439 | 0x8d58, 0xffffffff, 0x100, |
|
- | 440 | 0x9500, 0xffffffff, 0x0, |
|
- | 441 | 0x9510, 0xffffffff, 0x100, |
|
- | 442 | 0x9500, 0xffffffff, 0x1, |
|
- | 443 | 0x9510, 0xffffffff, 0x100, |
|
- | 444 | 0x9500, 0xffffffff, 0x2, |
|
- | 445 | 0x9510, 0xffffffff, 0x100, |
|
- | 446 | 0x9500, 0xffffffff, 0x3, |
|
- | 447 | 0x9510, 0xffffffff, 0x100, |
|
- | 448 | 0x9500, 0xffffffff, 0x4, |
|
- | 449 | 0x9510, 0xffffffff, 0x100, |
|
- | 450 | 0x9500, 0xffffffff, 0x5, |
|
- | 451 | 0x9510, 0xffffffff, 0x100, |
|
- | 452 | 0x9500, 0xffffffff, 0x6, |
|
- | 453 | 0x9510, 0xffffffff, 0x100, |
|
- | 454 | 0x9500, 0xffffffff, 0x7, |
|
- | 455 | 0x9510, 0xffffffff, 0x100, |
|
- | 456 | 0x9500, 0xffffffff, 0x8000, |
|
- | 457 | 0x9490, 0xffffffff, 0x0, |
|
- | 458 | 0x949c, 0xffffffff, 0x100, |
|
- | 459 | 0x9490, 0xffffffff, 0x1, |
|
- | 460 | 0x949c, 0xffffffff, 0x100, |
|
- | 461 | 0x9490, 0xffffffff, 0x2, |
|
- | 462 | 0x949c, 0xffffffff, 0x100, |
|
- | 463 | 0x9490, 0xffffffff, 0x3, |
|
- | 464 | 0x949c, 0xffffffff, 0x100, |
|
- | 465 | 0x9490, 0xffffffff, 0x4, |
|
- | 466 | 0x949c, 0xffffffff, 0x100, |
|
- | 467 | 0x9490, 0xffffffff, 0x5, |
|
- | 468 | 0x949c, 0xffffffff, 0x100, |
|
- | 469 | 0x9490, 0xffffffff, 0x6, |
|
- | 470 | 0x949c, 0xffffffff, 0x100, |
|
- | 471 | 0x9490, 0xffffffff, 0x7, |
|
- | 472 | 0x949c, 0xffffffff, 0x100, |
|
- | 473 | 0x9490, 0xffffffff, 0x8000, |
|
- | 474 | 0x9604, 0xffffffff, 0x0, |
|
- | 475 | 0x9654, 0xffffffff, 0x100, |
|
- | 476 | 0x9604, 0xffffffff, 0x1, |
|
- | 477 | 0x9654, 0xffffffff, 0x100, |
|
- | 478 | 0x9604, 0xffffffff, 0x2, |
|
- | 479 | 0x9654, 0xffffffff, 0x100, |
|
- | 480 | 0x9604, 0xffffffff, 0x3, |
|
- | 481 | 0x9654, 0xffffffff, 0x100, |
|
- | 482 | 0x9604, 0xffffffff, 0x4, |
|
- | 483 | 0x9654, 0xffffffff, 0x100, |
|
- | 484 | 0x9604, 0xffffffff, 0x5, |
|
- | 485 | 0x9654, 0xffffffff, 0x100, |
|
- | 486 | 0x9604, 0xffffffff, 0x6, |
|
- | 487 | 0x9654, 0xffffffff, 0x100, |
|
- | 488 | 0x9604, 0xffffffff, 0x7, |
|
- | 489 | 0x9654, 0xffffffff, 0x100, |
|
- | 490 | 0x9604, 0xffffffff, 0x80000000, |
|
- | 491 | 0x9030, 0xffffffff, 0x100, |
|
- | 492 | 0x9034, 0xffffffff, 0x100, |
|
- | 493 | 0x9038, 0xffffffff, 0x100, |
|
- | 494 | 0x903c, 0xffffffff, 0x100, |
|
- | 495 | 0x9040, 0xffffffff, 0x100, |
|
- | 496 | 0xa200, 0xffffffff, 0x100, |
|
- | 497 | 0xa204, 0xffffffff, 0x100, |
|
- | 498 | 0xa208, 0xffffffff, 0x100, |
|
- | 499 | 0xa20c, 0xffffffff, 0x100, |
|
- | 500 | 0x971c, 0xffffffff, 0x100, |
|
- | 501 | 0x915c, 0xffffffff, 0x00020001, |
|
- | 502 | 0x916c, 0xffffffff, 0x00040003, |
|
- | 503 | 0x9170, 0xffffffff, 0x00000005, |
|
- | 504 | 0x9178, 0xffffffff, 0x00050001, |
|
- | 505 | 0x917c, 0xffffffff, 0x00030002, |
|
- | 506 | 0x918c, 0xffffffff, 0x00000004, |
|
- | 507 | 0x9190, 0xffffffff, 0x00070006, |
|
- | 508 | 0x9194, 0xffffffff, 0x00050001, |
|
- | 509 | 0x9198, 0xffffffff, 0x00030002, |
|
- | 510 | 0x91a8, 0xffffffff, 0x00000004, |
|
- | 511 | 0x91ac, 0xffffffff, 0x00070006, |
|
- | 512 | 0x91b0, 0xffffffff, 0x00050001, |
|
- | 513 | 0x91b4, 0xffffffff, 0x00030002, |
|
- | 514 | 0x91c4, 0xffffffff, 0x00000004, |
|
- | 515 | 0x91c8, 0xffffffff, 0x00070006, |
|
- | 516 | 0x91cc, 0xffffffff, 0x00050001, |
|
- | 517 | 0x91d0, 0xffffffff, 0x00030002, |
|
- | 518 | 0x91e0, 0xffffffff, 0x00000004, |
|
- | 519 | 0x91e4, 0xffffffff, 0x00070006, |
|
- | 520 | 0x91e8, 0xffffffff, 0x00000001, |
|
- | 521 | 0x91ec, 0xffffffff, 0x00050001, |
|
- | 522 | 0x91f0, 0xffffffff, 0x00030002, |
|
- | 523 | 0x9200, 0xffffffff, 0x00000004, |
|
- | 524 | 0x9204, 0xffffffff, 0x00070006, |
|
- | 525 | 0x9208, 0xffffffff, 0x00050001, |
|
- | 526 | 0x920c, 0xffffffff, 0x00030002, |
|
- | 527 | 0x921c, 0xffffffff, 0x00000004, |
|
- | 528 | 0x9220, 0xffffffff, 0x00070006, |
|
- | 529 | 0x9224, 0xffffffff, 0x00050001, |
|
- | 530 | 0x9228, 0xffffffff, 0x00030002, |
|
- | 531 | 0x9238, 0xffffffff, 0x00000004, |
|
- | 532 | 0x923c, 0xffffffff, 0x00070006, |
|
- | 533 | 0x9240, 0xffffffff, 0x00050001, |
|
- | 534 | 0x9244, 0xffffffff, 0x00030002, |
|
- | 535 | 0x9254, 0xffffffff, 0x00000004, |
|
- | 536 | 0x9258, 0xffffffff, 0x00070006, |
|
- | 537 | 0x9294, 0xffffffff, 0x00000001, |
|
- | 538 | 0x929c, 0xffffffff, 0x00000002, |
|
- | 539 | 0x92a0, 0xffffffff, 0x00040003, |
|
- | 540 | 0x92a4, 0xffffffff, 0x00000005 |
|
- | 541 | }; |
|
- | 542 | ||
- | 543 | static const u32 rv740_golden_registers[] = |
|
- | 544 | { |
|
- | 545 | 0x88c4, 0xffffffff, 0x00000082, |
|
- | 546 | 0x28a50, 0xfffffffc, 0x00000004, |
|
- | 547 | 0x2650, 0x00040000, 0, |
|
- | 548 | 0x20bc, 0x00040000, 0, |
|
- | 549 | 0x733c, 0xffffffff, 0x00000002, |
|
- | 550 | 0x7300, 0xffffffff, 0x001000f0, |
|
- | 551 | 0x3f90, 0x00ff0000, 0, |
|
- | 552 | 0x9148, 0x00ff0000, 0, |
|
- | 553 | 0x3f94, 0x00ff0000, 0, |
|
- | 554 | 0x914c, 0x00ff0000, 0, |
|
- | 555 | 0x240c, 0xffffffff, 0x00000380, |
|
- | 556 | 0x8a14, 0x00000007, 0x00000007, |
|
- | 557 | 0x8b24, 0xffffffff, 0x00ff0fff, |
|
- | 558 | 0x28a4c, 0xffffffff, 0x00004000, |
|
- | 559 | 0xa180, 0xffffffff, 0x00003f3f, |
|
- | 560 | 0x8d00, 0xffffffff, 0x0e0e003a, |
|
- | 561 | 0x8d04, 0xffffffff, 0x013a0e2a, |
|
- | 562 | 0x8c00, 0xffffffff, 0xe400000f, |
|
- | 563 | 0x8db0, 0xffffffff, 0x98989898, |
|
- | 564 | 0x8db4, 0xffffffff, 0x98989898, |
|
- | 565 | 0x8db8, 0xffffffff, 0x98989898, |
|
- | 566 | 0x8dbc, 0xffffffff, 0x98989898, |
|
- | 567 | 0x8dc0, 0xffffffff, 0x98989898, |
|
- | 568 | 0x8dc4, 0xffffffff, 0x98989898, |
|
- | 569 | 0x8dc8, 0xffffffff, 0x98989898, |
|
- | 570 | 0x8dcc, 0xffffffff, 0x98989898, |
|
- | 571 | 0x9058, 0xffffffff, 0x0fffc40f, |
|
- | 572 | 0x900c, 0xffffffff, 0x003b033f, |
|
- | 573 | 0x28350, 0xffffffff, 0, |
|
- | 574 | 0x8cf0, 0x1fffffff, 0x08e00420, |
|
- | 575 | 0x9508, 0xffffffff, 0x00000002, |
|
- | 576 | 0x88c4, 0xffffffff, 0x000000c2, |
|
- | 577 | 0x9698, 0x18000000, 0x18000000 |
|
- | 578 | }; |
|
- | 579 | ||
- | 580 | static const u32 rv740_mgcg_init[] = |
|
- | 581 | { |
|
- | 582 | 0x8bcc, 0xffffffff, 0x13030100, |
|
- | 583 | 0x5448, 0xffffffff, 0x100, |
|
- | 584 | 0x55e4, 0xffffffff, 0x100, |
|
- | 585 | 0x160c, 0xffffffff, 0x100, |
|
- | 586 | 0x5644, 0xffffffff, 0x100, |
|
- | 587 | 0xc164, 0xffffffff, 0x100, |
|
- | 588 | 0x8a18, 0xffffffff, 0x100, |
|
- | 589 | 0x897c, 0xffffffff, 0x100, |
|
- | 590 | 0x8b28, 0xffffffff, 0x100, |
|
- | 591 | 0x9144, 0xffffffff, 0x100, |
|
- | 592 | 0x9a1c, 0xffffffff, 0x10000, |
|
- | 593 | 0x9a50, 0xffffffff, 0x100, |
|
- | 594 | 0x9a1c, 0xffffffff, 0x10001, |
|
- | 595 | 0x9a50, 0xffffffff, 0x100, |
|
- | 596 | 0x9a1c, 0xffffffff, 0x10002, |
|
- | 597 | 0x9a50, 0xffffffff, 0x100, |
|
- | 598 | 0x9a1c, 0xffffffff, 0x10003, |
|
- | 599 | 0x9a50, 0xffffffff, 0x100, |
|
- | 600 | 0x9a1c, 0xffffffff, 0x0, |
|
- | 601 | 0x9870, 0xffffffff, 0x100, |
|
- | 602 | 0x8d58, 0xffffffff, 0x100, |
|
- | 603 | 0x9500, 0xffffffff, 0x0, |
|
- | 604 | 0x9510, 0xffffffff, 0x100, |
|
- | 605 | 0x9500, 0xffffffff, 0x1, |
|
- | 606 | 0x9510, 0xffffffff, 0x100, |
|
- | 607 | 0x9500, 0xffffffff, 0x2, |
|
- | 608 | 0x9510, 0xffffffff, 0x100, |
|
- | 609 | 0x9500, 0xffffffff, 0x3, |
|
- | 610 | 0x9510, 0xffffffff, 0x100, |
|
- | 611 | 0x9500, 0xffffffff, 0x4, |
|
- | 612 | 0x9510, 0xffffffff, 0x100, |
|
- | 613 | 0x9500, 0xffffffff, 0x5, |
|
- | 614 | 0x9510, 0xffffffff, 0x100, |
|
- | 615 | 0x9500, 0xffffffff, 0x6, |
|
- | 616 | 0x9510, 0xffffffff, 0x100, |
|
- | 617 | 0x9500, 0xffffffff, 0x7, |
|
- | 618 | 0x9510, 0xffffffff, 0x100, |
|
- | 619 | 0x9500, 0xffffffff, 0x8000, |
|
- | 620 | 0x9490, 0xffffffff, 0x0, |
|
- | 621 | 0x949c, 0xffffffff, 0x100, |
|
- | 622 | 0x9490, 0xffffffff, 0x1, |
|
- | 623 | 0x949c, 0xffffffff, 0x100, |
|
- | 624 | 0x9490, 0xffffffff, 0x2, |
|
- | 625 | 0x949c, 0xffffffff, 0x100, |
|
- | 626 | 0x9490, 0xffffffff, 0x3, |
|
- | 627 | 0x949c, 0xffffffff, 0x100, |
|
- | 628 | 0x9490, 0xffffffff, 0x4, |
|
- | 629 | 0x949c, 0xffffffff, 0x100, |
|
- | 630 | 0x9490, 0xffffffff, 0x5, |
|
- | 631 | 0x949c, 0xffffffff, 0x100, |
|
- | 632 | 0x9490, 0xffffffff, 0x6, |
|
- | 633 | 0x949c, 0xffffffff, 0x100, |
|
- | 634 | 0x9490, 0xffffffff, 0x7, |
|
- | 635 | 0x949c, 0xffffffff, 0x100, |
|
- | 636 | 0x9490, 0xffffffff, 0x8000, |
|
- | 637 | 0x9604, 0xffffffff, 0x0, |
|
- | 638 | 0x9654, 0xffffffff, 0x100, |
|
- | 639 | 0x9604, 0xffffffff, 0x1, |
|
- | 640 | 0x9654, 0xffffffff, 0x100, |
|
- | 641 | 0x9604, 0xffffffff, 0x2, |
|
- | 642 | 0x9654, 0xffffffff, 0x100, |
|
- | 643 | 0x9604, 0xffffffff, 0x3, |
|
- | 644 | 0x9654, 0xffffffff, 0x100, |
|
- | 645 | 0x9604, 0xffffffff, 0x4, |
|
- | 646 | 0x9654, 0xffffffff, 0x100, |
|
- | 647 | 0x9604, 0xffffffff, 0x5, |
|
- | 648 | 0x9654, 0xffffffff, 0x100, |
|
- | 649 | 0x9604, 0xffffffff, 0x6, |
|
- | 650 | 0x9654, 0xffffffff, 0x100, |
|
- | 651 | 0x9604, 0xffffffff, 0x7, |
|
- | 652 | 0x9654, 0xffffffff, 0x100, |
|
- | 653 | 0x9604, 0xffffffff, 0x80000000, |
|
- | 654 | 0x9030, 0xffffffff, 0x100, |
|
- | 655 | 0x9034, 0xffffffff, 0x100, |
|
- | 656 | 0x9038, 0xffffffff, 0x100, |
|
- | 657 | 0x903c, 0xffffffff, 0x100, |
|
- | 658 | 0x9040, 0xffffffff, 0x100, |
|
- | 659 | 0xa200, 0xffffffff, 0x100, |
|
- | 660 | 0xa204, 0xffffffff, 0x100, |
|
- | 661 | 0xa208, 0xffffffff, 0x100, |
|
- | 662 | 0xa20c, 0xffffffff, 0x100, |
|
- | 663 | 0x971c, 0xffffffff, 0x100, |
|
- | 664 | 0x915c, 0xffffffff, 0x00020001, |
|
- | 665 | 0x9160, 0xffffffff, 0x00040003, |
|
- | 666 | 0x916c, 0xffffffff, 0x00060005, |
|
- | 667 | 0x9170, 0xffffffff, 0x00080007, |
|
- | 668 | 0x9174, 0xffffffff, 0x000a0009, |
|
- | 669 | 0x9178, 0xffffffff, 0x000c000b, |
|
- | 670 | 0x917c, 0xffffffff, 0x000e000d, |
|
- | 671 | 0x9180, 0xffffffff, 0x0010000f, |
|
- | 672 | 0x918c, 0xffffffff, 0x00120011, |
|
- | 673 | 0x9190, 0xffffffff, 0x00140013, |
|
- | 674 | 0x9194, 0xffffffff, 0x00020001, |
|
- | 675 | 0x9198, 0xffffffff, 0x00040003, |
|
- | 676 | 0x919c, 0xffffffff, 0x00060005, |
|
- | 677 | 0x91a8, 0xffffffff, 0x00080007, |
|
- | 678 | 0x91ac, 0xffffffff, 0x000a0009, |
|
- | 679 | 0x91b0, 0xffffffff, 0x000c000b, |
|
- | 680 | 0x91b4, 0xffffffff, 0x000e000d, |
|
- | 681 | 0x91b8, 0xffffffff, 0x0010000f, |
|
- | 682 | 0x91c4, 0xffffffff, 0x00120011, |
|
- | 683 | 0x91c8, 0xffffffff, 0x00140013, |
|
- | 684 | 0x91cc, 0xffffffff, 0x00020001, |
|
- | 685 | 0x91d0, 0xffffffff, 0x00040003, |
|
- | 686 | 0x91d4, 0xffffffff, 0x00060005, |
|
- | 687 | 0x91e0, 0xffffffff, 0x00080007, |
|
- | 688 | 0x91e4, 0xffffffff, 0x000a0009, |
|
- | 689 | 0x91e8, 0xffffffff, 0x000c000b, |
|
- | 690 | 0x91ec, 0xffffffff, 0x00020001, |
|
- | 691 | 0x91f0, 0xffffffff, 0x00040003, |
|
- | 692 | 0x91f4, 0xffffffff, 0x00060005, |
|
- | 693 | 0x9200, 0xffffffff, 0x00080007, |
|
- | 694 | 0x9204, 0xffffffff, 0x000a0009, |
|
- | 695 | 0x9208, 0xffffffff, 0x000c000b, |
|
- | 696 | 0x920c, 0xffffffff, 0x000e000d, |
|
- | 697 | 0x9210, 0xffffffff, 0x0010000f, |
|
- | 698 | 0x921c, 0xffffffff, 0x00120011, |
|
- | 699 | 0x9220, 0xffffffff, 0x00140013, |
|
- | 700 | 0x9224, 0xffffffff, 0x00020001, |
|
- | 701 | 0x9228, 0xffffffff, 0x00040003, |
|
- | 702 | 0x922c, 0xffffffff, 0x00060005, |
|
- | 703 | 0x9238, 0xffffffff, 0x00080007, |
|
- | 704 | 0x923c, 0xffffffff, 0x000a0009, |
|
- | 705 | 0x9240, 0xffffffff, 0x000c000b, |
|
- | 706 | 0x9244, 0xffffffff, 0x000e000d, |
|
- | 707 | 0x9248, 0xffffffff, 0x0010000f, |
|
- | 708 | 0x9254, 0xffffffff, 0x00120011, |
|
- | 709 | 0x9258, 0xffffffff, 0x00140013, |
|
- | 710 | 0x9294, 0xffffffff, 0x00020001, |
|
- | 711 | 0x929c, 0xffffffff, 0x00040003, |
|
- | 712 | 0x92a0, 0xffffffff, 0x00060005, |
|
- | 713 | 0x92a4, 0xffffffff, 0x00080007 |
|
- | 714 | }; |
|
- | 715 | ||
- | 716 | static void rv770_init_golden_registers(struct radeon_device *rdev) |
|
- | 717 | { |
|
- | 718 | switch (rdev->family) { |
|
- | 719 | case CHIP_RV770: |
|
- | 720 | radeon_program_register_sequence(rdev, |
|
- | 721 | r7xx_golden_registers, |
|
- | 722 | (const u32)ARRAY_SIZE(r7xx_golden_registers)); |
|
- | 723 | radeon_program_register_sequence(rdev, |
|
- | 724 | r7xx_golden_dyn_gpr_registers, |
|
- | 725 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
|
- | 726 | if (rdev->pdev->device == 0x994e) |
|
- | 727 | radeon_program_register_sequence(rdev, |
|
- | 728 | rv770ce_golden_registers, |
|
- | 729 | (const u32)ARRAY_SIZE(rv770ce_golden_registers)); |
|
- | 730 | else |
|
- | 731 | radeon_program_register_sequence(rdev, |
|
- | 732 | rv770_golden_registers, |
|
- | 733 | (const u32)ARRAY_SIZE(rv770_golden_registers)); |
|
- | 734 | radeon_program_register_sequence(rdev, |
|
- | 735 | rv770_mgcg_init, |
|
- | 736 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); |
|
- | 737 | break; |
|
- | 738 | case CHIP_RV730: |
|
- | 739 | radeon_program_register_sequence(rdev, |
|
- | 740 | r7xx_golden_registers, |
|
- | 741 | (const u32)ARRAY_SIZE(r7xx_golden_registers)); |
|
- | 742 | radeon_program_register_sequence(rdev, |
|
- | 743 | r7xx_golden_dyn_gpr_registers, |
|
- | 744 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
|
- | 745 | radeon_program_register_sequence(rdev, |
|
- | 746 | rv730_golden_registers, |
|
- | 747 | (const u32)ARRAY_SIZE(rv770_golden_registers)); |
|
- | 748 | radeon_program_register_sequence(rdev, |
|
- | 749 | rv730_mgcg_init, |
|
- | 750 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); |
|
- | 751 | break; |
|
- | 752 | case CHIP_RV710: |
|
- | 753 | radeon_program_register_sequence(rdev, |
|
- | 754 | r7xx_golden_registers, |
|
- | 755 | (const u32)ARRAY_SIZE(r7xx_golden_registers)); |
|
- | 756 | radeon_program_register_sequence(rdev, |
|
- | 757 | r7xx_golden_dyn_gpr_registers, |
|
- | 758 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
|
- | 759 | radeon_program_register_sequence(rdev, |
|
- | 760 | rv710_golden_registers, |
|
- | 761 | (const u32)ARRAY_SIZE(rv770_golden_registers)); |
|
- | 762 | radeon_program_register_sequence(rdev, |
|
- | 763 | rv710_mgcg_init, |
|
- | 764 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); |
|
- | 765 | break; |
|
- | 766 | case CHIP_RV740: |
|
- | 767 | radeon_program_register_sequence(rdev, |
|
- | 768 | rv740_golden_registers, |
|
- | 769 | (const u32)ARRAY_SIZE(rv770_golden_registers)); |
|
- | 770 | radeon_program_register_sequence(rdev, |
|
- | 771 | rv740_mgcg_init, |
|
- | 772 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); |
|
- | 773 | break; |
|
- | 774 | default: |
|
- | 775 | break; |
|
- | 776 | } |
|
- | 777 | } |
|
- | 778 | ||
- | 779 | #define PCIE_BUS_CLK 10000 |
|
- | 780 | #define TCLK (PCIE_BUS_CLK / 10) |
|
- | 781 | ||
- | 782 | /** |
|
- | 783 | * rv770_get_xclk - get the xclk |
|
- | 784 | * |
|
- | 785 | * @rdev: radeon_device pointer |
|
- | 786 | * |
|
- | 787 | * Returns the reference clock used by the gfx engine |
|
- | 788 | * (r7xx-cayman). |
|
- | 789 | */ |
|
- | 790 | u32 rv770_get_xclk(struct radeon_device *rdev) |
|
- | 791 | { |
|
- | 792 | u32 reference_clock = rdev->clock.spll.reference_freq; |
|
- | 793 | u32 tmp = RREG32(CG_CLKPIN_CNTL); |
|
- | 794 | ||
- | 795 | if (tmp & MUX_TCLK_TO_XCLK) |
|
- | 796 | return TCLK; |
|
- | 797 | ||
- | 798 | if (tmp & XTALIN_DIVIDE) |
|
- | 799 | return reference_clock / 4; |
|
- | 800 | ||
- | 801 | return reference_clock; |
|
- | 802 | } |
|
- | 803 | ||
- | 804 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
|
- | 805 | { |
|
- | 806 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
|
- | 807 | u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); |
|
- | 808 | int i; |
|
- | 809 | ||
- | 810 | /* Lock the graphics update lock */ |
|
- | 811 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
|
- | 812 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
|
- | 813 | ||
- | 814 | /* update the scanout addresses */ |
|
- | 815 | if (radeon_crtc->crtc_id) { |
|
- | 816 | WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
|
- | 817 | WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
|
- | 818 | } else { |
|
- | 819 | WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
|
- | 820 | WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
|
- | 821 | } |
|
- | 822 | WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
|
- | 823 | (u32)crtc_base); |
|
- | 824 | WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
|
- | 825 | (u32)crtc_base); |
|
- | 826 | ||
- | 827 | /* Wait for update_pending to go high. */ |
|
- | 828 | for (i = 0; i < rdev->usec_timeout; i++) { |
|
- | 829 | if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) |
|
- | 830 | break; |
|
- | 831 | udelay(1); |
|
- | 832 | } |
|
- | 833 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
|
- | 834 | ||
- | 835 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
|
- | 836 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
|
- | 837 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
|
- | 838 | ||
- | 839 | /* Return current update_pending status: */ |
|
- | 840 | return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; |
|
- | 841 | } |
|
- | 842 | ||
- | 843 | /* get temperature in millidegrees */ |
|
- | 844 | int rv770_get_temp(struct radeon_device *rdev) |
|
- | 845 | { |
|
- | 846 | u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> |
|
- | 847 | ASIC_T_SHIFT; |
|
- | 848 | int actual_temp; |
|
- | 849 | ||
- | 850 | if (temp & 0x400) |
|
- | 851 | actual_temp = -256; |
|
- | 852 | else if (temp & 0x200) |
|
- | 853 | actual_temp = 255; |
|
- | 854 | else if (temp & 0x100) { |
|
- | 855 | actual_temp = temp & 0x1ff; |
|
- | 856 | actual_temp |= ~0x1ff; |
|
- | 857 | } else |
|
- | 858 | actual_temp = temp & 0xff; |
|
- | 859 | ||
- | 860 | return (actual_temp * 1000) / 2; |
|
- | 861 | } |
|
- | 862 | ||
- | 863 | void rv770_pm_misc(struct radeon_device *rdev) |
|
- | 864 | { |
|
- | 865 | int req_ps_idx = rdev->pm.requested_power_state_index; |
|
- | 866 | int req_cm_idx = rdev->pm.requested_clock_mode_index; |
|
- | 867 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; |
|
- | 868 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
|
- | 869 | ||
- | 870 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
|
- | 871 | /* 0xff01 is a flag rather then an actual voltage */ |
|
- | 872 | if (voltage->voltage == 0xff01) |
|
- | 873 | return; |
|
- | 874 | if (voltage->voltage != rdev->pm.current_vddc) { |
|
- | 875 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
|
- | 876 | rdev->pm.current_vddc = voltage->voltage; |
|
- | 877 | DRM_DEBUG("Setting: v: %d\n", voltage->voltage); |
|
- | 878 | } |
|
- | 879 | } |
|
45 | 880 | } |
|
46 | 881 | ||
47 | /* |
882 | /* |
48 | * GART |
883 | * GART |
49 | */ |
884 | */ |
50 | static int rv770_pcie_gart_enable(struct radeon_device *rdev) |
885 | static int rv770_pcie_gart_enable(struct radeon_device *rdev) |
51 | { |
886 | { |
52 | u32 tmp; |
887 | u32 tmp; |
53 | int r, i; |
888 | int r, i; |
54 | 889 | ||
55 | if (rdev->gart.robj == NULL) { |
890 | if (rdev->gart.robj == NULL) { |
56 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
891 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
57 | return -EINVAL; |
892 | return -EINVAL; |
58 | } |
893 | } |
59 | r = radeon_gart_table_vram_pin(rdev); |
894 | r = radeon_gart_table_vram_pin(rdev); |
60 | if (r) |
895 | if (r) |
61 | return r; |
896 | return r; |
62 | radeon_gart_restore(rdev); |
897 | radeon_gart_restore(rdev); |
63 | /* Setup L2 cache */ |
898 | /* Setup L2 cache */ |
64 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
899 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
65 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
900 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
66 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
901 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
67 | WREG32(VM_L2_CNTL2, 0); |
902 | WREG32(VM_L2_CNTL2, 0); |
68 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
903 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
69 | /* Setup TLB control */ |
904 | /* Setup TLB control */ |
70 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
905 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
71 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
906 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
72 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
907 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
73 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
908 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
74 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
909 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
75 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
910 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
76 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
911 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
77 | if (rdev->family == CHIP_RV740) |
912 | if (rdev->family == CHIP_RV740) |
78 | WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); |
913 | WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); |
79 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
914 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
80 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
915 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
81 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
916 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
82 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
917 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
83 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
918 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
84 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
919 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
85 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
920 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
86 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
921 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
87 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
922 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
88 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
923 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
89 | (u32)(rdev->dummy_page.addr >> 12)); |
924 | (u32)(rdev->dummy_page.addr >> 12)); |
90 | for (i = 1; i < 7; i++) |
925 | for (i = 1; i < 7; i++) |
91 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
926 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
92 | 927 | ||
93 | r600_pcie_gart_tlb_flush(rdev); |
928 | r600_pcie_gart_tlb_flush(rdev); |
94 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
929 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
95 | (unsigned)(rdev->mc.gtt_size >> 20), |
930 | (unsigned)(rdev->mc.gtt_size >> 20), |
96 | (unsigned long long)rdev->gart.table_addr); |
931 | (unsigned long long)rdev->gart.table_addr); |
97 | rdev->gart.ready = true; |
932 | rdev->gart.ready = true; |
98 | return 0; |
933 | return 0; |
99 | } |
934 | } |
100 | 935 | ||
101 | static void rv770_pcie_gart_disable(struct radeon_device *rdev) |
936 | static void rv770_pcie_gart_disable(struct radeon_device *rdev) |
102 | { |
937 | { |
103 | u32 tmp; |
938 | u32 tmp; |
104 | int i; |
939 | int i; |
105 | 940 | ||
106 | /* Disable all tables */ |
941 | /* Disable all tables */ |
107 | for (i = 0; i < 7; i++) |
942 | for (i = 0; i < 7; i++) |
108 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
943 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
109 | 944 | ||
110 | /* Setup L2 cache */ |
945 | /* Setup L2 cache */ |
111 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
946 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
112 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
947 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
113 | WREG32(VM_L2_CNTL2, 0); |
948 | WREG32(VM_L2_CNTL2, 0); |
114 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
949 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
115 | /* Setup TLB control */ |
950 | /* Setup TLB control */ |
116 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
951 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
117 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
952 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
118 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
953 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
119 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
954 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
120 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
955 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
121 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
956 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
122 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
957 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
123 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
958 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
124 | radeon_gart_table_vram_unpin(rdev); |
959 | radeon_gart_table_vram_unpin(rdev); |
125 | } |
960 | } |
126 | 961 | ||
127 | static void rv770_pcie_gart_fini(struct radeon_device *rdev) |
962 | static void rv770_pcie_gart_fini(struct radeon_device *rdev) |
128 | { |
963 | { |
129 | radeon_gart_fini(rdev); |
964 | radeon_gart_fini(rdev); |
130 | rv770_pcie_gart_disable(rdev); |
965 | rv770_pcie_gart_disable(rdev); |
131 | radeon_gart_table_vram_free(rdev); |
966 | radeon_gart_table_vram_free(rdev); |
132 | } |
967 | } |
133 | 968 | ||
134 | 969 | ||
135 | static void rv770_agp_enable(struct radeon_device *rdev) |
970 | static void rv770_agp_enable(struct radeon_device *rdev) |
136 | { |
971 | { |
137 | u32 tmp; |
972 | u32 tmp; |
138 | int i; |
973 | int i; |
139 | 974 | ||
140 | /* Setup L2 cache */ |
975 | /* Setup L2 cache */ |
141 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
976 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
142 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
977 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
143 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
978 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
144 | WREG32(VM_L2_CNTL2, 0); |
979 | WREG32(VM_L2_CNTL2, 0); |
145 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
980 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
146 | /* Setup TLB control */ |
981 | /* Setup TLB control */ |
147 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
982 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
148 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
983 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
149 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
984 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
150 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
985 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
151 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
986 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
152 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
987 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
153 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
988 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
154 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
989 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
155 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
990 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
156 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
991 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
157 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
992 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
158 | for (i = 0; i < 7; i++) |
993 | for (i = 0; i < 7; i++) |
159 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
994 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
160 | } |
995 | } |
161 | 996 | ||
162 | static void rv770_mc_program(struct radeon_device *rdev) |
997 | static void rv770_mc_program(struct radeon_device *rdev) |
163 | { |
998 | { |
164 | struct rv515_mc_save save; |
999 | struct rv515_mc_save save; |
165 | u32 tmp; |
1000 | u32 tmp; |
166 | int i, j; |
1001 | int i, j; |
167 | 1002 | ||
168 | /* Initialize HDP */ |
1003 | /* Initialize HDP */ |
169 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
1004 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
170 | WREG32((0x2c14 + j), 0x00000000); |
1005 | WREG32((0x2c14 + j), 0x00000000); |
171 | WREG32((0x2c18 + j), 0x00000000); |
1006 | WREG32((0x2c18 + j), 0x00000000); |
172 | WREG32((0x2c1c + j), 0x00000000); |
1007 | WREG32((0x2c1c + j), 0x00000000); |
173 | WREG32((0x2c20 + j), 0x00000000); |
1008 | WREG32((0x2c20 + j), 0x00000000); |
174 | WREG32((0x2c24 + j), 0x00000000); |
1009 | WREG32((0x2c24 + j), 0x00000000); |
175 | } |
1010 | } |
176 | /* r7xx hw bug. Read from HDP_DEBUG1 rather |
1011 | /* r7xx hw bug. Read from HDP_DEBUG1 rather |
177 | * than writing to HDP_REG_COHERENCY_FLUSH_CNTL |
1012 | * than writing to HDP_REG_COHERENCY_FLUSH_CNTL |
178 | */ |
1013 | */ |
179 | tmp = RREG32(HDP_DEBUG1); |
1014 | tmp = RREG32(HDP_DEBUG1); |
180 | 1015 | ||
181 | rv515_mc_stop(rdev, &save); |
1016 | rv515_mc_stop(rdev, &save); |
182 | if (r600_mc_wait_for_idle(rdev)) { |
1017 | if (r600_mc_wait_for_idle(rdev)) { |
183 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
1018 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
184 | } |
1019 | } |
185 | /* Lockout access through VGA aperture*/ |
1020 | /* Lockout access through VGA aperture*/ |
186 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
1021 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
187 | /* Update configuration */ |
1022 | /* Update configuration */ |
188 | if (rdev->flags & RADEON_IS_AGP) { |
1023 | if (rdev->flags & RADEON_IS_AGP) { |
189 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
1024 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
190 | /* VRAM before AGP */ |
1025 | /* VRAM before AGP */ |
191 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
1026 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
192 | rdev->mc.vram_start >> 12); |
1027 | rdev->mc.vram_start >> 12); |
193 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
1028 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
194 | rdev->mc.gtt_end >> 12); |
1029 | rdev->mc.gtt_end >> 12); |
195 | } else { |
1030 | } else { |
196 | /* VRAM after AGP */ |
1031 | /* VRAM after AGP */ |
197 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
1032 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
198 | rdev->mc.gtt_start >> 12); |
1033 | rdev->mc.gtt_start >> 12); |
199 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
1034 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
200 | rdev->mc.vram_end >> 12); |
1035 | rdev->mc.vram_end >> 12); |
201 | } |
1036 | } |
202 | } else { |
1037 | } else { |
203 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
1038 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
204 | rdev->mc.vram_start >> 12); |
1039 | rdev->mc.vram_start >> 12); |
205 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
1040 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
206 | rdev->mc.vram_end >> 12); |
1041 | rdev->mc.vram_end >> 12); |
207 | } |
1042 | } |
208 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
1043 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
209 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
1044 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
210 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
1045 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
211 | WREG32(MC_VM_FB_LOCATION, tmp); |
1046 | WREG32(MC_VM_FB_LOCATION, tmp); |
212 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
1047 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
213 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
1048 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
214 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
1049 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
215 | if (rdev->flags & RADEON_IS_AGP) { |
1050 | if (rdev->flags & RADEON_IS_AGP) { |
216 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
1051 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
217 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
1052 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
218 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
1053 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
219 | } else { |
1054 | } else { |
220 | WREG32(MC_VM_AGP_BASE, 0); |
1055 | WREG32(MC_VM_AGP_BASE, 0); |
221 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
1056 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
222 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
1057 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
223 | } |
1058 | } |
224 | if (r600_mc_wait_for_idle(rdev)) { |
1059 | if (r600_mc_wait_for_idle(rdev)) { |
225 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
1060 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
226 | } |
1061 | } |
227 | rv515_mc_resume(rdev, &save); |
1062 | rv515_mc_resume(rdev, &save); |
228 | /* we need to own VRAM, so turn off the VGA renderer here |
1063 | /* we need to own VRAM, so turn off the VGA renderer here |
229 | * to stop it overwriting our objects */ |
1064 | * to stop it overwriting our objects */ |
230 | rv515_vga_render_disable(rdev); |
1065 | rv515_vga_render_disable(rdev); |
231 | } |
1066 | } |
232 | 1067 | ||
233 | 1068 | ||
234 | /* |
1069 | /* |
235 | * CP. |
1070 | * CP. |
236 | */ |
1071 | */ |
237 | void r700_cp_stop(struct radeon_device *rdev) |
1072 | void r700_cp_stop(struct radeon_device *rdev) |
238 | { |
1073 | { |
239 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
1074 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
240 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
1075 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
241 | WREG32(SCRATCH_UMSK, 0); |
1076 | WREG32(SCRATCH_UMSK, 0); |
242 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
1077 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
243 | } |
1078 | } |
244 | 1079 | ||
245 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
1080 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
246 | { |
1081 | { |
247 | const __be32 *fw_data; |
1082 | const __be32 *fw_data; |
248 | int i; |
1083 | int i; |
249 | 1084 | ||
250 | if (!rdev->me_fw || !rdev->pfp_fw) |
1085 | if (!rdev->me_fw || !rdev->pfp_fw) |
251 | return -EINVAL; |
1086 | return -EINVAL; |
252 | 1087 | ||
253 | r700_cp_stop(rdev); |
1088 | r700_cp_stop(rdev); |
254 | WREG32(CP_RB_CNTL, |
1089 | WREG32(CP_RB_CNTL, |
255 | #ifdef __BIG_ENDIAN |
1090 | #ifdef __BIG_ENDIAN |
256 | BUF_SWAP_32BIT | |
1091 | BUF_SWAP_32BIT | |
257 | #endif |
1092 | #endif |
258 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
1093 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
259 | 1094 | ||
260 | /* Reset cp */ |
1095 | /* Reset cp */ |
261 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
1096 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
262 | RREG32(GRBM_SOFT_RESET); |
1097 | RREG32(GRBM_SOFT_RESET); |
263 | mdelay(15); |
1098 | mdelay(15); |
264 | WREG32(GRBM_SOFT_RESET, 0); |
1099 | WREG32(GRBM_SOFT_RESET, 0); |
265 | 1100 | ||
266 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
1101 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
267 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1102 | WREG32(CP_PFP_UCODE_ADDR, 0); |
268 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) |
1103 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) |
269 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
1104 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
270 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1105 | WREG32(CP_PFP_UCODE_ADDR, 0); |
271 | 1106 | ||
272 | fw_data = (const __be32 *)rdev->me_fw->data; |
1107 | fw_data = (const __be32 *)rdev->me_fw->data; |
273 | WREG32(CP_ME_RAM_WADDR, 0); |
1108 | WREG32(CP_ME_RAM_WADDR, 0); |
274 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) |
1109 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) |
275 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
1110 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
276 | 1111 | ||
277 | WREG32(CP_PFP_UCODE_ADDR, 0); |
1112 | WREG32(CP_PFP_UCODE_ADDR, 0); |
278 | WREG32(CP_ME_RAM_WADDR, 0); |
1113 | WREG32(CP_ME_RAM_WADDR, 0); |
279 | WREG32(CP_ME_RAM_RADDR, 0); |
1114 | WREG32(CP_ME_RAM_RADDR, 0); |
280 | return 0; |
1115 | return 0; |
281 | } |
1116 | } |
282 | 1117 | ||
283 | 1118 | ||
284 | /* |
1119 | /* |
285 | * Core functions |
1120 | * Core functions |
286 | */ |
1121 | */ |
287 | static void rv770_gpu_init(struct radeon_device *rdev) |
1122 | static void rv770_gpu_init(struct radeon_device *rdev) |
288 | { |
1123 | { |
289 | int i, j, num_qd_pipes; |
1124 | int i, j, num_qd_pipes; |
290 | u32 ta_aux_cntl; |
1125 | u32 ta_aux_cntl; |
291 | u32 sx_debug_1; |
1126 | u32 sx_debug_1; |
292 | u32 smx_dc_ctl0; |
1127 | u32 smx_dc_ctl0; |
293 | u32 db_debug3; |
1128 | u32 db_debug3; |
294 | u32 num_gs_verts_per_thread; |
1129 | u32 num_gs_verts_per_thread; |
295 | u32 vgt_gs_per_es; |
1130 | u32 vgt_gs_per_es; |
296 | u32 gs_prim_buffer_depth = 0; |
1131 | u32 gs_prim_buffer_depth = 0; |
297 | u32 sq_ms_fifo_sizes; |
1132 | u32 sq_ms_fifo_sizes; |
298 | u32 sq_config; |
1133 | u32 sq_config; |
299 | u32 sq_thread_resource_mgmt; |
1134 | u32 sq_thread_resource_mgmt; |
300 | u32 hdp_host_path_cntl; |
1135 | u32 hdp_host_path_cntl; |
301 | u32 sq_dyn_gpr_size_simd_ab_0; |
1136 | u32 sq_dyn_gpr_size_simd_ab_0; |
302 | u32 gb_tiling_config = 0; |
1137 | u32 gb_tiling_config = 0; |
303 | u32 cc_rb_backend_disable = 0; |
1138 | u32 cc_rb_backend_disable = 0; |
304 | u32 cc_gc_shader_pipe_config = 0; |
1139 | u32 cc_gc_shader_pipe_config = 0; |
305 | u32 mc_arb_ramcfg; |
1140 | u32 mc_arb_ramcfg; |
306 | u32 db_debug4, tmp; |
1141 | u32 db_debug4, tmp; |
307 | u32 inactive_pipes, shader_pipe_config; |
1142 | u32 inactive_pipes, shader_pipe_config; |
308 | u32 disabled_rb_mask; |
1143 | u32 disabled_rb_mask; |
309 | unsigned active_number; |
1144 | unsigned active_number; |
310 | 1145 | ||
311 | /* setup chip specs */ |
1146 | /* setup chip specs */ |
312 | rdev->config.rv770.tiling_group_size = 256; |
1147 | rdev->config.rv770.tiling_group_size = 256; |
313 | switch (rdev->family) { |
1148 | switch (rdev->family) { |
314 | case CHIP_RV770: |
1149 | case CHIP_RV770: |
315 | rdev->config.rv770.max_pipes = 4; |
1150 | rdev->config.rv770.max_pipes = 4; |
316 | rdev->config.rv770.max_tile_pipes = 8; |
1151 | rdev->config.rv770.max_tile_pipes = 8; |
317 | rdev->config.rv770.max_simds = 10; |
1152 | rdev->config.rv770.max_simds = 10; |
318 | rdev->config.rv770.max_backends = 4; |
1153 | rdev->config.rv770.max_backends = 4; |
319 | rdev->config.rv770.max_gprs = 256; |
1154 | rdev->config.rv770.max_gprs = 256; |
320 | rdev->config.rv770.max_threads = 248; |
1155 | rdev->config.rv770.max_threads = 248; |
321 | rdev->config.rv770.max_stack_entries = 512; |
1156 | rdev->config.rv770.max_stack_entries = 512; |
322 | rdev->config.rv770.max_hw_contexts = 8; |
1157 | rdev->config.rv770.max_hw_contexts = 8; |
323 | rdev->config.rv770.max_gs_threads = 16 * 2; |
1158 | rdev->config.rv770.max_gs_threads = 16 * 2; |
324 | rdev->config.rv770.sx_max_export_size = 128; |
1159 | rdev->config.rv770.sx_max_export_size = 128; |
325 | rdev->config.rv770.sx_max_export_pos_size = 16; |
1160 | rdev->config.rv770.sx_max_export_pos_size = 16; |
326 | rdev->config.rv770.sx_max_export_smx_size = 112; |
1161 | rdev->config.rv770.sx_max_export_smx_size = 112; |
327 | rdev->config.rv770.sq_num_cf_insts = 2; |
1162 | rdev->config.rv770.sq_num_cf_insts = 2; |
328 | 1163 | ||
329 | rdev->config.rv770.sx_num_of_sets = 7; |
1164 | rdev->config.rv770.sx_num_of_sets = 7; |
330 | rdev->config.rv770.sc_prim_fifo_size = 0xF9; |
1165 | rdev->config.rv770.sc_prim_fifo_size = 0xF9; |
331 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
1166 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
332 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
1167 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
333 | break; |
1168 | break; |
334 | case CHIP_RV730: |
1169 | case CHIP_RV730: |
335 | rdev->config.rv770.max_pipes = 2; |
1170 | rdev->config.rv770.max_pipes = 2; |
336 | rdev->config.rv770.max_tile_pipes = 4; |
1171 | rdev->config.rv770.max_tile_pipes = 4; |
337 | rdev->config.rv770.max_simds = 8; |
1172 | rdev->config.rv770.max_simds = 8; |
338 | rdev->config.rv770.max_backends = 2; |
1173 | rdev->config.rv770.max_backends = 2; |
339 | rdev->config.rv770.max_gprs = 128; |
1174 | rdev->config.rv770.max_gprs = 128; |
340 | rdev->config.rv770.max_threads = 248; |
1175 | rdev->config.rv770.max_threads = 248; |
341 | rdev->config.rv770.max_stack_entries = 256; |
1176 | rdev->config.rv770.max_stack_entries = 256; |
342 | rdev->config.rv770.max_hw_contexts = 8; |
1177 | rdev->config.rv770.max_hw_contexts = 8; |
343 | rdev->config.rv770.max_gs_threads = 16 * 2; |
1178 | rdev->config.rv770.max_gs_threads = 16 * 2; |
344 | rdev->config.rv770.sx_max_export_size = 256; |
1179 | rdev->config.rv770.sx_max_export_size = 256; |
345 | rdev->config.rv770.sx_max_export_pos_size = 32; |
1180 | rdev->config.rv770.sx_max_export_pos_size = 32; |
346 | rdev->config.rv770.sx_max_export_smx_size = 224; |
1181 | rdev->config.rv770.sx_max_export_smx_size = 224; |
347 | rdev->config.rv770.sq_num_cf_insts = 2; |
1182 | rdev->config.rv770.sq_num_cf_insts = 2; |
348 | 1183 | ||
349 | rdev->config.rv770.sx_num_of_sets = 7; |
1184 | rdev->config.rv770.sx_num_of_sets = 7; |
350 | rdev->config.rv770.sc_prim_fifo_size = 0xf9; |
1185 | rdev->config.rv770.sc_prim_fifo_size = 0xf9; |
351 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
1186 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
352 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
1187 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
353 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
1188 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
354 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
1189 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
355 | rdev->config.rv770.sx_max_export_smx_size += 16; |
1190 | rdev->config.rv770.sx_max_export_smx_size += 16; |
356 | } |
1191 | } |
357 | break; |
1192 | break; |
358 | case CHIP_RV710: |
1193 | case CHIP_RV710: |
359 | rdev->config.rv770.max_pipes = 2; |
1194 | rdev->config.rv770.max_pipes = 2; |
360 | rdev->config.rv770.max_tile_pipes = 2; |
1195 | rdev->config.rv770.max_tile_pipes = 2; |
361 | rdev->config.rv770.max_simds = 2; |
1196 | rdev->config.rv770.max_simds = 2; |
362 | rdev->config.rv770.max_backends = 1; |
1197 | rdev->config.rv770.max_backends = 1; |
363 | rdev->config.rv770.max_gprs = 256; |
1198 | rdev->config.rv770.max_gprs = 256; |
364 | rdev->config.rv770.max_threads = 192; |
1199 | rdev->config.rv770.max_threads = 192; |
365 | rdev->config.rv770.max_stack_entries = 256; |
1200 | rdev->config.rv770.max_stack_entries = 256; |
366 | rdev->config.rv770.max_hw_contexts = 4; |
1201 | rdev->config.rv770.max_hw_contexts = 4; |
367 | rdev->config.rv770.max_gs_threads = 8 * 2; |
1202 | rdev->config.rv770.max_gs_threads = 8 * 2; |
368 | rdev->config.rv770.sx_max_export_size = 128; |
1203 | rdev->config.rv770.sx_max_export_size = 128; |
369 | rdev->config.rv770.sx_max_export_pos_size = 16; |
1204 | rdev->config.rv770.sx_max_export_pos_size = 16; |
370 | rdev->config.rv770.sx_max_export_smx_size = 112; |
1205 | rdev->config.rv770.sx_max_export_smx_size = 112; |
371 | rdev->config.rv770.sq_num_cf_insts = 1; |
1206 | rdev->config.rv770.sq_num_cf_insts = 1; |
372 | 1207 | ||
373 | rdev->config.rv770.sx_num_of_sets = 7; |
1208 | rdev->config.rv770.sx_num_of_sets = 7; |
374 | rdev->config.rv770.sc_prim_fifo_size = 0x40; |
1209 | rdev->config.rv770.sc_prim_fifo_size = 0x40; |
375 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
1210 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
376 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
1211 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
377 | break; |
1212 | break; |
378 | case CHIP_RV740: |
1213 | case CHIP_RV740: |
379 | rdev->config.rv770.max_pipes = 4; |
1214 | rdev->config.rv770.max_pipes = 4; |
380 | rdev->config.rv770.max_tile_pipes = 4; |
1215 | rdev->config.rv770.max_tile_pipes = 4; |
381 | rdev->config.rv770.max_simds = 8; |
1216 | rdev->config.rv770.max_simds = 8; |
382 | rdev->config.rv770.max_backends = 4; |
1217 | rdev->config.rv770.max_backends = 4; |
383 | rdev->config.rv770.max_gprs = 256; |
1218 | rdev->config.rv770.max_gprs = 256; |
384 | rdev->config.rv770.max_threads = 248; |
1219 | rdev->config.rv770.max_threads = 248; |
385 | rdev->config.rv770.max_stack_entries = 512; |
1220 | rdev->config.rv770.max_stack_entries = 512; |
386 | rdev->config.rv770.max_hw_contexts = 8; |
1221 | rdev->config.rv770.max_hw_contexts = 8; |
387 | rdev->config.rv770.max_gs_threads = 16 * 2; |
1222 | rdev->config.rv770.max_gs_threads = 16 * 2; |
388 | rdev->config.rv770.sx_max_export_size = 256; |
1223 | rdev->config.rv770.sx_max_export_size = 256; |
389 | rdev->config.rv770.sx_max_export_pos_size = 32; |
1224 | rdev->config.rv770.sx_max_export_pos_size = 32; |
390 | rdev->config.rv770.sx_max_export_smx_size = 224; |
1225 | rdev->config.rv770.sx_max_export_smx_size = 224; |
391 | rdev->config.rv770.sq_num_cf_insts = 2; |
1226 | rdev->config.rv770.sq_num_cf_insts = 2; |
392 | 1227 | ||
393 | rdev->config.rv770.sx_num_of_sets = 7; |
1228 | rdev->config.rv770.sx_num_of_sets = 7; |
394 | rdev->config.rv770.sc_prim_fifo_size = 0x100; |
1229 | rdev->config.rv770.sc_prim_fifo_size = 0x100; |
395 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
1230 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
396 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
1231 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
397 | 1232 | ||
398 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
1233 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
399 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
1234 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
400 | rdev->config.rv770.sx_max_export_smx_size += 16; |
1235 | rdev->config.rv770.sx_max_export_smx_size += 16; |
401 | } |
1236 | } |
402 | break; |
1237 | break; |
403 | default: |
1238 | default: |
404 | break; |
1239 | break; |
405 | } |
1240 | } |
406 | 1241 | ||
407 | /* Initialize HDP */ |
1242 | /* Initialize HDP */ |
408 | j = 0; |
1243 | j = 0; |
409 | for (i = 0; i < 32; i++) { |
1244 | for (i = 0; i < 32; i++) { |
410 | WREG32((0x2c14 + j), 0x00000000); |
1245 | WREG32((0x2c14 + j), 0x00000000); |
411 | WREG32((0x2c18 + j), 0x00000000); |
1246 | WREG32((0x2c18 + j), 0x00000000); |
412 | WREG32((0x2c1c + j), 0x00000000); |
1247 | WREG32((0x2c1c + j), 0x00000000); |
413 | WREG32((0x2c20 + j), 0x00000000); |
1248 | WREG32((0x2c20 + j), 0x00000000); |
414 | WREG32((0x2c24 + j), 0x00000000); |
1249 | WREG32((0x2c24 + j), 0x00000000); |
415 | j += 0x18; |
1250 | j += 0x18; |
416 | } |
1251 | } |
417 | 1252 | ||
418 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
1253 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
419 | 1254 | ||
420 | /* setup tiling, simd, pipe config */ |
1255 | /* setup tiling, simd, pipe config */ |
421 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
1256 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
422 | 1257 | ||
423 | shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
1258 | shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
424 | inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; |
1259 | inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; |
425 | for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { |
1260 | for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { |
426 | if (!(inactive_pipes & tmp)) { |
1261 | if (!(inactive_pipes & tmp)) { |
427 | active_number++; |
1262 | active_number++; |
428 | } |
1263 | } |
429 | tmp <<= 1; |
1264 | tmp <<= 1; |
430 | } |
1265 | } |
431 | if (active_number == 1) { |
1266 | if (active_number == 1) { |
432 | WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); |
1267 | WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); |
433 | } else { |
1268 | } else { |
434 | WREG32(SPI_CONFIG_CNTL, 0); |
1269 | WREG32(SPI_CONFIG_CNTL, 0); |
435 | } |
1270 | } |
436 | 1271 | ||
437 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
1272 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
438 | tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); |
1273 | tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); |
439 | if (tmp < rdev->config.rv770.max_backends) { |
1274 | if (tmp < rdev->config.rv770.max_backends) { |
440 | rdev->config.rv770.max_backends = tmp; |
1275 | rdev->config.rv770.max_backends = tmp; |
441 | } |
1276 | } |
442 | 1277 | ||
443 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
1278 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
444 | tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); |
1279 | tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); |
445 | if (tmp < rdev->config.rv770.max_pipes) { |
1280 | if (tmp < rdev->config.rv770.max_pipes) { |
446 | rdev->config.rv770.max_pipes = tmp; |
1281 | rdev->config.rv770.max_pipes = tmp; |
447 | } |
1282 | } |
448 | tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); |
1283 | tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); |
449 | if (tmp < rdev->config.rv770.max_simds) { |
1284 | if (tmp < rdev->config.rv770.max_simds) { |
450 | rdev->config.rv770.max_simds = tmp; |
1285 | rdev->config.rv770.max_simds = tmp; |
451 | } |
1286 | } |
452 | 1287 | ||
453 | switch (rdev->config.rv770.max_tile_pipes) { |
1288 | switch (rdev->config.rv770.max_tile_pipes) { |
454 | case 1: |
1289 | case 1: |
455 | default: |
1290 | default: |
456 | gb_tiling_config = PIPE_TILING(0); |
1291 | gb_tiling_config = PIPE_TILING(0); |
457 | break; |
1292 | break; |
458 | case 2: |
1293 | case 2: |
459 | gb_tiling_config = PIPE_TILING(1); |
1294 | gb_tiling_config = PIPE_TILING(1); |
460 | break; |
1295 | break; |
461 | case 4: |
1296 | case 4: |
462 | gb_tiling_config = PIPE_TILING(2); |
1297 | gb_tiling_config = PIPE_TILING(2); |
463 | break; |
1298 | break; |
464 | case 8: |
1299 | case 8: |
465 | gb_tiling_config = PIPE_TILING(3); |
1300 | gb_tiling_config = PIPE_TILING(3); |
466 | break; |
1301 | break; |
467 | } |
1302 | } |
468 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
1303 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
469 | 1304 | ||
470 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; |
1305 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; |
471 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
1306 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
472 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, |
1307 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, |
473 | R7XX_MAX_BACKENDS, disabled_rb_mask); |
1308 | R7XX_MAX_BACKENDS, disabled_rb_mask); |
474 | gb_tiling_config |= tmp << 16; |
1309 | gb_tiling_config |= tmp << 16; |
475 | rdev->config.rv770.backend_map = tmp; |
1310 | rdev->config.rv770.backend_map = tmp; |
476 | 1311 | ||
477 | if (rdev->family == CHIP_RV770) |
1312 | if (rdev->family == CHIP_RV770) |
478 | gb_tiling_config |= BANK_TILING(1); |
1313 | gb_tiling_config |= BANK_TILING(1); |
479 | else { |
1314 | else { |
480 | if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) |
1315 | if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) |
481 | gb_tiling_config |= BANK_TILING(1); |
1316 | gb_tiling_config |= BANK_TILING(1); |
482 | else |
1317 | else |
483 | gb_tiling_config |= BANK_TILING(0); |
1318 | gb_tiling_config |= BANK_TILING(0); |
484 | } |
1319 | } |
485 | rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); |
1320 | rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); |
486 | gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
1321 | gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
487 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
1322 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
488 | gb_tiling_config |= ROW_TILING(3); |
1323 | gb_tiling_config |= ROW_TILING(3); |
489 | gb_tiling_config |= SAMPLE_SPLIT(3); |
1324 | gb_tiling_config |= SAMPLE_SPLIT(3); |
490 | } else { |
1325 | } else { |
491 | gb_tiling_config |= |
1326 | gb_tiling_config |= |
492 | ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
1327 | ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
493 | gb_tiling_config |= |
1328 | gb_tiling_config |= |
494 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
1329 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
495 | } |
1330 | } |
496 | 1331 | ||
497 | gb_tiling_config |= BANK_SWAPS(1); |
1332 | gb_tiling_config |= BANK_SWAPS(1); |
498 | rdev->config.rv770.tile_config = gb_tiling_config; |
1333 | rdev->config.rv770.tile_config = gb_tiling_config; |
499 | 1334 | ||
500 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
1335 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
501 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
1336 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
502 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
1337 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
503 | WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
1338 | WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
504 | WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); |
1339 | WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); |
- | 1340 | if (rdev->family == CHIP_RV730) { |
|
- | 1341 | WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
|
- | 1342 | WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
|
- | 1343 | WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
|
- | 1344 | } |
|
505 | 1345 | ||
506 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
1346 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
507 | WREG32(CGTS_TCC_DISABLE, 0); |
1347 | WREG32(CGTS_TCC_DISABLE, 0); |
508 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
1348 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
509 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
1349 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
510 | 1350 | ||
511 | 1351 | ||
512 | num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
1352 | num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
513 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
1353 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
514 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
1354 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
515 | 1355 | ||
516 | /* set HW defaults for 3D engine */ |
1356 | /* set HW defaults for 3D engine */ |
517 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
1357 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
518 | ROQ_IB2_START(0x2b))); |
1358 | ROQ_IB2_START(0x2b))); |
519 | 1359 | ||
520 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
1360 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
521 | 1361 | ||
522 | ta_aux_cntl = RREG32(TA_CNTL_AUX); |
1362 | ta_aux_cntl = RREG32(TA_CNTL_AUX); |
523 | WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); |
1363 | WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); |
524 | 1364 | ||
525 | sx_debug_1 = RREG32(SX_DEBUG_1); |
1365 | sx_debug_1 = RREG32(SX_DEBUG_1); |
526 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
1366 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
527 | WREG32(SX_DEBUG_1, sx_debug_1); |
1367 | WREG32(SX_DEBUG_1, sx_debug_1); |
528 | 1368 | ||
529 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
1369 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
530 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
1370 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
531 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
1371 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
532 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
1372 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
533 | 1373 | ||
534 | if (rdev->family != CHIP_RV740) |
1374 | if (rdev->family != CHIP_RV740) |
535 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | |
1375 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | |
536 | GS_FLUSH_CTL(4) | |
1376 | GS_FLUSH_CTL(4) | |
537 | ACK_FLUSH_CTL(3) | |
1377 | ACK_FLUSH_CTL(3) | |
538 | SYNC_FLUSH_CTL)); |
1378 | SYNC_FLUSH_CTL)); |
539 | 1379 | ||
540 | if (rdev->family != CHIP_RV770) |
1380 | if (rdev->family != CHIP_RV770) |
541 | WREG32(SMX_SAR_CTL0, 0x00003f3f); |
1381 | WREG32(SMX_SAR_CTL0, 0x00003f3f); |
542 | 1382 | ||
543 | db_debug3 = RREG32(DB_DEBUG3); |
1383 | db_debug3 = RREG32(DB_DEBUG3); |
544 | db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); |
1384 | db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); |
545 | switch (rdev->family) { |
1385 | switch (rdev->family) { |
546 | case CHIP_RV770: |
1386 | case CHIP_RV770: |
547 | case CHIP_RV740: |
1387 | case CHIP_RV740: |
548 | db_debug3 |= DB_CLK_OFF_DELAY(0x1f); |
1388 | db_debug3 |= DB_CLK_OFF_DELAY(0x1f); |
549 | break; |
1389 | break; |
550 | case CHIP_RV710: |
1390 | case CHIP_RV710: |
551 | case CHIP_RV730: |
1391 | case CHIP_RV730: |
552 | default: |
1392 | default: |
553 | db_debug3 |= DB_CLK_OFF_DELAY(2); |
1393 | db_debug3 |= DB_CLK_OFF_DELAY(2); |
554 | break; |
1394 | break; |
555 | } |
1395 | } |
556 | WREG32(DB_DEBUG3, db_debug3); |
1396 | WREG32(DB_DEBUG3, db_debug3); |
557 | 1397 | ||
558 | if (rdev->family != CHIP_RV770) { |
1398 | if (rdev->family != CHIP_RV770) { |
559 | db_debug4 = RREG32(DB_DEBUG4); |
1399 | db_debug4 = RREG32(DB_DEBUG4); |
560 | db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; |
1400 | db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; |
561 | WREG32(DB_DEBUG4, db_debug4); |
1401 | WREG32(DB_DEBUG4, db_debug4); |
562 | } |
1402 | } |
563 | 1403 | ||
564 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | |
1404 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | |
565 | POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | |
1405 | POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | |
566 | SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); |
1406 | SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); |
567 | 1407 | ||
568 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | |
1408 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | |
569 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | |
1409 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | |
570 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); |
1410 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); |
571 | 1411 | ||
572 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
1412 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
573 | 1413 | ||
574 | WREG32(VGT_NUM_INSTANCES, 1); |
1414 | WREG32(VGT_NUM_INSTANCES, 1); |
575 | 1415 | ||
576 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
1416 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
577 | 1417 | ||
578 | WREG32(CP_PERFMON_CNTL, 0); |
1418 | WREG32(CP_PERFMON_CNTL, 0); |
579 | 1419 | ||
580 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
1420 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
581 | DONE_FIFO_HIWATER(0xe0) | |
1421 | DONE_FIFO_HIWATER(0xe0) | |
582 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
1422 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
583 | switch (rdev->family) { |
1423 | switch (rdev->family) { |
584 | case CHIP_RV770: |
1424 | case CHIP_RV770: |
585 | case CHIP_RV730: |
1425 | case CHIP_RV730: |
586 | case CHIP_RV710: |
1426 | case CHIP_RV710: |
587 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
1427 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
588 | break; |
1428 | break; |
589 | case CHIP_RV740: |
1429 | case CHIP_RV740: |
590 | default: |
1430 | default: |
591 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
1431 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
592 | break; |
1432 | break; |
593 | } |
1433 | } |
594 | WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); |
1434 | WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); |
595 | 1435 | ||
596 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
1436 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
597 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
1437 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
598 | */ |
1438 | */ |
599 | sq_config = RREG32(SQ_CONFIG); |
1439 | sq_config = RREG32(SQ_CONFIG); |
600 | sq_config &= ~(PS_PRIO(3) | |
1440 | sq_config &= ~(PS_PRIO(3) | |
601 | VS_PRIO(3) | |
1441 | VS_PRIO(3) | |
602 | GS_PRIO(3) | |
1442 | GS_PRIO(3) | |
603 | ES_PRIO(3)); |
1443 | ES_PRIO(3)); |
604 | sq_config |= (DX9_CONSTS | |
1444 | sq_config |= (DX9_CONSTS | |
605 | VC_ENABLE | |
1445 | VC_ENABLE | |
606 | EXPORT_SRC_C | |
1446 | EXPORT_SRC_C | |
607 | PS_PRIO(0) | |
1447 | PS_PRIO(0) | |
608 | VS_PRIO(1) | |
1448 | VS_PRIO(1) | |
609 | GS_PRIO(2) | |
1449 | GS_PRIO(2) | |
610 | ES_PRIO(3)); |
1450 | ES_PRIO(3)); |
611 | if (rdev->family == CHIP_RV710) |
1451 | if (rdev->family == CHIP_RV710) |
612 | /* no vertex cache */ |
1452 | /* no vertex cache */ |
613 | sq_config &= ~VC_ENABLE; |
1453 | sq_config &= ~VC_ENABLE; |
614 | 1454 | ||
615 | WREG32(SQ_CONFIG, sq_config); |
1455 | WREG32(SQ_CONFIG, sq_config); |
616 | 1456 | ||
617 | WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
1457 | WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
618 | NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
1458 | NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
619 | NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); |
1459 | NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); |
620 | 1460 | ||
621 | WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | |
1461 | WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | |
622 | NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); |
1462 | NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); |
623 | 1463 | ||
624 | sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | |
1464 | sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | |
625 | NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | |
1465 | NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | |
626 | NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); |
1466 | NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); |
627 | if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) |
1467 | if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) |
628 | sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); |
1468 | sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); |
629 | else |
1469 | else |
630 | sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); |
1470 | sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); |
631 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
1471 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
632 | 1472 | ||
633 | WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
1473 | WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
634 | NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
1474 | NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
635 | 1475 | ||
636 | WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
1476 | WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
637 | NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
1477 | NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
638 | 1478 | ||
639 | sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
1479 | sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
640 | SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | |
1480 | SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | |
641 | SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
1481 | SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
642 | SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); |
1482 | SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); |
643 | 1483 | ||
644 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); |
1484 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); |
645 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); |
1485 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); |
646 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); |
1486 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); |
647 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); |
1487 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); |
648 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); |
1488 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); |
649 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); |
1489 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); |
650 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); |
1490 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); |
651 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); |
1491 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); |
652 | 1492 | ||
653 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
1493 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
654 | FORCE_EOV_MAX_REZ_CNT(255))); |
1494 | FORCE_EOV_MAX_REZ_CNT(255))); |
655 | 1495 | ||
656 | if (rdev->family == CHIP_RV710) |
1496 | if (rdev->family == CHIP_RV710) |
657 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | |
1497 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | |
658 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
1498 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
659 | else |
1499 | else |
660 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | |
1500 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | |
661 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
1501 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
662 | 1502 | ||
663 | switch (rdev->family) { |
1503 | switch (rdev->family) { |
664 | case CHIP_RV770: |
1504 | case CHIP_RV770: |
665 | case CHIP_RV730: |
1505 | case CHIP_RV730: |
666 | case CHIP_RV740: |
1506 | case CHIP_RV740: |
667 | gs_prim_buffer_depth = 384; |
1507 | gs_prim_buffer_depth = 384; |
668 | break; |
1508 | break; |
669 | case CHIP_RV710: |
1509 | case CHIP_RV710: |
670 | gs_prim_buffer_depth = 128; |
1510 | gs_prim_buffer_depth = 128; |
671 | break; |
1511 | break; |
672 | default: |
1512 | default: |
673 | break; |
1513 | break; |
674 | } |
1514 | } |
675 | 1515 | ||
676 | num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; |
1516 | num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; |
677 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; |
1517 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; |
678 | /* Max value for this is 256 */ |
1518 | /* Max value for this is 256 */ |
679 | if (vgt_gs_per_es > 256) |
1519 | if (vgt_gs_per_es > 256) |
680 | vgt_gs_per_es = 256; |
1520 | vgt_gs_per_es = 256; |
681 | 1521 | ||
682 | WREG32(VGT_ES_PER_GS, 128); |
1522 | WREG32(VGT_ES_PER_GS, 128); |
683 | WREG32(VGT_GS_PER_ES, vgt_gs_per_es); |
1523 | WREG32(VGT_GS_PER_ES, vgt_gs_per_es); |
684 | WREG32(VGT_GS_PER_VS, 2); |
1524 | WREG32(VGT_GS_PER_VS, 2); |
685 | 1525 | ||
686 | /* more default values. 2D/3D driver should adjust as needed */ |
1526 | /* more default values. 2D/3D driver should adjust as needed */ |
687 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
1527 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
688 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
1528 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
689 | WREG32(VGT_STRMOUT_EN, 0); |
1529 | WREG32(VGT_STRMOUT_EN, 0); |
690 | WREG32(SX_MISC, 0); |
1530 | WREG32(SX_MISC, 0); |
691 | WREG32(PA_SC_MODE_CNTL, 0); |
1531 | WREG32(PA_SC_MODE_CNTL, 0); |
692 | WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); |
1532 | WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); |
693 | WREG32(PA_SC_AA_CONFIG, 0); |
1533 | WREG32(PA_SC_AA_CONFIG, 0); |
694 | WREG32(PA_SC_CLIPRECT_RULE, 0xffff); |
1534 | WREG32(PA_SC_CLIPRECT_RULE, 0xffff); |
695 | WREG32(PA_SC_LINE_STIPPLE, 0); |
1535 | WREG32(PA_SC_LINE_STIPPLE, 0); |
696 | WREG32(SPI_INPUT_Z, 0); |
1536 | WREG32(SPI_INPUT_Z, 0); |
697 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
1537 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
698 | WREG32(CB_COLOR7_FRAG, 0); |
1538 | WREG32(CB_COLOR7_FRAG, 0); |
699 | 1539 | ||
700 | /* clear render buffer base addresses */ |
1540 | /* clear render buffer base addresses */ |
701 | WREG32(CB_COLOR0_BASE, 0); |
1541 | WREG32(CB_COLOR0_BASE, 0); |
702 | WREG32(CB_COLOR1_BASE, 0); |
1542 | WREG32(CB_COLOR1_BASE, 0); |
703 | WREG32(CB_COLOR2_BASE, 0); |
1543 | WREG32(CB_COLOR2_BASE, 0); |
704 | WREG32(CB_COLOR3_BASE, 0); |
1544 | WREG32(CB_COLOR3_BASE, 0); |
705 | WREG32(CB_COLOR4_BASE, 0); |
1545 | WREG32(CB_COLOR4_BASE, 0); |
706 | WREG32(CB_COLOR5_BASE, 0); |
1546 | WREG32(CB_COLOR5_BASE, 0); |
707 | WREG32(CB_COLOR6_BASE, 0); |
1547 | WREG32(CB_COLOR6_BASE, 0); |
708 | WREG32(CB_COLOR7_BASE, 0); |
1548 | WREG32(CB_COLOR7_BASE, 0); |
709 | 1549 | ||
710 | WREG32(TCP_CNTL, 0); |
1550 | WREG32(TCP_CNTL, 0); |
711 | 1551 | ||
712 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
1552 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
713 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
1553 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
714 | 1554 | ||
715 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
1555 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
716 | 1556 | ||
717 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
1557 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
718 | NUM_CLIP_SEQ(3))); |
1558 | NUM_CLIP_SEQ(3))); |
719 | WREG32(VC_ENHANCE, 0); |
1559 | WREG32(VC_ENHANCE, 0); |
720 | } |
1560 | } |
721 | 1561 | ||
722 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
1562 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
723 | { |
1563 | { |
724 | u64 size_bf, size_af; |
1564 | u64 size_bf, size_af; |
725 | 1565 | ||
726 | if (mc->mc_vram_size > 0xE0000000) { |
1566 | if (mc->mc_vram_size > 0xE0000000) { |
727 | /* leave room for at least 512M GTT */ |
1567 | /* leave room for at least 512M GTT */ |
728 | dev_warn(rdev->dev, "limiting VRAM\n"); |
1568 | dev_warn(rdev->dev, "limiting VRAM\n"); |
729 | mc->real_vram_size = 0xE0000000; |
1569 | mc->real_vram_size = 0xE0000000; |
730 | mc->mc_vram_size = 0xE0000000; |
1570 | mc->mc_vram_size = 0xE0000000; |
731 | } |
1571 | } |
732 | if (rdev->flags & RADEON_IS_AGP) { |
1572 | if (rdev->flags & RADEON_IS_AGP) { |
733 | size_bf = mc->gtt_start; |
1573 | size_bf = mc->gtt_start; |
734 | size_af = 0xFFFFFFFF - mc->gtt_end; |
1574 | size_af = mc->mc_mask - mc->gtt_end; |
735 | if (size_bf > size_af) { |
1575 | if (size_bf > size_af) { |
736 | if (mc->mc_vram_size > size_bf) { |
1576 | if (mc->mc_vram_size > size_bf) { |
737 | dev_warn(rdev->dev, "limiting VRAM\n"); |
1577 | dev_warn(rdev->dev, "limiting VRAM\n"); |
738 | mc->real_vram_size = size_bf; |
1578 | mc->real_vram_size = size_bf; |
739 | mc->mc_vram_size = size_bf; |
1579 | mc->mc_vram_size = size_bf; |
740 | } |
1580 | } |
741 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; |
1581 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; |
742 | } else { |
1582 | } else { |
743 | if (mc->mc_vram_size > size_af) { |
1583 | if (mc->mc_vram_size > size_af) { |
744 | dev_warn(rdev->dev, "limiting VRAM\n"); |
1584 | dev_warn(rdev->dev, "limiting VRAM\n"); |
745 | mc->real_vram_size = size_af; |
1585 | mc->real_vram_size = size_af; |
746 | mc->mc_vram_size = size_af; |
1586 | mc->mc_vram_size = size_af; |
747 | } |
1587 | } |
748 | mc->vram_start = mc->gtt_end + 1; |
1588 | mc->vram_start = mc->gtt_end + 1; |
749 | } |
1589 | } |
750 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
1590 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
751 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
1591 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
752 | mc->mc_vram_size >> 20, mc->vram_start, |
1592 | mc->mc_vram_size >> 20, mc->vram_start, |
753 | mc->vram_end, mc->real_vram_size >> 20); |
1593 | mc->vram_end, mc->real_vram_size >> 20); |
754 | } else { |
1594 | } else { |
755 | radeon_vram_location(rdev, &rdev->mc, 0); |
1595 | radeon_vram_location(rdev, &rdev->mc, 0); |
756 | rdev->mc.gtt_base_align = 0; |
1596 | rdev->mc.gtt_base_align = 0; |
757 | radeon_gtt_location(rdev, mc); |
1597 | radeon_gtt_location(rdev, mc); |
758 | } |
1598 | } |
759 | } |
1599 | } |
760 | 1600 | ||
761 | static int rv770_mc_init(struct radeon_device *rdev) |
1601 | static int rv770_mc_init(struct radeon_device *rdev) |
762 | { |
1602 | { |
763 | u32 tmp; |
1603 | u32 tmp; |
764 | int chansize, numchan; |
1604 | int chansize, numchan; |
765 | 1605 | ||
766 | /* Get VRAM informations */ |
1606 | /* Get VRAM informations */ |
767 | rdev->mc.vram_is_ddr = true; |
1607 | rdev->mc.vram_is_ddr = true; |
768 | tmp = RREG32(MC_ARB_RAMCFG); |
1608 | tmp = RREG32(MC_ARB_RAMCFG); |
769 | if (tmp & CHANSIZE_OVERRIDE) { |
1609 | if (tmp & CHANSIZE_OVERRIDE) { |
770 | chansize = 16; |
1610 | chansize = 16; |
771 | } else if (tmp & CHANSIZE_MASK) { |
1611 | } else if (tmp & CHANSIZE_MASK) { |
772 | chansize = 64; |
1612 | chansize = 64; |
773 | } else { |
1613 | } else { |
774 | chansize = 32; |
1614 | chansize = 32; |
775 | } |
1615 | } |
776 | tmp = RREG32(MC_SHARED_CHMAP); |
1616 | tmp = RREG32(MC_SHARED_CHMAP); |
777 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
1617 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
778 | case 0: |
1618 | case 0: |
779 | default: |
1619 | default: |
780 | numchan = 1; |
1620 | numchan = 1; |
781 | break; |
1621 | break; |
782 | case 1: |
1622 | case 1: |
783 | numchan = 2; |
1623 | numchan = 2; |
784 | break; |
1624 | break; |
785 | case 2: |
1625 | case 2: |
786 | numchan = 4; |
1626 | numchan = 4; |
787 | break; |
1627 | break; |
788 | case 3: |
1628 | case 3: |
789 | numchan = 8; |
1629 | numchan = 8; |
790 | break; |
1630 | break; |
791 | } |
1631 | } |
792 | rdev->mc.vram_width = numchan * chansize; |
1632 | rdev->mc.vram_width = numchan * chansize; |
793 | /* Could aper size report 0 ? */ |
1633 | /* Could aper size report 0 ? */ |
794 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
1634 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
795 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
1635 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
796 | /* Setup GPU memory space */ |
1636 | /* Setup GPU memory space */ |
797 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
1637 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
798 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
1638 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
799 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
1639 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
800 | r700_vram_gtt_location(rdev, &rdev->mc); |
1640 | r700_vram_gtt_location(rdev, &rdev->mc); |
801 | radeon_update_bandwidth_info(rdev); |
1641 | radeon_update_bandwidth_info(rdev); |
802 | 1642 | ||
803 | return 0; |
1643 | return 0; |
804 | } |
1644 | } |
- | 1645 | ||
- | 1646 | /** |
|
- | 1647 | * rv770_copy_dma - copy pages using the DMA engine |
|
- | 1648 | * |
|
- | 1649 | * @rdev: radeon_device pointer |
|
- | 1650 | * @src_offset: src GPU address |
|
- | 1651 | * @dst_offset: dst GPU address |
|
- | 1652 | * @num_gpu_pages: number of GPU pages to xfer |
|
- | 1653 | * @fence: radeon fence object |
|
- | 1654 | * |
|
- | 1655 | * Copy GPU paging using the DMA engine (r7xx). |
|
- | 1656 | * Used by the radeon ttm implementation to move pages if |
|
- | 1657 | * registered as the asic copy callback. |
|
- | 1658 | */ |
|
- | 1659 | int rv770_copy_dma(struct radeon_device *rdev, |
|
- | 1660 | uint64_t src_offset, uint64_t dst_offset, |
|
- | 1661 | unsigned num_gpu_pages, |
|
- | 1662 | struct radeon_fence **fence) |
|
- | 1663 | { |
|
- | 1664 | struct radeon_semaphore *sem = NULL; |
|
- | 1665 | int ring_index = rdev->asic->copy.dma_ring_index; |
|
- | 1666 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
|
- | 1667 | u32 size_in_dw, cur_size_in_dw; |
|
- | 1668 | int i, num_loops; |
|
- | 1669 | int r = 0; |
|
- | 1670 | ||
- | 1671 | r = radeon_semaphore_create(rdev, &sem); |
|
- | 1672 | if (r) { |
|
- | 1673 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
|
- | 1674 | return r; |
|
- | 1675 | } |
|
- | 1676 | ||
- | 1677 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
|
- | 1678 | num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF); |
|
- | 1679 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8); |
|
- | 1680 | if (r) { |
|
- | 1681 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
|
- | 1682 | radeon_semaphore_free(rdev, &sem, NULL); |
|
- | 1683 | return r; |
|
- | 1684 | } |
|
- | 1685 | ||
- | 1686 | if (radeon_fence_need_sync(*fence, ring->idx)) { |
|
- | 1687 | radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, |
|
- | 1688 | ring->idx); |
|
- | 1689 | radeon_fence_note_sync(*fence, ring->idx); |
|
- | 1690 | } else { |
|
- | 1691 | radeon_semaphore_free(rdev, &sem, NULL); |
|
- | 1692 | } |
|
- | 1693 | ||
- | 1694 | for (i = 0; i < num_loops; i++) { |
|
- | 1695 | cur_size_in_dw = size_in_dw; |
|
- | 1696 | if (cur_size_in_dw > 0xFFFF) |
|
- | 1697 | cur_size_in_dw = 0xFFFF; |
|
- | 1698 | size_in_dw -= cur_size_in_dw; |
|
- | 1699 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); |
|
- | 1700 | radeon_ring_write(ring, dst_offset & 0xfffffffc); |
|
- | 1701 | radeon_ring_write(ring, src_offset & 0xfffffffc); |
|
- | 1702 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); |
|
- | 1703 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
|
- | 1704 | src_offset += cur_size_in_dw * 4; |
|
- | 1705 | dst_offset += cur_size_in_dw * 4; |
|
- | 1706 | } |
|
- | 1707 | ||
- | 1708 | r = radeon_fence_emit(rdev, fence, ring->idx); |
|
- | 1709 | if (r) { |
|
- | 1710 | radeon_ring_unlock_undo(rdev, ring); |
|
- | 1711 | return r; |
|
- | 1712 | } |
|
- | 1713 | ||
- | 1714 | radeon_ring_unlock_commit(rdev, ring); |
|
- | 1715 | radeon_semaphore_free(rdev, &sem, *fence); |
|
- | 1716 | ||
- | 1717 | return r; |
|
- | 1718 | } |
|
805 | 1719 | ||
806 | static int rv770_startup(struct radeon_device *rdev) |
1720 | static int rv770_startup(struct radeon_device *rdev) |
807 | { |
1721 | { |
808 | struct radeon_ring *ring; |
1722 | struct radeon_ring *ring; |
809 | int r; |
1723 | int r; |
810 | 1724 | ||
811 | /* enable pcie gen2 link */ |
1725 | /* enable pcie gen2 link */ |
812 | rv770_pcie_gen2_enable(rdev); |
1726 | rv770_pcie_gen2_enable(rdev); |
813 | 1727 | ||
814 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
1728 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
815 | r = r600_init_microcode(rdev); |
1729 | r = r600_init_microcode(rdev); |
816 | if (r) { |
1730 | if (r) { |
817 | DRM_ERROR("Failed to load firmware!\n"); |
1731 | DRM_ERROR("Failed to load firmware!\n"); |
818 | return r; |
1732 | return r; |
819 | } |
1733 | } |
820 | } |
1734 | } |
821 | 1735 | ||
822 | r = r600_vram_scratch_init(rdev); |
1736 | r = r600_vram_scratch_init(rdev); |
823 | if (r) |
1737 | if (r) |
824 | return r; |
1738 | return r; |
825 | 1739 | ||
826 | rv770_mc_program(rdev); |
1740 | rv770_mc_program(rdev); |
827 | if (rdev->flags & RADEON_IS_AGP) { |
1741 | if (rdev->flags & RADEON_IS_AGP) { |
828 | rv770_agp_enable(rdev); |
1742 | rv770_agp_enable(rdev); |
829 | } else { |
1743 | } else { |
830 | r = rv770_pcie_gart_enable(rdev); |
1744 | r = rv770_pcie_gart_enable(rdev); |
831 | if (r) |
1745 | if (r) |
832 | return r; |
1746 | return r; |
833 | } |
1747 | } |
834 | 1748 | ||
835 | rv770_gpu_init(rdev); |
1749 | rv770_gpu_init(rdev); |
836 | r = r600_blit_init(rdev); |
1750 | r = r600_blit_init(rdev); |
837 | if (r) { |
1751 | if (r) { |
838 | r600_blit_fini(rdev); |
1752 | r600_blit_fini(rdev); |
839 | rdev->asic->copy.copy = NULL; |
1753 | rdev->asic->copy.copy = NULL; |
840 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1754 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
841 | } |
1755 | } |
842 | - | ||
843 | // r = r600_video_init(rdev); |
- | |
844 | // if (r) { |
- | |
845 | // r600_video_fini(rdev); |
- | |
846 | // rdev->asic->copy = NULL; |
- | |
847 | // dev_warn(rdev->dev, "failed video blitter (%d) falling back to memcpy\n", r); |
- | |
848 | // } |
- | |
849 | 1756 | ||
850 | /* allocate wb buffer */ |
1757 | /* allocate wb buffer */ |
851 | r = radeon_wb_init(rdev); |
1758 | r = radeon_wb_init(rdev); |
852 | if (r) |
1759 | if (r) |
853 | return r; |
1760 | return r; |
854 | 1761 | ||
855 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
1762 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
856 | if (r) { |
1763 | if (r) { |
857 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
1764 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
858 | return r; |
1765 | return r; |
859 | } |
1766 | } |
860 | 1767 | ||
861 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
1768 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
862 | if (r) { |
1769 | if (r) { |
863 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
1770 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
864 | return r; |
1771 | return r; |
865 | } |
1772 | } |
- | 1773 | ||
- | 1774 | // r = rv770_uvd_resume(rdev); |
|
- | 1775 | // if (!r) { |
|
- | 1776 | // r = radeon_fence_driver_start_ring(rdev, |
|
- | 1777 | // R600_RING_TYPE_UVD_INDEX); |
|
- | 1778 | // if (r) |
|
- | 1779 | // dev_err(rdev->dev, "UVD fences init error (%d).\n", r); |
|
- | 1780 | // } |
|
- | 1781 | ||
- | 1782 | // if (r) |
|
- | 1783 | // rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
|
866 | 1784 | ||
- | 1785 | /* Enable IRQ */ |
|
- | 1786 | if (!rdev->irq.installed) { |
|
- | 1787 | r = radeon_irq_kms_init(rdev); |
|
- | 1788 | if (r) |
|
- | 1789 | return r; |
|
- | 1790 | } |
|
867 | /* Enable IRQ */ |
1791 | |
868 | r = r600_irq_init(rdev); |
1792 | r = r600_irq_init(rdev); |
869 | if (r) { |
1793 | if (r) { |
870 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
1794 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
871 | // radeon_irq_kms_fini(rdev); |
1795 | // radeon_irq_kms_fini(rdev); |
872 | return r; |
1796 | return r; |
873 | } |
1797 | } |
874 | r600_irq_set(rdev); |
1798 | r600_irq_set(rdev); |
875 | 1799 | ||
876 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
1800 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
877 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
1801 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
878 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
1802 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
879 | 0, 0xfffff, RADEON_CP_PACKET2); |
1803 | 0, 0xfffff, RADEON_CP_PACKET2); |
880 | if (r) |
1804 | if (r) |
881 | return r; |
1805 | return r; |
882 | 1806 | ||
883 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
1807 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
884 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
1808 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
885 | DMA_RB_RPTR, DMA_RB_WPTR, |
1809 | DMA_RB_RPTR, DMA_RB_WPTR, |
886 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
1810 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
887 | if (r) |
1811 | if (r) |
888 | return r; |
1812 | return r; |
889 | 1813 | ||
890 | r = rv770_cp_load_microcode(rdev); |
1814 | r = rv770_cp_load_microcode(rdev); |
891 | if (r) |
1815 | if (r) |
892 | return r; |
1816 | return r; |
893 | r = r600_cp_resume(rdev); |
1817 | r = r600_cp_resume(rdev); |
894 | if (r) |
1818 | if (r) |
895 | return r; |
1819 | return r; |
896 | 1820 | ||
897 | r = r600_dma_resume(rdev); |
1821 | r = r600_dma_resume(rdev); |
898 | if (r) |
1822 | if (r) |
899 | return r; |
1823 | return r; |
- | 1824 | ||
- | 1825 | // ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
|
- | 1826 | // if (ring->ring_size) { |
|
- | 1827 | // r = radeon_ring_init(rdev, ring, ring->ring_size, |
|
- | 1828 | // R600_WB_UVD_RPTR_OFFSET, |
|
- | 1829 | // UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, |
|
- | 1830 | // 0, 0xfffff, RADEON_CP_PACKET2); |
|
- | 1831 | // if (!r) |
|
- | 1832 | // r = r600_uvd_init(rdev); |
|
- | 1833 | ||
- | 1834 | // if (r) |
|
- | 1835 | // DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
|
- | 1836 | // } |
|
900 | 1837 | ||
901 | r = radeon_ib_pool_init(rdev); |
1838 | r = radeon_ib_pool_init(rdev); |
902 | if (r) { |
1839 | if (r) { |
903 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
1840 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
904 | return r; |
1841 | return r; |
905 | } |
1842 | } |
906 | 1843 | ||
907 | 1844 | ||
908 | return 0; |
1845 | return 0; |
909 | } |
1846 | } |
910 | 1847 | ||
911 | 1848 | ||
912 | 1849 | ||
913 | 1850 | ||
914 | 1851 | ||
915 | 1852 | ||
916 | 1853 | ||
917 | /* Plan is to move initialization in that function and use |
1854 | /* Plan is to move initialization in that function and use |
918 | * helper function so that radeon_device_init pretty much |
1855 | * helper function so that radeon_device_init pretty much |
919 | * do nothing more than calling asic specific function. This |
1856 | * do nothing more than calling asic specific function. This |
920 | * should also allow to remove a bunch of callback function |
1857 | * should also allow to remove a bunch of callback function |
921 | * like vram_info. |
1858 | * like vram_info. |
922 | */ |
1859 | */ |
923 | int rv770_init(struct radeon_device *rdev) |
1860 | int rv770_init(struct radeon_device *rdev) |
924 | { |
1861 | { |
925 | int r; |
1862 | int r; |
926 | 1863 | ||
927 | /* Read BIOS */ |
1864 | /* Read BIOS */ |
928 | if (!radeon_get_bios(rdev)) { |
1865 | if (!radeon_get_bios(rdev)) { |
929 | if (ASIC_IS_AVIVO(rdev)) |
1866 | if (ASIC_IS_AVIVO(rdev)) |
930 | return -EINVAL; |
1867 | return -EINVAL; |
931 | } |
1868 | } |
932 | /* Must be an ATOMBIOS */ |
1869 | /* Must be an ATOMBIOS */ |
933 | if (!rdev->is_atom_bios) { |
1870 | if (!rdev->is_atom_bios) { |
934 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
1871 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
935 | return -EINVAL; |
1872 | return -EINVAL; |
936 | } |
1873 | } |
937 | r = radeon_atombios_init(rdev); |
1874 | r = radeon_atombios_init(rdev); |
938 | if (r) |
1875 | if (r) |
939 | return r; |
1876 | return r; |
940 | /* Post card if necessary */ |
1877 | /* Post card if necessary */ |
941 | if (!radeon_card_posted(rdev)) { |
1878 | if (!radeon_card_posted(rdev)) { |
942 | if (!rdev->bios) { |
1879 | if (!rdev->bios) { |
943 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
1880 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
944 | return -EINVAL; |
1881 | return -EINVAL; |
945 | } |
1882 | } |
946 | DRM_INFO("GPU not posted. posting now...\n"); |
1883 | DRM_INFO("GPU not posted. posting now...\n"); |
947 | atom_asic_init(rdev->mode_info.atom_context); |
1884 | atom_asic_init(rdev->mode_info.atom_context); |
948 | } |
1885 | } |
- | 1886 | /* init golden registers */ |
|
- | 1887 | rv770_init_golden_registers(rdev); |
|
949 | /* Initialize scratch registers */ |
1888 | /* Initialize scratch registers */ |
950 | r600_scratch_init(rdev); |
1889 | r600_scratch_init(rdev); |
951 | /* Initialize surface registers */ |
1890 | /* Initialize surface registers */ |
952 | radeon_surface_init(rdev); |
1891 | radeon_surface_init(rdev); |
953 | /* Initialize clocks */ |
1892 | /* Initialize clocks */ |
954 | radeon_get_clock_info(rdev->ddev); |
1893 | radeon_get_clock_info(rdev->ddev); |
955 | /* Fence driver */ |
1894 | /* Fence driver */ |
956 | r = radeon_fence_driver_init(rdev); |
1895 | r = radeon_fence_driver_init(rdev); |
957 | if (r) |
1896 | if (r) |
958 | return r; |
1897 | return r; |
959 | /* initialize AGP */ |
1898 | /* initialize AGP */ |
960 | if (rdev->flags & RADEON_IS_AGP) { |
1899 | if (rdev->flags & RADEON_IS_AGP) { |
961 | r = radeon_agp_init(rdev); |
1900 | r = radeon_agp_init(rdev); |
962 | if (r) |
1901 | if (r) |
963 | radeon_agp_disable(rdev); |
1902 | radeon_agp_disable(rdev); |
964 | } |
1903 | } |
965 | r = rv770_mc_init(rdev); |
1904 | r = rv770_mc_init(rdev); |
966 | if (r) |
1905 | if (r) |
967 | return r; |
1906 | return r; |
968 | /* Memory manager */ |
1907 | /* Memory manager */ |
969 | r = radeon_bo_init(rdev); |
1908 | r = radeon_bo_init(rdev); |
970 | if (r) |
1909 | if (r) |
971 | return r; |
1910 | return r; |
972 | - | ||
973 | r = radeon_irq_kms_init(rdev); |
- | |
974 | if (r) |
- | |
975 | return r; |
- | |
976 | 1911 | ||
977 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
1912 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
978 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
1913 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
979 | 1914 | ||
980 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
1915 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
981 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
1916 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
- | 1917 | ||
- | 1918 | // r = radeon_uvd_init(rdev); |
|
- | 1919 | // if (!r) { |
|
- | 1920 | // rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; |
|
- | 1921 | // r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], |
|
- | 1922 | // 4096); |
|
- | 1923 | // } |
|
982 | 1924 | ||
983 | rdev->ih.ring_obj = NULL; |
1925 | rdev->ih.ring_obj = NULL; |
984 | r600_ih_ring_init(rdev, 64 * 1024); |
1926 | r600_ih_ring_init(rdev, 64 * 1024); |
985 | 1927 | ||
986 | r = r600_pcie_gart_init(rdev); |
1928 | r = r600_pcie_gart_init(rdev); |
987 | if (r) |
1929 | if (r) |
988 | return r; |
1930 | return r; |
989 | 1931 | ||
990 | rdev->accel_working = true; |
1932 | rdev->accel_working = true; |
991 | r = rv770_startup(rdev); |
1933 | r = rv770_startup(rdev); |
992 | if (r) { |
1934 | if (r) { |
993 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1935 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
994 | rv770_pcie_gart_fini(rdev); |
1936 | rv770_pcie_gart_fini(rdev); |
995 | rdev->accel_working = false; |
1937 | rdev->accel_working = false; |
996 | } |
1938 | } |
997 | 1939 | ||
998 | return 0; |
1940 | return 0; |
999 | } |
1941 | } |
1000 | 1942 | ||
1001 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) |
1943 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) |
1002 | { |
1944 | { |
1003 | u32 link_width_cntl, lanes, speed_cntl, tmp; |
1945 | u32 link_width_cntl, lanes, speed_cntl, tmp; |
1004 | u16 link_cntl2; |
1946 | u16 link_cntl2; |
1005 | u32 mask; |
- | |
1006 | int ret; |
- | |
1007 | 1947 | ||
1008 | if (radeon_pcie_gen2 == 0) |
1948 | if (radeon_pcie_gen2 == 0) |
1009 | return; |
1949 | return; |
1010 | 1950 | ||
1011 | if (rdev->flags & RADEON_IS_IGP) |
1951 | if (rdev->flags & RADEON_IS_IGP) |
1012 | return; |
1952 | return; |
1013 | 1953 | ||
1014 | if (!(rdev->flags & RADEON_IS_PCIE)) |
1954 | if (!(rdev->flags & RADEON_IS_PCIE)) |
1015 | return; |
1955 | return; |
1016 | 1956 | ||
1017 | /* x2 cards have a special sequence */ |
1957 | /* x2 cards have a special sequence */ |
1018 | if (ASIC_IS_X2(rdev)) |
1958 | if (ASIC_IS_X2(rdev)) |
1019 | return; |
1959 | return; |
1020 | 1960 | ||
1021 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
- | |
1022 | if (ret != 0) |
- | |
1023 | return; |
- | |
1024 | 1961 | if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && |
|
1025 | if (!(mask & DRM_PCIE_SPEED_50)) |
1962 | (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) |
1026 | return; |
1963 | return; |
1027 | 1964 | ||
1028 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
1965 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
1029 | 1966 | ||
1030 | /* advertise upconfig capability */ |
1967 | /* advertise upconfig capability */ |
1031 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
1968 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
1032 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
1969 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
1033 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
1970 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
1034 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
1971 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
1035 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
1972 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
1036 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
1973 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
1037 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
1974 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
1038 | LC_RECONFIG_ARC_MISSING_ESCAPE); |
1975 | LC_RECONFIG_ARC_MISSING_ESCAPE); |
1039 | link_width_cntl |= lanes | LC_RECONFIG_NOW | |
1976 | link_width_cntl |= lanes | LC_RECONFIG_NOW | |
1040 | LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; |
1977 | LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; |
1041 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
1978 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
1042 | } else { |
1979 | } else { |
1043 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
1980 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
1044 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
1981 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
1045 | } |
1982 | } |
1046 | 1983 | ||
1047 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
1984 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
1048 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
1985 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
1049 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
1986 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
1050 | 1987 | ||
1051 | tmp = RREG32(0x541c); |
1988 | tmp = RREG32(0x541c); |
1052 | WREG32(0x541c, tmp | 0x8); |
1989 | WREG32(0x541c, tmp | 0x8); |
1053 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); |
1990 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); |
1054 | link_cntl2 = RREG16(0x4088); |
1991 | link_cntl2 = RREG16(0x4088); |
1055 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; |
1992 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; |
1056 | link_cntl2 |= 0x2; |
1993 | link_cntl2 |= 0x2; |
1057 | WREG16(0x4088, link_cntl2); |
1994 | WREG16(0x4088, link_cntl2); |
1058 | WREG32(MM_CFGREGS_CNTL, 0); |
1995 | WREG32(MM_CFGREGS_CNTL, 0); |
1059 | 1996 | ||
1060 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
1997 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
1061 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
1998 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
1062 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
1999 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
1063 | 2000 | ||
1064 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
2001 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
1065 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; |
2002 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; |
1066 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
2003 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
1067 | 2004 | ||
1068 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
2005 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
1069 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; |
2006 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; |
1070 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
2007 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
1071 | 2008 | ||
1072 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
2009 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
1073 | speed_cntl |= LC_GEN2_EN_STRAP; |
2010 | speed_cntl |= LC_GEN2_EN_STRAP; |
1074 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
2011 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
1075 | 2012 | ||
1076 | } else { |
2013 | } else { |
1077 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
2014 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
1078 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
2015 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
1079 | if (1) |
2016 | if (1) |
1080 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
2017 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
1081 | else |
2018 | else |
1082 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
2019 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
1083 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
2020 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
1084 | } |
2021 | } |
1085 | }><>><>>>>=><=>>>>>><>><>>>>>> |
2022 | }>><>><>><>>>>=><=>>>>>><>><>>>>>>>->-> |