Subversion Repositories Kolibri OS

Rev

Rev 2997 | Rev 3764 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 2997 Rev 3192
Line 237... Line 237...
237
void r700_cp_stop(struct radeon_device *rdev)
237
void r700_cp_stop(struct radeon_device *rdev)
238
{
238
{
239
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
239
//   radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
240
	WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
240
	WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
241
	WREG32(SCRATCH_UMSK, 0);
241
	WREG32(SCRATCH_UMSK, 0);
-
 
242
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
242
}
243
}
Line 243... Line 244...
243
 
244
 
244
static int rv770_cp_load_microcode(struct radeon_device *rdev)
245
static int rv770_cp_load_microcode(struct radeon_device *rdev)
245
{
246
{
Line 497... Line 498...
497
	rdev->config.rv770.tile_config = gb_tiling_config;
498
	rdev->config.rv770.tile_config = gb_tiling_config;
Line 498... Line 499...
498
 
499
 
499
	WREG32(GB_TILING_CONFIG, gb_tiling_config);
500
	WREG32(GB_TILING_CONFIG, gb_tiling_config);
500
	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
501
	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
-
 
502
	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
-
 
503
	WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
Line 501... Line 504...
501
	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
504
	WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
502
 
505
 
503
	WREG32(CGTS_SYS_TCC_DISABLE, 0);
506
	WREG32(CGTS_SYS_TCC_DISABLE, 0);
504
	WREG32(CGTS_TCC_DISABLE, 0);
507
	WREG32(CGTS_TCC_DISABLE, 0);
Line 800... Line 803...
800
	return 0;
803
	return 0;
801
}
804
}
Line 802... Line 805...
802
 
805
 
803
static int rv770_startup(struct radeon_device *rdev)
806
static int rv770_startup(struct radeon_device *rdev)
804
{
807
{
805
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
808
	struct radeon_ring *ring;
Line 806... Line 809...
806
	int r;
809
	int r;
807
 
810
 
Line 847... Line 850...
847
	/* allocate wb buffer */
850
	/* allocate wb buffer */
848
	r = radeon_wb_init(rdev);
851
	r = radeon_wb_init(rdev);
849
	if (r)
852
	if (r)
850
		return r;
853
		return r;
Line -... Line 854...
-
 
854
 
-
 
855
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
-
 
856
	if (r) {
-
 
857
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
-
 
858
		return r;
-
 
859
	}
-
 
860
 
-
 
861
	r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
-
 
862
	if (r) {
-
 
863
		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
-
 
864
		return r;
-
 
865
	}
851
 
866
 
852
	/* Enable IRQ */
867
	/* Enable IRQ */
853
	r = r600_irq_init(rdev);
868
	r = r600_irq_init(rdev);
854
	if (r) {
869
	if (r) {
855
		DRM_ERROR("radeon: IH init failed (%d).\n", r);
870
		DRM_ERROR("radeon: IH init failed (%d).\n", r);
856
//		radeon_irq_kms_fini(rdev);
871
//		radeon_irq_kms_fini(rdev);
857
		return r;
872
		return r;
858
	}
873
	}
Line -... Line 874...
-
 
874
	r600_irq_set(rdev);
859
	r600_irq_set(rdev);
875
 
860
 
876
	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
861
	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
877
	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
862
			     R600_CP_RB_RPTR, R600_CP_RB_WPTR,
878
			     R600_CP_RB_RPTR, R600_CP_RB_WPTR,
863
			     0, 0xfffff, RADEON_CP_PACKET2);
879
			     0, 0xfffff, RADEON_CP_PACKET2);
-
 
880
	if (r)
-
 
881
		return r;
-
 
882
 
-
 
883
	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
-
 
884
	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-
 
885
			     DMA_RB_RPTR, DMA_RB_WPTR,
-
 
886
			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
-
 
887
	if (r)
864
	if (r)
888
		return r;
865
		return r;
889
 
866
	r = rv770_cp_load_microcode(rdev);
890
	r = rv770_cp_load_microcode(rdev);
867
	if (r)
891
	if (r)
868
		return r;
892
		return r;
869
	r = r600_cp_resume(rdev);
893
	r = r600_cp_resume(rdev);
Line -... Line 894...
-
 
894
	if (r)
-
 
895
		return r;
-
 
896
 
-
 
897
	r = r600_dma_resume(rdev);
870
	if (r)
898
	if (r)
871
		return r;
899
		return r;
872
 
900
 
873
	r = radeon_ib_pool_init(rdev);
901
	r = radeon_ib_pool_init(rdev);
874
	if (r) {
902
	if (r) {
Line 947... Line 975...
947
		return r;
975
		return r;
Line 948... Line 976...
948
 
976
 
949
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
977
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
Line -... Line 978...
-
 
978
	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
-
 
979
 
-
 
980
	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
950
	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
981
	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
951
 
982
 
Line 952... Line 983...
952
	rdev->ih.ring_obj = NULL;
983
	rdev->ih.ring_obj = NULL;
953
	r600_ih_ring_init(rdev, 64 * 1024);
984
	r600_ih_ring_init(rdev, 64 * 1024);