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23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | //#include |
28 | #include |
29 | //#include |
29 | //#include |
30 | #include "drmP.h" |
30 | #include "drmP.h" |
31 | #include "radeon.h" |
31 | #include "radeon.h" |
32 | #include "radeon_drm.h" |
32 | #include "radeon_drm.h" |
33 | #include "rv770d.h" |
33 | #include "rv770d.h" |
Line 232... | Line 232... | ||
232 | void r700_cp_stop(struct radeon_device *rdev) |
232 | void r700_cp_stop(struct radeon_device *rdev) |
233 | { |
233 | { |
234 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
234 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
235 | } |
235 | } |
Line 236... | Line 236... | ||
236 | 236 | ||
237 | #if 0 |
237 | |
238 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
238 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
239 | { |
239 | { |
240 | const __be32 *fw_data; |
240 | const __be32 *fw_data; |
Line 267... | Line 267... | ||
267 | WREG32(CP_ME_RAM_WADDR, 0); |
267 | WREG32(CP_ME_RAM_WADDR, 0); |
268 | WREG32(CP_ME_RAM_RADDR, 0); |
268 | WREG32(CP_ME_RAM_RADDR, 0); |
269 | return 0; |
269 | return 0; |
270 | } |
270 | } |
Line 271... | Line -... | ||
271 | - | ||
Line 272... | Line 271... | ||
272 | #endif |
271 | |
273 | 272 | ||
274 | /* |
273 | /* |
275 | * Core functions |
274 | * Core functions |
Line 869... | Line 868... | ||
869 | 868 | ||
870 | static int rv770_startup(struct radeon_device *rdev) |
869 | static int rv770_startup(struct radeon_device *rdev) |
871 | { |
870 | { |
Line -... | Line 871... | ||
- | 871 | int r; |
|
- | 872 | ||
- | 873 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
|
- | 874 | r = r600_init_microcode(rdev); |
|
- | 875 | if (r) { |
|
- | 876 | DRM_ERROR("Failed to load firmware!\n"); |
|
- | 877 | return r; |
|
- | 878 | } |
|
872 | int r; |
879 | } |
873 | 880 | ||
874 | rv770_mc_program(rdev); |
881 | rv770_mc_program(rdev); |
875 | if (rdev->flags & RADEON_IS_AGP) { |
882 | if (rdev->flags & RADEON_IS_AGP) { |
876 | rv770_agp_enable(rdev); |
883 | rv770_agp_enable(rdev); |
877 | } else { |
884 | } else { |
878 | r = rv770_pcie_gart_enable(rdev); |
885 | r = rv770_pcie_gart_enable(rdev); |
879 | if (r) |
886 | if (r) |
880 | return r; |
887 | return r; |
881 | } |
- | |
882 | rv770_gpu_init(rdev); |
- | |
883 | - | ||
884 | - | ||
885 | // r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
- | |
886 | // &rdev->r600_blit.shader_gpu_addr); |
- | |
887 | // if (r) { |
- | |
888 | // DRM_ERROR("failed to pin blit object %d\n", r); |
- | |
889 | // return r; |
- | |
890 | // } |
888 | } |
891 | 889 | rv770_gpu_init(rdev); |
|
892 | // r = radeon_ring_init(rdev, rdev->cp.ring_size); |
890 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
893 | // if (r) |
891 | if (r) |
894 | // return r; |
892 | return r; |
895 | // r = rv770_cp_load_microcode(rdev); |
893 | r = rv770_cp_load_microcode(rdev); |
896 | // if (r) |
894 | if (r) |
897 | // return r; |
895 | return r; |
898 | // r = r600_cp_resume(rdev); |
896 | r = r600_cp_resume(rdev); |
899 | // if (r) |
897 | if (r) |
900 | // return r; |
898 | return r; |
901 | /* write back buffer are not vital so don't worry about failure */ |
899 | /* write back buffer are not vital so don't worry about failure */ |
902 | // r600_wb_enable(rdev); |
900 | // r600_wb_enable(rdev); |
Line -... | Line 901... | ||
- | 901 | return 0; |
|
- | 902 | } |
|
- | 903 | ||
- | 904 | ||
- | 905 | ||
903 | return 0; |
906 | |
904 | } |
907 | |
905 | 908 | ||
906 | 909 | ||
907 | /* Plan is to move initialization in that function and use |
910 | /* Plan is to move initialization in that function and use |
Line 969... | Line 972... | ||
969 | /* Memory manager */ |
972 | /* Memory manager */ |
970 | r = radeon_bo_init(rdev); |
973 | r = radeon_bo_init(rdev); |
971 | if (r) |
974 | if (r) |
972 | return r; |
975 | return r; |
Line -... | Line 976... | ||
- | 976 | ||
973 | 977 | ||
974 | // if (!rdev->me_fw || !rdev->pfp_fw) { |
978 | rdev->cp.ring_obj = NULL; |
975 | // r = r600_cp_init_microcode(rdev); |
- | |
976 | // if (r) { |
- | |
977 | // DRM_ERROR("Failed to load firmware!\n"); |
- | |
978 | // return r; |
- | |
979 | // } |
979 | r600_ring_init(rdev, 1024 * 1024); |
Line 980... | Line 980... | ||
980 | // } |
980 | |
981 | 981 | ||
982 | r = r600_pcie_gart_init(rdev); |
982 | r = r600_pcie_gart_init(rdev); |
Line 983... | Line 983... | ||
983 | if (r) |
983 | if (r) |
984 | return r; |
- | |
985 | - | ||
986 | rdev->accel_working = true; |
- | |
987 | // r = r600_blit_init(rdev); |
- | |
988 | // if (r) { |
- | |
989 | // DRM_ERROR("radeon: failled blitter (%d).\n", r); |
- | |
990 | // rdev->accel_working = false; |
984 | return r; |
991 | // } |
985 | |
992 | - | ||
993 | r = rv770_startup(rdev); |
- | |
994 | if (r) { |
986 | rdev->accel_working = true; |
- | 987 | r = rv770_startup(rdev); |
|
995 | // rv770_suspend(rdev); |
988 | if (r) { |
996 | // r600_wb_fini(rdev); |
989 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
997 | // radeon_ring_fini(rdev); |
990 | |
998 | rv770_pcie_gart_fini(rdev); |
991 | rv770_pcie_gart_fini(rdev); |
999 | rdev->accel_working = false; |
992 | rdev->accel_working = false; |