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Rev 1403 Rev 1404
Line 111... Line 111...
111 
	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 111 
	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
112 
	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 112 
	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
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	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 113 
	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
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	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 114 
	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
115 
	if (rdev->gart.table.vram.robj) {
 115 
	if (rdev->gart.table.vram.robj) {
- 
 
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		r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
- 
 
 117 
		if (likely(r == 0)) {
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//       radeon_object_kunmap(rdev->gart.table.vram.robj);
 118 
			radeon_bo_kunmap(rdev->gart.table.vram.robj);
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//       radeon_object_unpin(rdev->gart.table.vram.robj);
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			radeon_bo_unpin(rdev->gart.table.vram.robj);
- 
 
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			radeon_bo_unreserve(rdev->gart.table.vram.robj);
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		}
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	}
 122 
	}
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}
 123 
}
Line 120... Line 124...
120 
 
 124 
 
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void rv770_pcie_gart_fini(struct radeon_device *rdev)
 125 
void rv770_pcie_gart_fini(struct radeon_device *rdev)
122 
{
 126 
{
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	rv770_pcie_gart_disable(rdev);
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	rv770_pcie_gart_disable(rdev);
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//   radeon_gart_table_vram_free(rdev);
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	radeon_gart_table_vram_free(rdev);
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    radeon_gart_fini(rdev);
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    radeon_gart_fini(rdev);
Line 126... Line 130...
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}
 130 
}
Line 875... Line 879...
875 
		if (r)
 879 
		if (r)
876 
			return r;
 880 
			return r;
877 
	}
 881 
	}
878 
	rv770_gpu_init(rdev);
 882 
	rv770_gpu_init(rdev);
Line -... Line 883...
- 
 
 883 
 
879 
 
 884 
 
880 
//  r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 885 
//  r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
881 
//                 &rdev->r600_blit.shader_gpu_addr);
 886 
//                 &rdev->r600_blit.shader_gpu_addr);
882 
//   if (r) {
 887 
//   if (r) {
883 
//       DRM_ERROR("failed to pin blit object %d\n", r);
 888 
//       DRM_ERROR("failed to pin blit object %d\n", r);