Rev 3764 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 3764 | Rev 5078 | ||
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Line 122... | Line 122... | ||
122 | radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
122 | radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
123 | radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); |
123 | radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); |
124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
126 | radeon_ring_write(ring, 0); |
126 | radeon_ring_write(ring, 0); |
127 | radeon_ring_unlock_commit(rdev, ring); |
127 | radeon_ring_unlock_commit(rdev, ring, false); |
128 | } |
128 | } |
Line 129... | Line 129... | ||
129 | 129 | ||
130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
131 | { |
131 | { |
Line 207... | Line 207... | ||
207 | radeon_update_bandwidth_info(rdev); |
207 | radeon_update_bandwidth_info(rdev); |
208 | } |
208 | } |
Line 209... | Line 209... | ||
209 | 209 | ||
210 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
210 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
- | 211 | { |
|
211 | { |
212 | unsigned long flags; |
Line -... | Line 213... | ||
- | 213 | uint32_t r; |
|
212 | uint32_t r; |
214 | |
213 | 215 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
|
214 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
216 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
- | 217 | r = RREG32(MC_IND_DATA); |
|
- | 218 | WREG32(MC_IND_INDEX, 0); |
|
215 | r = RREG32(MC_IND_DATA); |
219 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
216 | WREG32(MC_IND_INDEX, 0); |
220 | |
Line 217... | Line 221... | ||
217 | return r; |
221 | return r; |
218 | } |
222 | } |
- | 223 | ||
- | 224 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
|
- | 225 | { |
|
219 | 226 | unsigned long flags; |
|
220 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
227 | |
221 | { |
228 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
- | 229 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
|
222 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
230 | WREG32(MC_IND_DATA, (v)); |
Line 223... | Line 231... | ||
223 | WREG32(MC_IND_DATA, (v)); |
231 | WREG32(MC_IND_INDEX, 0); |
224 | WREG32(MC_IND_INDEX, 0); |
232 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
225 | } |
233 | } |
Line 396... | Line 404... | ||
396 | 404 | ||
397 | /* unlock regs and wait for update */ |
405 | /* unlock regs and wait for update */ |
398 | for (i = 0; i < rdev->num_crtc; i++) { |
406 | for (i = 0; i < rdev->num_crtc; i++) { |
399 | if (save->crtc_enabled[i]) { |
407 | if (save->crtc_enabled[i]) { |
400 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); |
408 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); |
401 | if ((tmp & 0x3) != 0) { |
409 | if ((tmp & 0x7) != 3) { |
- | 410 | tmp &= ~0x7; |
|
402 | tmp &= ~0x3; |
411 | tmp |= 0x3; |
403 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); |
412 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); |
404 | } |
413 | } |
405 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
414 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
406 | if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { |
415 | if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { |
Line 620... | Line 629... | ||
620 | r = rv370_pcie_gart_init(rdev); |
629 | r = rv370_pcie_gart_init(rdev); |
621 | if (r) |
630 | if (r) |
622 | return r; |
631 | return r; |
623 | rv515_set_safe_registers(rdev); |
632 | rv515_set_safe_registers(rdev); |
Line -... | Line 633... | ||
- | 633 | ||
- | 634 | /* Initialize power management */ |
|
- | 635 | radeon_pm_init(rdev); |
|
624 | 636 | ||
625 | rdev->accel_working = true; |
637 | rdev->accel_working = true; |
626 | r = rv515_startup(rdev); |
638 | r = rv515_startup(rdev); |
627 | if (r) { |
639 | if (r) { |
628 | /* Somethings want wront with the accel init stop accel */ |
640 | /* Somethings want wront with the accel init stop accel */ |
Line 875... | Line 887... | ||
875 | fixed20_12 sclk; |
887 | fixed20_12 sclk; |
876 | }; |
888 | }; |
Line 877... | Line 889... | ||
877 | 889 | ||
878 | static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
890 | static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
879 | struct radeon_crtc *crtc, |
891 | struct radeon_crtc *crtc, |
- | 892 | struct rv515_watermark *wm, |
|
880 | struct rv515_watermark *wm) |
893 | bool low) |
881 | { |
894 | { |
882 | struct drm_display_mode *mode = &crtc->base.mode; |
895 | struct drm_display_mode *mode = &crtc->base.mode; |
883 | fixed20_12 a, b, c; |
896 | fixed20_12 a, b, c; |
884 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
897 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
- | 898 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
|
- | 899 | fixed20_12 sclk; |
|
Line 885... | Line 900... | ||
885 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
900 | u32 selected_sclk; |
886 | 901 | ||
887 | if (!crtc->base.enabled) { |
902 | if (!crtc->base.enabled) { |
888 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
903 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
889 | wm->lb_request_fifo_depth = 4; |
904 | wm->lb_request_fifo_depth = 4; |
Line -... | Line 905... | ||
- | 905 | return; |
|
- | 906 | } |
|
- | 907 | ||
- | 908 | /* rv6xx, rv7xx */ |
|
- | 909 | if ((rdev->family >= CHIP_RV610) && |
|
- | 910 | (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) |
|
- | 911 | selected_sclk = radeon_dpm_get_sclk(rdev, low); |
|
- | 912 | else |
|
- | 913 | selected_sclk = rdev->pm.current_sclk; |
|
- | 914 | ||
- | 915 | /* sclk in Mhz */ |
|
- | 916 | a.full = dfixed_const(100); |
|
890 | return; |
917 | sclk.full = dfixed_const(selected_sclk); |
891 | } |
918 | sclk.full = dfixed_div(sclk, a); |
892 | 919 | ||
893 | if (crtc->vsc.full > dfixed_const(2)) |
920 | if (crtc->vsc.full > dfixed_const(2)) |
Line 953... | Line 980... | ||
953 | * ChunkTime = the time it takes the DCP to send one chunk of data |
980 | * ChunkTime = the time it takes the DCP to send one chunk of data |
954 | * to the LB which consists of pipeline delay and inter chunk gap |
981 | * to the LB which consists of pipeline delay and inter chunk gap |
955 | * sclk = system clock(Mhz) |
982 | * sclk = system clock(Mhz) |
956 | */ |
983 | */ |
957 | a.full = dfixed_const(600 * 1000); |
984 | a.full = dfixed_const(600 * 1000); |
958 | chunk_time.full = dfixed_div(a, rdev->pm.sclk); |
985 | chunk_time.full = dfixed_div(a, sclk); |
959 | read_delay_latency.full = dfixed_const(1000); |
986 | read_delay_latency.full = dfixed_const(1000); |
Line 960... | Line 987... | ||
960 | 987 | ||
961 | /* Determine the worst case latency |
988 | /* Determine the worst case latency |
962 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
989 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
Line 1014... | Line 1041... | ||
1014 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
1041 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
1015 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
1042 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
1016 | } |
1043 | } |
1017 | } |
1044 | } |
Line 1018... | Line 1045... | ||
1018 | 1045 | ||
- | 1046 | static void rv515_compute_mode_priority(struct radeon_device *rdev, |
|
- | 1047 | struct rv515_watermark *wm0, |
|
- | 1048 | struct rv515_watermark *wm1, |
|
- | 1049 | struct drm_display_mode *mode0, |
|
- | 1050 | struct drm_display_mode *mode1, |
|
- | 1051 | u32 *d1mode_priority_a_cnt, |
|
1019 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
1052 | u32 *d2mode_priority_a_cnt) |
1020 | { |
- | |
1021 | struct drm_display_mode *mode0 = NULL; |
- | |
1022 | struct drm_display_mode *mode1 = NULL; |
- | |
1023 | struct rv515_watermark wm0; |
- | |
1024 | struct rv515_watermark wm1; |
- | |
1025 | u32 tmp; |
- | |
1026 | u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; |
- | |
1027 | u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; |
1053 | { |
1028 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
1054 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
Line 1029... | Line -... | ||
1029 | fixed20_12 a, b; |
- | |
1030 | 1055 | fixed20_12 a, b; |
|
1031 | if (rdev->mode_info.crtcs[0]->base.enabled) |
- | |
1032 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
1056 | |
1033 | if (rdev->mode_info.crtcs[1]->base.enabled) |
- | |
1034 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
- | |
1035 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
- | |
1036 | - | ||
1037 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
- | |
1038 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
- | |
1039 | - | ||
1040 | tmp = wm0.lb_request_fifo_depth; |
- | |
Line 1041... | Line 1057... | ||
1041 | tmp |= wm1.lb_request_fifo_depth << 16; |
1057 | *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; |
1042 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
1058 | *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; |
1043 | 1059 | ||
1044 | if (mode0 && mode1) { |
1060 | if (mode0 && mode1) { |
1045 | if (dfixed_trunc(wm0.dbpp) > 64) |
1061 | if (dfixed_trunc(wm0->dbpp) > 64) |
1046 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
1062 | a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); |
1047 | else |
1063 | else |
1048 | a.full = wm0.num_line_pair.full; |
1064 | a.full = wm0->num_line_pair.full; |
1049 | if (dfixed_trunc(wm1.dbpp) > 64) |
1065 | if (dfixed_trunc(wm1->dbpp) > 64) |
1050 | b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
1066 | b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); |
1051 | else |
1067 | else |
1052 | b.full = wm1.num_line_pair.full; |
1068 | b.full = wm1->num_line_pair.full; |
1053 | a.full += b.full; |
1069 | a.full += b.full; |
1054 | fill_rate.full = dfixed_div(wm0.sclk, a); |
1070 | fill_rate.full = dfixed_div(wm0->sclk, a); |
1055 | if (wm0.consumption_rate.full > fill_rate.full) { |
1071 | if (wm0->consumption_rate.full > fill_rate.full) { |
1056 | b.full = wm0.consumption_rate.full - fill_rate.full; |
1072 | b.full = wm0->consumption_rate.full - fill_rate.full; |
1057 | b.full = dfixed_mul(b, wm0.active_time); |
1073 | b.full = dfixed_mul(b, wm0->active_time); |
1058 | a.full = dfixed_const(16); |
1074 | a.full = dfixed_const(16); |
1059 | b.full = dfixed_div(b, a); |
1075 | b.full = dfixed_div(b, a); |
1060 | a.full = dfixed_mul(wm0.worst_case_latency, |
1076 | a.full = dfixed_mul(wm0->worst_case_latency, |
1061 | wm0.consumption_rate); |
1077 | wm0->consumption_rate); |
1062 | priority_mark02.full = a.full + b.full; |
1078 | priority_mark02.full = a.full + b.full; |
1063 | } else { |
1079 | } else { |
1064 | a.full = dfixed_mul(wm0.worst_case_latency, |
1080 | a.full = dfixed_mul(wm0->worst_case_latency, |
1065 | wm0.consumption_rate); |
1081 | wm0->consumption_rate); |
1066 | b.full = dfixed_const(16 * 1000); |
1082 | b.full = dfixed_const(16 * 1000); |
1067 | priority_mark02.full = dfixed_div(a, b); |
1083 | priority_mark02.full = dfixed_div(a, b); |
1068 | } |
1084 | } |
1069 | if (wm1.consumption_rate.full > fill_rate.full) { |
1085 | if (wm1->consumption_rate.full > fill_rate.full) { |
1070 | b.full = wm1.consumption_rate.full - fill_rate.full; |
1086 | b.full = wm1->consumption_rate.full - fill_rate.full; |
1071 | b.full = dfixed_mul(b, wm1.active_time); |
1087 | b.full = dfixed_mul(b, wm1->active_time); |
1072 | a.full = dfixed_const(16); |
1088 | a.full = dfixed_const(16); |
1073 | b.full = dfixed_div(b, a); |
1089 | b.full = dfixed_div(b, a); |
1074 | a.full = dfixed_mul(wm1.worst_case_latency, |
1090 | a.full = dfixed_mul(wm1->worst_case_latency, |
1075 | wm1.consumption_rate); |
1091 | wm1->consumption_rate); |
1076 | priority_mark12.full = a.full + b.full; |
1092 | priority_mark12.full = a.full + b.full; |
1077 | } else { |
1093 | } else { |
1078 | a.full = dfixed_mul(wm1.worst_case_latency, |
1094 | a.full = dfixed_mul(wm1->worst_case_latency, |
1079 | wm1.consumption_rate); |
1095 | wm1->consumption_rate); |
1080 | b.full = dfixed_const(16 * 1000); |
1096 | b.full = dfixed_const(16 * 1000); |
1081 | priority_mark12.full = dfixed_div(a, b); |
1097 | priority_mark12.full = dfixed_div(a, b); |
1082 | } |
- | |
1083 | if (wm0.priority_mark.full > priority_mark02.full) |
- | |
1084 | priority_mark02.full = wm0.priority_mark.full; |
1098 | } |
1085 | if (dfixed_trunc(priority_mark02) < 0) |
1099 | if (wm0->priority_mark.full > priority_mark02.full) |
1086 | priority_mark02.full = 0; |
1100 | priority_mark02.full = wm0->priority_mark.full; |
1087 | if (wm0.priority_mark_max.full > priority_mark02.full) |
1101 | if (wm0->priority_mark_max.full > priority_mark02.full) |
1088 | priority_mark02.full = wm0.priority_mark_max.full; |
- | |
1089 | if (wm1.priority_mark.full > priority_mark12.full) |
- | |
1090 | priority_mark12.full = wm1.priority_mark.full; |
1102 | priority_mark02.full = wm0->priority_mark_max.full; |
1091 | if (dfixed_trunc(priority_mark12) < 0) |
1103 | if (wm1->priority_mark.full > priority_mark12.full) |
1092 | priority_mark12.full = 0; |
1104 | priority_mark12.full = wm1->priority_mark.full; |
1093 | if (wm1.priority_mark_max.full > priority_mark12.full) |
1105 | if (wm1->priority_mark_max.full > priority_mark12.full) |
1094 | priority_mark12.full = wm1.priority_mark_max.full; |
1106 | priority_mark12.full = wm1->priority_mark_max.full; |
1095 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1107 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1096 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1108 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1097 | if (rdev->disp_priority == 2) { |
1109 | if (rdev->disp_priority == 2) { |
1098 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1110 | *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1099 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1111 | *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1100 | } |
1112 | } |
1101 | } else if (mode0) { |
1113 | } else if (mode0) { |
1102 | if (dfixed_trunc(wm0.dbpp) > 64) |
1114 | if (dfixed_trunc(wm0->dbpp) > 64) |
1103 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
1115 | a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); |
1104 | else |
1116 | else |
1105 | a.full = wm0.num_line_pair.full; |
1117 | a.full = wm0->num_line_pair.full; |
1106 | fill_rate.full = dfixed_div(wm0.sclk, a); |
1118 | fill_rate.full = dfixed_div(wm0->sclk, a); |
1107 | if (wm0.consumption_rate.full > fill_rate.full) { |
1119 | if (wm0->consumption_rate.full > fill_rate.full) { |
1108 | b.full = wm0.consumption_rate.full - fill_rate.full; |
1120 | b.full = wm0->consumption_rate.full - fill_rate.full; |
1109 | b.full = dfixed_mul(b, wm0.active_time); |
1121 | b.full = dfixed_mul(b, wm0->active_time); |
1110 | a.full = dfixed_const(16); |
1122 | a.full = dfixed_const(16); |
1111 | b.full = dfixed_div(b, a); |
1123 | b.full = dfixed_div(b, a); |
1112 | a.full = dfixed_mul(wm0.worst_case_latency, |
1124 | a.full = dfixed_mul(wm0->worst_case_latency, |
1113 | wm0.consumption_rate); |
1125 | wm0->consumption_rate); |
1114 | priority_mark02.full = a.full + b.full; |
1126 | priority_mark02.full = a.full + b.full; |
1115 | } else { |
1127 | } else { |
1116 | a.full = dfixed_mul(wm0.worst_case_latency, |
1128 | a.full = dfixed_mul(wm0->worst_case_latency, |
1117 | wm0.consumption_rate); |
1129 | wm0->consumption_rate); |
1118 | b.full = dfixed_const(16); |
1130 | b.full = dfixed_const(16); |
1119 | priority_mark02.full = dfixed_div(a, b); |
1131 | priority_mark02.full = dfixed_div(a, b); |
1120 | } |
- | |
1121 | if (wm0.priority_mark.full > priority_mark02.full) |
- | |
1122 | priority_mark02.full = wm0.priority_mark.full; |
1132 | } |
1123 | if (dfixed_trunc(priority_mark02) < 0) |
1133 | if (wm0->priority_mark.full > priority_mark02.full) |
1124 | priority_mark02.full = 0; |
1134 | priority_mark02.full = wm0->priority_mark.full; |
1125 | if (wm0.priority_mark_max.full > priority_mark02.full) |
1135 | if (wm0->priority_mark_max.full > priority_mark02.full) |
1126 | priority_mark02.full = wm0.priority_mark_max.full; |
1136 | priority_mark02.full = wm0->priority_mark_max.full; |
1127 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1137 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1128 | if (rdev->disp_priority == 2) |
1138 | if (rdev->disp_priority == 2) |
1129 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1139 | *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1130 | } else if (mode1) { |
1140 | } else if (mode1) { |
1131 | if (dfixed_trunc(wm1.dbpp) > 64) |
1141 | if (dfixed_trunc(wm1->dbpp) > 64) |
1132 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
1142 | a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); |
1133 | else |
1143 | else |
1134 | a.full = wm1.num_line_pair.full; |
1144 | a.full = wm1->num_line_pair.full; |
1135 | fill_rate.full = dfixed_div(wm1.sclk, a); |
1145 | fill_rate.full = dfixed_div(wm1->sclk, a); |
1136 | if (wm1.consumption_rate.full > fill_rate.full) { |
1146 | if (wm1->consumption_rate.full > fill_rate.full) { |
1137 | b.full = wm1.consumption_rate.full - fill_rate.full; |
1147 | b.full = wm1->consumption_rate.full - fill_rate.full; |
1138 | b.full = dfixed_mul(b, wm1.active_time); |
1148 | b.full = dfixed_mul(b, wm1->active_time); |
1139 | a.full = dfixed_const(16); |
1149 | a.full = dfixed_const(16); |
1140 | b.full = dfixed_div(b, a); |
1150 | b.full = dfixed_div(b, a); |
1141 | a.full = dfixed_mul(wm1.worst_case_latency, |
1151 | a.full = dfixed_mul(wm1->worst_case_latency, |
1142 | wm1.consumption_rate); |
1152 | wm1->consumption_rate); |
1143 | priority_mark12.full = a.full + b.full; |
1153 | priority_mark12.full = a.full + b.full; |
1144 | } else { |
1154 | } else { |
1145 | a.full = dfixed_mul(wm1.worst_case_latency, |
1155 | a.full = dfixed_mul(wm1->worst_case_latency, |
1146 | wm1.consumption_rate); |
1156 | wm1->consumption_rate); |
1147 | b.full = dfixed_const(16 * 1000); |
1157 | b.full = dfixed_const(16 * 1000); |
1148 | priority_mark12.full = dfixed_div(a, b); |
1158 | priority_mark12.full = dfixed_div(a, b); |
1149 | } |
- | |
1150 | if (wm1.priority_mark.full > priority_mark12.full) |
- | |
1151 | priority_mark12.full = wm1.priority_mark.full; |
1159 | } |
1152 | if (dfixed_trunc(priority_mark12) < 0) |
1160 | if (wm1->priority_mark.full > priority_mark12.full) |
1153 | priority_mark12.full = 0; |
1161 | priority_mark12.full = wm1->priority_mark.full; |
1154 | if (wm1.priority_mark_max.full > priority_mark12.full) |
1162 | if (wm1->priority_mark_max.full > priority_mark12.full) |
1155 | priority_mark12.full = wm1.priority_mark_max.full; |
1163 | priority_mark12.full = wm1->priority_mark_max.full; |
1156 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1164 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
- | 1165 | if (rdev->disp_priority == 2) |
|
- | 1166 | *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
|
- | 1167 | } |
|
- | 1168 | } |
|
- | 1169 | ||
- | 1170 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
|
- | 1171 | { |
|
- | 1172 | struct drm_display_mode *mode0 = NULL; |
|
- | 1173 | struct drm_display_mode *mode1 = NULL; |
|
- | 1174 | struct rv515_watermark wm0_high, wm0_low; |
|
- | 1175 | struct rv515_watermark wm1_high, wm1_low; |
|
- | 1176 | u32 tmp; |
|
- | 1177 | u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; |
|
- | 1178 | u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; |
|
- | 1179 | ||
- | 1180 | if (rdev->mode_info.crtcs[0]->base.enabled) |
|
- | 1181 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
|
- | 1182 | if (rdev->mode_info.crtcs[1]->base.enabled) |
|
- | 1183 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
|
- | 1184 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
|
- | 1185 | ||
- | 1186 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); |
|
- | 1187 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); |
|
- | 1188 | ||
- | 1189 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); |
|
- | 1190 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); |
|
- | 1191 | ||
- | 1192 | tmp = wm0_high.lb_request_fifo_depth; |
|
- | 1193 | tmp |= wm1_high.lb_request_fifo_depth << 16; |
|
- | 1194 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
|
- | 1195 | ||
- | 1196 | rv515_compute_mode_priority(rdev, |
|
- | 1197 | &wm0_high, &wm1_high, |
|
- | 1198 | mode0, mode1, |
|
- | 1199 | &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); |
|
- | 1200 | rv515_compute_mode_priority(rdev, |
|
Line 1157... | Line 1201... | ||
1157 | if (rdev->disp_priority == 2) |
1201 | &wm0_low, &wm1_low, |
1158 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1202 | mode0, mode1, |
1159 | } |
1203 | &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); |
1160 | 1204 | ||
1161 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
1205 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
Line 1162... | Line 1206... | ||
1162 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
1206 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); |
1163 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
1207 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
1164 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
1208 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); |