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Rev 3192 Rev 3764
Line 301... Line 301...
301 
		if (crtc_enabled) {
 301 
		if (crtc_enabled) {
302 
			save->crtc_enabled[i] = true;
 302 
			save->crtc_enabled[i] = true;
303 
			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
 303 
			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
304 
			if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
 304 
			if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
305 
				radeon_wait_for_vblank(rdev, i);
 305 
				radeon_wait_for_vblank(rdev, i);
- 
 
 306 
				WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
306 
				tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 307 
				tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
307 
				WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
 308 
				WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
- 
 
 309 
				WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
308 
			}
 310 
			}
309 
			/* wait for the next frame */
 311 
			/* wait for the next frame */
310 
			frame_count = radeon_get_vblank_counter(rdev, i);
 312 
			frame_count = radeon_get_vblank_counter(rdev, i);
311 
			for (j = 0; j < rdev->usec_timeout; j++) {
 313 
			for (j = 0; j < rdev->usec_timeout; j++) {
312 
				if (radeon_get_vblank_counter(rdev, i) != frame_count)
 314 
				if (radeon_get_vblank_counter(rdev, i) != frame_count)
313 
					break;
 315 
					break;
314 
				udelay(1);
 316 
				udelay(1);
315 
			}
 317 
			}
- 
 
 318 
 
- 
 
 319 
			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
- 
 
 320 
			WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
- 
 
 321 
			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
- 
 
 322 
			tmp &= ~AVIVO_CRTC_EN;
- 
 
 323 
			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
- 
 
 324 
			WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
- 
 
 325 
			save->crtc_enabled[i] = false;
- 
 
 326 
			/* ***** */
316 
		} else {
 327 
		} else {
317 
			save->crtc_enabled[i] = false;
 328 
			save->crtc_enabled[i] = false;
318 
		}
 329 
		}
319 
	}
 330 
	}
Line 334... Line 345...
334 
				WREG32(R700_MC_CITF_CNTL, blackout);
 345 
				WREG32(R700_MC_CITF_CNTL, blackout);
335 
			else
 346 
			else
336 
				WREG32(R600_CITF_CNTL, blackout);
 347 
				WREG32(R600_CITF_CNTL, blackout);
337 
		}
 348 
		}
338 
	}
 349 
	}
- 
 
 350 
	/* wait for the MC to settle */
- 
 
 351 
	udelay(100);
- 
 
 352 
 
- 
 
 353 
	/* lock double buffered regs */
- 
 
 354 
	for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 355 
		if (save->crtc_enabled[i]) {
- 
 
 356 
			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
- 
 
 357 
			if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
- 
 
 358 
				tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
- 
 
 359 
				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
- 
 
 360 
			}
- 
 
 361 
			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
- 
 
 362 
			if (!(tmp & 1)) {
- 
 
 363 
				tmp |= 1;
- 
 
 364 
				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
- 
 
 365 
			}
- 
 
 366 
		}
- 
 
 367 
	}
339 
}
 368 
}
Line 340... Line 369...
340 
 
 369 
 
341 
void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
 370 
void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
342 
{
 371 
{
343 
	u32 tmp, frame_count;
 372 
	u32 tmp, frame_count;
Line 344... Line 373...
344 
	int i, j;
 373 
	int i, j;
345 
 
 374 
 
346 
	/* update crtc base addresses */
 375 
	/* update crtc base addresses */
347 
	for (i = 0; i < rdev->num_crtc; i++) {
 376 
	for (i = 0; i < rdev->num_crtc; i++) {
348 
		if (rdev->family >= CHIP_RV770) {
 377 
		if (rdev->family >= CHIP_RV770) {
349 
			if (i == 1) {
 378 
			if (i == 0) {
350 
				WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
 379 
				WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
351 
				       upper_32_bits(rdev->mc.vram_start));
 380 
				       upper_32_bits(rdev->mc.vram_start));
352 
				WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
 381 
				WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
Line 363... Line 392...
363 
		WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 392 
		WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
364 
		       (u32)rdev->mc.vram_start);
 393 
		       (u32)rdev->mc.vram_start);
365 
	}
 394 
	}
366 
	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 395 
	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
Line -... Line 396...
- 
 
 396 
 
- 
 
 397 
	/* unlock regs and wait for update */
- 
 
 398 
	for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 399 
		if (save->crtc_enabled[i]) {
- 
 
 400 
			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
- 
 
 401 
			if ((tmp & 0x3) != 0) {
- 
 
 402 
				tmp &= ~0x3;
- 
 
 403 
				WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
- 
 
 404 
			}
- 
 
 405 
			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
- 
 
 406 
			if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
- 
 
 407 
				tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
- 
 
 408 
				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
- 
 
 409 
			}
- 
 
 410 
			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
- 
 
 411 
			if (tmp & 1) {
- 
 
 412 
				tmp &= ~1;
- 
 
 413 
				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
- 
 
 414 
			}
- 
 
 415 
			for (j = 0; j < rdev->usec_timeout; j++) {
- 
 
 416 
				tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
- 
 
 417 
				if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
- 
 
 418 
					break;
- 
 
 419 
				udelay(1);
- 
 
 420 
			}
- 
 
 421 
		}
- 
 
 422 
	}
367 
 
 423 
 
368 
	if (rdev->family >= CHIP_R600) {
 424 
	if (rdev->family >= CHIP_R600) {
369 
		/* unblackout the MC */
 425 
		/* unblackout the MC */
370 
		if (rdev->family >= CHIP_RV770)
 426 
		if (rdev->family >= CHIP_RV770)
371 
			tmp = RREG32(R700_MC_CITF_CNTL);
 427 
			tmp = RREG32(R700_MC_CITF_CNTL);
Line 474... Line 530...
474 
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 530 
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
475 
		return r;
 531 
		return r;
476 
	}
 532 
	}
Line 477... Line 533...
477 
 
 533 
 
- 
 
 534 
	/* Enable IRQ */
- 
 
 535 
	if (!rdev->irq.installed) {
- 
 
 536 
		r = radeon_irq_kms_init(rdev);
- 
 
 537 
		if (r)
- 
 
 538 
			return r;
- 
 
 539 
	}
478 
	/* Enable IRQ */
 540 
 
479 
	rs600_irq_set(rdev);
 541 
	rs600_irq_set(rdev);
480 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 542 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
481 
	/* 1M ring buffer */
 543 
	/* 1M ring buffer */
482 
	r = r100_cp_init(rdev, 1024 * 1024);
 544 
	r = r100_cp_init(rdev, 1024 * 1024);
Line 549... Line 611...
549 
	rv515_debugfs(rdev);
 611 
	rv515_debugfs(rdev);
550 
	/* Fence driver */
 612 
	/* Fence driver */
551 
	r = radeon_fence_driver_init(rdev);
 613 
	r = radeon_fence_driver_init(rdev);
552 
	if (r)
 614 
	if (r)
553 
		return r;
 615 
		return r;
554 
	r = radeon_irq_kms_init(rdev);
 - 
 
555 
	if (r)
 - 
 
556 
		return r;
 - 
 
557 
	/* Memory manager */
 616 
	/* Memory manager */
558 
	r = radeon_bo_init(rdev);
 617 
	r = radeon_bo_init(rdev);
559 
	if (r)
 618 
	if (r)
560 
		return r;
 619 
		return r;
561 
	r = rv370_pcie_gart_init(rdev);
 620 
	r = rv370_pcie_gart_init(rdev);
Line 566... Line 625...
566 
	rdev->accel_working = true;
 625 
	rdev->accel_working = true;
567 
	r = rv515_startup(rdev);
 626 
	r = rv515_startup(rdev);
568 
	if (r) {
 627 
	if (r) {
569 
		/* Somethings want wront with the accel init stop accel */
 628 
		/* Somethings want wront with the accel init stop accel */
570 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
 629 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
571 
//		r100_cp_fini(rdev);
 - 
 
572 
//		r100_wb_fini(rdev);
 - 
 
573 
//		r100_ib_fini(rdev);
 - 
 
574 
		rv370_pcie_gart_fini(rdev);
 - 
 
575 
//		radeon_agp_fini(rdev);
 - 
 
576 
		rdev->accel_working = false;
 630 
		rdev->accel_working = false;
577 
	}
 631 
	}
578 
	return 0;
 632 
	return 0;
579 
}
 633 
}