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Rev 3120 Rev 3192
Line 38... Line 38...
38 
static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
 38 
static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 
static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
 39 
static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 
static void rv515_gpu_init(struct radeon_device *rdev);
 40 
static void rv515_gpu_init(struct radeon_device *rdev);
41 
int rv515_mc_wait_for_idle(struct radeon_device *rdev);
 41 
int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Line -... Line 42...
- 
 
 42 
 
- 
 
 43 
static const u32 crtc_offsets[2] =
- 
 
 44 
{
- 
 
 45 
	0,
- 
 
 46 
	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
- 
 
 47 
};
42 
 
 48 
 
43 
void rv515_debugfs(struct radeon_device *rdev)
 49 
void rv515_debugfs(struct radeon_device *rdev)
44 
{
 50 
{
45 
	if (r100_debugfs_rbbm_init(rdev)) {
 51 
	if (r100_debugfs_rbbm_init(rdev)) {
46 
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 52 
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
Line 279... Line 285...
279 
#endif
 285 
#endif
280 
}
 286 
}
Line 281... Line 287...
281 
 
 287 
 
282 
void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
 288 
void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
- 
 
 289 
{
- 
 
 290 
	u32 crtc_enabled, tmp, frame_count, blackout;
- 
 
 291 
	int i, j;
283 
{
 292 
 
284 
	save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
 293 
	save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
Line 285... Line 294...
285 
	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
 294 
	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
286 
 
 - 
 
287 
	/* Stop all video */
 295 
 
- 
 
 296 
	/* disable VGA render */
- 
 
 297 
	WREG32(R_000300_VGA_RENDER_CONTROL, 0);
- 
 
 298 
	/* blank the display controllers */
- 
 
 299 
	for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 300 
		crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
288 
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 301 
		if (crtc_enabled) {
- 
 
 302 
			save->crtc_enabled[i] = true;
289 
	WREG32(R_000300_VGA_RENDER_CONTROL, 0);
 303 
			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
- 
 
 304 
			if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
290 
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
 305 
				radeon_wait_for_vblank(rdev, i);
- 
 
 306 
				tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
- 
 
 307 
				WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
- 
 
 308 
			}
- 
 
 309 
			/* wait for the next frame */
- 
 
 310 
			frame_count = radeon_get_vblank_counter(rdev, i);
- 
 
 311 
			for (j = 0; j < rdev->usec_timeout; j++) {
- 
 
 312 
				if (radeon_get_vblank_counter(rdev, i) != frame_count)
- 
 
 313 
					break;
- 
 
 314 
				udelay(1);
- 
 
 315 
			}
- 
 
 316 
		} else {
- 
 
 317 
			save->crtc_enabled[i] = false;
- 
 
 318 
		}
- 
 
 319 
	}
- 
 
 320 
 
- 
 
 321 
	radeon_mc_wait_for_idle(rdev);
- 
 
 322 
 
291 
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
 323 
	if (rdev->family >= CHIP_R600) {
- 
 
 324 
		if (rdev->family >= CHIP_RV770)
292 
	WREG32(R_006080_D1CRTC_CONTROL, 0);
 325 
			blackout = RREG32(R700_MC_CITF_CNTL);
- 
 
 326 
		else
- 
 
 327 
			blackout = RREG32(R600_CITF_CNTL);
293 
	WREG32(R_006880_D2CRTC_CONTROL, 0);
 328 
		if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
- 
 
 329 
			/* Block CPU access */
- 
 
 330 
			WREG32(R600_BIF_FB_EN, 0);
- 
 
 331 
			/* blackout the MC */
294 
	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
 332 
			blackout |= R600_BLACKOUT_MASK;
- 
 
 333 
			if (rdev->family >= CHIP_RV770)
295 
	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
 334 
				WREG32(R700_MC_CITF_CNTL, blackout);
- 
 
 335 
			else
- 
 
 336 
				WREG32(R600_CITF_CNTL, blackout);
296 
	WREG32(R_000330_D1VGA_CONTROL, 0);
 337 
		}
Line 297... Line 338...
297 
	WREG32(R_000338_D2VGA_CONTROL, 0);
 338 
	}
298 
}
 339 
}
- 
 
 340 
 
- 
 
 341 
void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
- 
 
 342 
{
- 
 
 343 
	u32 tmp, frame_count;
- 
 
 344 
	int i, j;
- 
 
 345 
 
- 
 
 346 
	/* update crtc base addresses */
299 
 
 347 
	for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 348 
		if (rdev->family >= CHIP_RV770) {
300 
void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
 349 
			if (i == 1) {
- 
 
 350 
				WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
- 
 
 351 
				       upper_32_bits(rdev->mc.vram_start));
- 
 
 352 
				WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
- 
 
 353 
				       upper_32_bits(rdev->mc.vram_start));
- 
 
 354 
			} else {
- 
 
 355 
				WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
- 
 
 356 
				       upper_32_bits(rdev->mc.vram_start));
- 
 
 357 
				WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
301 
{
 358 
				       upper_32_bits(rdev->mc.vram_start));
- 
 
 359 
			}
302 
	WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 360 
		}
- 
 
 361 
		WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
- 
 
 362 
		       (u32)rdev->mc.vram_start);
303 
	WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 363 
		WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
- 
 
 364 
		       (u32)rdev->mc.vram_start);
- 
 
 365 
	}
- 
 
 366 
	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
- 
 
 367 
 
- 
 
 368 
	if (rdev->family >= CHIP_R600) {
- 
 
 369 
		/* unblackout the MC */
- 
 
 370 
		if (rdev->family >= CHIP_RV770)
- 
 
 371 
			tmp = RREG32(R700_MC_CITF_CNTL);
- 
 
 372 
		else
- 
 
 373 
			tmp = RREG32(R600_CITF_CNTL);
- 
 
 374 
		tmp &= ~R600_BLACKOUT_MASK;
- 
 
 375 
		if (rdev->family >= CHIP_RV770)
- 
 
 376 
			WREG32(R700_MC_CITF_CNTL, tmp);
- 
 
 377 
		else
- 
 
 378 
			WREG32(R600_CITF_CNTL, tmp);
- 
 
 379 
		/* allow CPU access */
- 
 
 380 
		WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
- 
 
 381 
	}
- 
 
 382 
 
- 
 
 383 
	for (i = 0; i < rdev->num_crtc; i++) {
- 
 
 384 
		if (save->crtc_enabled[i]) {
- 
 
 385 
			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
- 
 
 386 
			tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
- 
 
 387 
			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
- 
 
 388 
			/* wait for the next frame */
- 
 
 389 
			frame_count = radeon_get_vblank_counter(rdev, i);
- 
 
 390 
			for (j = 0; j < rdev->usec_timeout; j++) {
- 
 
 391 
				if (radeon_get_vblank_counter(rdev, i) != frame_count)
- 
 
 392 
					break;
- 
 
 393 
				udelay(1);
304 
	WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 394 
			}
305 
	WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
 395 
		}
306 
	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
 396 
	}
307 
	/* Unlock host access */
 397 
	/* Unlock vga access */
308 
	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
 398 
	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);