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23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | //#include |
28 | #include |
29 | #include "drmP.h" |
29 | #include "drmP.h" |
30 | #include "radeon_reg.h" |
30 | #include "rv515d.h" |
31 | #include "radeon.h" |
31 | #include "radeon.h" |
Line -... | Line 32... | ||
- | 32 | ||
32 | 33 | #include "rv515_reg_safe.h" |
|
33 | /* rv515 depends on : */ |
34 | /* rv515 depends on : */ |
34 | void r100_hdp_reset(struct radeon_device *rdev); |
35 | void r100_hdp_reset(struct radeon_device *rdev); |
35 | int r100_cp_reset(struct radeon_device *rdev); |
36 | int r100_cp_reset(struct radeon_device *rdev); |
36 | int r100_rb2d_reset(struct radeon_device *rdev); |
37 | int r100_rb2d_reset(struct radeon_device *rdev); |
37 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
38 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
38 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
- | |
39 | int rv370_pcie_gart_enable(struct radeon_device *rdev); |
- | |
40 | void rv370_pcie_gart_disable(struct radeon_device *rdev); |
39 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
41 | void r420_pipes_init(struct radeon_device *rdev); |
40 | void r420_pipes_init(struct radeon_device *rdev); |
42 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
41 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
Line 43... | Line 42... | ||
43 | void rs600_disable_vga(struct radeon_device *rdev); |
42 | void rs600_disable_vga(struct radeon_device *rdev); |
Line 50... | Line 49... | ||
50 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
49 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
51 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
50 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
52 | void rv515_gpu_init(struct radeon_device *rdev); |
51 | void rv515_gpu_init(struct radeon_device *rdev); |
53 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
52 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
Line -... | Line 53... | ||
- | 53 | ||
54 | 54 | ||
55 | /* |
55 | /* |
56 | * MC |
56 | * MC |
57 | */ |
57 | */ |
58 | int rv515_mc_init(struct radeon_device *rdev) |
58 | int rv515_mc_init(struct radeon_device *rdev) |
Line 74... | Line 74... | ||
74 | rv370_pcie_gart_disable(rdev); |
74 | rv370_pcie_gart_disable(rdev); |
Line 75... | Line 75... | ||
75 | 75 | ||
76 | /* Setup GPU memory space */ |
76 | /* Setup GPU memory space */ |
77 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
77 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
78 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
78 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
79 | if (rdev->flags & RADEON_IS_AGP) { |
79 | // if (rdev->flags & RADEON_IS_AGP) { |
80 | r = radeon_agp_init(rdev); |
80 | // r = radeon_agp_init(rdev); |
81 | if (r) { |
81 | // if (r) { |
82 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
82 | // printk(KERN_WARNING "[drm] Disabling AGP\n"); |
83 | rdev->flags &= ~RADEON_IS_AGP; |
83 | // rdev->flags &= ~RADEON_IS_AGP; |
84 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
84 | // rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
85 | } else { |
85 | // } else { |
86 | rdev->mc.gtt_location = rdev->mc.agp_base; |
86 | // rdev->mc.gtt_location = rdev->mc.agp_base; |
87 | } |
87 | // } |
88 | } |
88 | // } |
89 | r = radeon_mc_setup(rdev); |
89 | r = radeon_mc_setup(rdev); |
90 | if (r) { |
90 | if (r) { |
91 | return r; |
91 | return r; |
Line 96... | Line 96... | ||
96 | if (rv515_mc_wait_for_idle(rdev)) { |
96 | if (rv515_mc_wait_for_idle(rdev)) { |
97 | printk(KERN_WARNING "Failed to wait MC idle while " |
97 | printk(KERN_WARNING "Failed to wait MC idle while " |
98 | "programming pipes. Bad things might happen.\n"); |
98 | "programming pipes. Bad things might happen.\n"); |
99 | } |
99 | } |
100 | /* Write VRAM size in case we are limiting it */ |
100 | /* Write VRAM size in case we are limiting it */ |
101 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
101 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
102 | tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16); |
102 | tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); |
103 | WREG32(0x134, tmp); |
103 | WREG32(0x134, tmp); |
104 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
104 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
105 | tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16); |
105 | tmp = REG_SET(MC_FB_TOP, tmp >> 16); |
106 | tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16); |
106 | tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); |
107 | WREG32_MC(RV515_MC_FB_LOCATION, tmp); |
107 | WREG32_MC(MC_FB_LOCATION, tmp); |
108 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
108 | WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
109 | WREG32(0x310, rdev->mc.vram_location); |
109 | WREG32(0x310, rdev->mc.vram_location); |
110 | if (rdev->flags & RADEON_IS_AGP) { |
110 | if (rdev->flags & RADEON_IS_AGP) { |
111 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
111 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
112 | tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16); |
112 | tmp = REG_SET(MC_AGP_TOP, tmp >> 16); |
113 | tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16); |
113 | tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16); |
114 | WREG32_MC(RV515_MC_AGP_LOCATION, tmp); |
114 | WREG32_MC(MC_AGP_LOCATION, tmp); |
115 | WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base); |
115 | WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base); |
116 | WREG32_MC(RV515_MC_AGP_BASE_2, 0); |
116 | WREG32_MC(MC_AGP_BASE_2, 0); |
117 | } else { |
117 | } else { |
118 | WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF); |
118 | WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF); |
119 | WREG32_MC(RV515_MC_AGP_BASE, 0); |
119 | WREG32_MC(MC_AGP_BASE, 0); |
120 | WREG32_MC(RV515_MC_AGP_BASE_2, 0); |
120 | WREG32_MC(MC_AGP_BASE_2, 0); |
121 | } |
121 | } |
122 | return 0; |
122 | return 0; |
123 | } |
123 | } |
Line 124... | Line 124... | ||
124 | 124 | ||
125 | void rv515_mc_fini(struct radeon_device *rdev) |
125 | void rv515_mc_fini(struct radeon_device *rdev) |
126 | { |
- | |
127 | rv370_pcie_gart_disable(rdev); |
- | |
128 | radeon_gart_table_vram_free(rdev); |
- | |
129 | radeon_gart_fini(rdev); |
126 | { |
Line 130... | Line 127... | ||
130 | } |
127 | } |
131 | 128 | ||
132 | 129 | ||
133 | /* |
130 | /* |
134 | * Global GPU functions |
131 | * Global GPU functions |
135 | */ |
- | |
136 | void rv515_ring_start(struct radeon_device *rdev) |
132 | */ |
Line 137... | Line -... | ||
137 | { |
- | |
138 | unsigned gb_tile_config; |
- | |
139 | int r; |
- | |
140 | - | ||
141 | dbgprintf("%s\n",__FUNCTION__); |
- | |
142 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
- | |
143 | gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16; |
133 | void rv515_ring_start(struct radeon_device *rdev) |
144 | switch (rdev->num_gb_pipes) { |
- | |
145 | case 2: |
- | |
146 | gb_tile_config |= R300_PIPE_COUNT_R300; |
- | |
147 | break; |
- | |
148 | case 3: |
- | |
149 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
- | |
150 | break; |
- | |
151 | case 4: |
- | |
152 | gb_tile_config |= R300_PIPE_COUNT_R420; |
- | |
153 | break; |
- | |
154 | case 1: |
- | |
Line 155... | Line 134... | ||
155 | default: |
134 | { |
156 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
135 | int r; |
157 | break; |
136 | |
158 | } |
137 | ENTER(); |
159 | 138 | ||
160 | r = radeon_ring_lock(rdev, 64); |
- | |
161 | if (r) { |
- | |
162 | return; |
- | |
163 | } |
- | |
164 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
- | |
165 | radeon_ring_write(rdev, |
- | |
166 | RADEON_ISYNC_ANY2D_IDLE3D | |
- | |
167 | RADEON_ISYNC_ANY3D_IDLE2D | |
- | |
168 | RADEON_ISYNC_WAIT_IDLEGUI | |
139 | r = radeon_ring_lock(rdev, 64); |
169 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
140 | if (r) { |
- | 141 | return; |
|
170 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
142 | } |
- | 143 | radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); |
|
- | 144 | radeon_ring_write(rdev, |
|
- | 145 | ISYNC_ANY2D_IDLE3D | |
|
171 | radeon_ring_write(rdev, gb_tile_config); |
146 | ISYNC_ANY3D_IDLE2D | |
172 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
147 | ISYNC_WAIT_IDLEGUI | |
173 | radeon_ring_write(rdev, |
148 | ISYNC_CPSCRATCH_IDLEGUI); |
174 | RADEON_WAIT_2D_IDLECLEAN | |
149 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
175 | RADEON_WAIT_3D_IDLECLEAN); |
150 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
176 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
151 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
177 | radeon_ring_write(rdev, 1 << 31); |
152 | radeon_ring_write(rdev, 1 << 31); |
178 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
153 | radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); |
179 | radeon_ring_write(rdev, 0); |
154 | radeon_ring_write(rdev, 0); |
180 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
155 | radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); |
181 | radeon_ring_write(rdev, 0); |
156 | radeon_ring_write(rdev, 0); |
182 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); |
157 | radeon_ring_write(rdev, PACKET0(0x42C8, 0)); |
183 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
158 | radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
184 | radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0)); |
159 | radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); |
185 | radeon_ring_write(rdev, 0); |
160 | radeon_ring_write(rdev, 0); |
186 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
- | |
187 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
- | |
188 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
161 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
189 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
162 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
190 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
163 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
191 | radeon_ring_write(rdev, |
164 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
192 | RADEON_WAIT_2D_IDLECLEAN | |
165 | radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); |
193 | RADEON_WAIT_3D_IDLECLEAN); |
166 | radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
194 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
167 | radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); |
195 | radeon_ring_write(rdev, 0); |
168 | radeon_ring_write(rdev, 0); |
196 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
- | |
197 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
- | |
198 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
- | |
199 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
- | |
200 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
- | |
201 | radeon_ring_write(rdev, |
- | |
202 | ((6 << R300_MS_X0_SHIFT) | |
- | |
203 | (6 << R300_MS_Y0_SHIFT) | |
- | |
204 | (6 << R300_MS_X1_SHIFT) | |
- | |
205 | (6 << R300_MS_Y1_SHIFT) | |
- | |
206 | (6 << R300_MS_X2_SHIFT) | |
- | |
207 | (6 << R300_MS_Y2_SHIFT) | |
- | |
208 | (6 << R300_MSBD0_Y_SHIFT) | |
- | |
209 | (6 << R300_MSBD0_X_SHIFT))); |
- | |
210 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
- | |
211 | radeon_ring_write(rdev, |
- | |
212 | ((6 << R300_MS_X3_SHIFT) | |
- | |
213 | (6 << R300_MS_Y3_SHIFT) | |
- | |
214 | (6 << R300_MS_X4_SHIFT) | |
- | |
215 | (6 << R300_MS_Y4_SHIFT) | |
- | |
216 | (6 << R300_MS_X5_SHIFT) | |
- | |
217 | (6 << R300_MS_Y5_SHIFT) | |
169 | radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
- | 170 | radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); |
|
- | 171 | radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
|
- | 172 | radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); |
|
- | 173 | radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); |
|
- | 174 | radeon_ring_write(rdev, |
|
- | 175 | ((6 << MS_X0_SHIFT) | |
|
- | 176 | (6 << MS_Y0_SHIFT) | |
|
218 | (6 << R300_MSBD1_SHIFT))); |
177 | (6 << MS_X1_SHIFT) | |
219 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
178 | (6 << MS_Y1_SHIFT) | |
220 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
179 | (6 << MS_X2_SHIFT) | |
- | 180 | (6 << MS_Y2_SHIFT) | |
|
- | 181 | (6 << MSBD0_Y_SHIFT) | |
|
- | 182 | (6 << MSBD0_X_SHIFT))); |
|
221 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
183 | radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); |
- | 184 | radeon_ring_write(rdev, |
|
- | 185 | ((6 << MS_X3_SHIFT) | |
|
222 | radeon_ring_write(rdev, |
186 | (6 << MS_Y3_SHIFT) | |
- | 187 | (6 << MS_X4_SHIFT) | |
|
- | 188 | (6 << MS_Y4_SHIFT) | |
|
- | 189 | (6 << MS_X5_SHIFT) | |
|
- | 190 | (6 << MS_Y5_SHIFT) | |
|
- | 191 | (6 << MSBD1_SHIFT))); |
|
- | 192 | radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); |
|
223 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
193 | radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
224 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
194 | radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); |
225 | radeon_ring_write(rdev, |
195 | radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
Line 226... | Line 196... | ||
226 | R300_GEOMETRY_ROUND_NEAREST | |
196 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); |
Line 227... | Line 197... | ||
227 | R300_COLOR_ROUND_NEAREST); |
197 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
Line 228... | Line 198... | ||
228 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
198 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
229 | radeon_ring_write(rdev, 0); |
199 | radeon_ring_write(rdev, 0); |
Line 243... | Line 213... | ||
243 | unsigned i; |
213 | unsigned i; |
244 | uint32_t tmp; |
214 | uint32_t tmp; |
Line 245... | Line 215... | ||
245 | 215 | ||
246 | for (i = 0; i < rdev->usec_timeout; i++) { |
216 | for (i = 0; i < rdev->usec_timeout; i++) { |
247 | /* read MC_STATUS */ |
217 | /* read MC_STATUS */ |
248 | tmp = RREG32_MC(RV515_MC_STATUS); |
218 | tmp = RREG32_MC(MC_STATUS); |
249 | if (tmp & RV515_MC_STATUS_IDLE) { |
219 | if (tmp & MC_STATUS_IDLE) { |
250 | return 0; |
220 | return 0; |
251 | } |
221 | } |
252 | DRM_UDELAY(1); |
222 | DRM_UDELAY(1); |
253 | } |
223 | } |
Line 283... | Line 253... | ||
283 | printk(KERN_WARNING "Failed to wait MC idle while " |
253 | printk(KERN_WARNING "Failed to wait MC idle while " |
284 | "programming pipes. Bad things might happen.\n"); |
254 | "programming pipes. Bad things might happen.\n"); |
285 | } |
255 | } |
286 | } |
256 | } |
Line 287... | Line -... | ||
287 | - | ||
288 | 257 | ||
289 | int rv515_ga_reset(struct radeon_device *rdev) |
258 | int rv515_ga_reset(struct radeon_device *rdev) |
290 | { |
259 | { |
291 | uint32_t tmp; |
260 | uint32_t tmp; |
292 | bool reinit_cp; |
261 | bool reinit_cp; |
Line 293... | Line 262... | ||
293 | int i; |
262 | int i; |
Line 294... | Line 263... | ||
294 | 263 | ||
295 | dbgprintf("%s\n",__FUNCTION__); |
264 | ENTER(); |
296 | 265 | ||
297 | reinit_cp = rdev->cp.ready; |
266 | reinit_cp = rdev->cp.ready; |
298 | rdev->cp.ready = false; |
267 | rdev->cp.ready = false; |
299 | for (i = 0; i < rdev->usec_timeout; i++) { |
268 | for (i = 0; i < rdev->usec_timeout; i++) { |
300 | WREG32(RADEON_CP_CSQ_MODE, 0); |
269 | WREG32(CP_CSQ_MODE, 0); |
301 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
270 | WREG32(CP_CSQ_CNTL, 0); |
302 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
271 | WREG32(RBBM_SOFT_RESET, 0x32005); |
303 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
272 | (void)RREG32(RBBM_SOFT_RESET); |
304 | udelay(200); |
273 | udelay(200); |
305 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
274 | WREG32(RBBM_SOFT_RESET, 0); |
306 | /* Wait to prevent race in RBBM_STATUS */ |
275 | /* Wait to prevent race in RBBM_STATUS */ |
307 | mdelay(1); |
276 | mdelay(1); |
308 | tmp = RREG32(RADEON_RBBM_STATUS); |
277 | tmp = RREG32(RBBM_STATUS); |
309 | if (tmp & ((1 << 20) | (1 << 26))) { |
278 | if (tmp & ((1 << 20) | (1 << 26))) { |
310 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); |
279 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); |
311 | /* GA still busy soft reset it */ |
280 | /* GA still busy soft reset it */ |
312 | WREG32(0x429C, 0x200); |
281 | WREG32(0x429C, 0x200); |
313 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
282 | WREG32(VAP_PVS_STATE_FLUSH_REG, 0); |
314 | WREG32(0x43E0, 0); |
283 | WREG32(0x43E0, 0); |
315 | WREG32(0x43E4, 0); |
284 | WREG32(0x43E4, 0); |
316 | WREG32(0x24AC, 0); |
285 | WREG32(0x24AC, 0); |
317 | } |
286 | } |
318 | /* Wait to prevent race in RBBM_STATUS */ |
287 | /* Wait to prevent race in RBBM_STATUS */ |
319 | mdelay(1); |
288 | mdelay(1); |
320 | tmp = RREG32(RADEON_RBBM_STATUS); |
289 | tmp = RREG32(RBBM_STATUS); |
321 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
290 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
322 | break; |
291 | break; |
323 | } |
292 | } |
324 | } |
293 | } |
325 | for (i = 0; i < rdev->usec_timeout; i++) { |
294 | for (i = 0; i < rdev->usec_timeout; i++) { |
326 | tmp = RREG32(RADEON_RBBM_STATUS); |
295 | tmp = RREG32(RBBM_STATUS); |
327 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
296 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
328 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
297 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
Line 335... | Line 304... | ||
335 | } |
304 | } |
336 | return 0; |
305 | return 0; |
337 | } |
306 | } |
338 | DRM_UDELAY(1); |
307 | DRM_UDELAY(1); |
339 | } |
308 | } |
340 | tmp = RREG32(RADEON_RBBM_STATUS); |
309 | tmp = RREG32(RBBM_STATUS); |
341 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
310 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
342 | return -1; |
311 | return -1; |
343 | } |
312 | } |
Line 344... | Line 313... | ||
344 | 313 | ||
345 | int rv515_gpu_reset(struct radeon_device *rdev) |
314 | int rv515_gpu_reset(struct radeon_device *rdev) |
346 | { |
315 | { |
Line 347... | Line 316... | ||
347 | uint32_t status; |
316 | uint32_t status; |
Line 348... | Line 317... | ||
348 | 317 | ||
349 | dbgprintf("%s\n",__FUNCTION__); |
318 | ENTER(); |
350 | 319 | ||
351 | /* reset order likely matter */ |
320 | /* reset order likely matter */ |
352 | status = RREG32(RADEON_RBBM_STATUS); |
321 | status = RREG32(RBBM_STATUS); |
353 | /* reset HDP */ |
322 | /* reset HDP */ |
354 | r100_hdp_reset(rdev); |
323 | r100_hdp_reset(rdev); |
Line 359... | Line 328... | ||
359 | /* reset GA */ |
328 | /* reset GA */ |
360 | if (status & ((1 << 20) | (1 << 26))) { |
329 | if (status & ((1 << 20) | (1 << 26))) { |
361 | rv515_ga_reset(rdev); |
330 | rv515_ga_reset(rdev); |
362 | } |
331 | } |
363 | /* reset CP */ |
332 | /* reset CP */ |
364 | status = RREG32(RADEON_RBBM_STATUS); |
333 | status = RREG32(RBBM_STATUS); |
365 | if (status & (1 << 16)) { |
334 | if (status & (1 << 16)) { |
366 | r100_cp_reset(rdev); |
335 | r100_cp_reset(rdev); |
367 | } |
336 | } |
368 | /* Check if GPU is idle */ |
337 | /* Check if GPU is idle */ |
369 | status = RREG32(RADEON_RBBM_STATUS); |
338 | status = RREG32(RBBM_STATUS); |
370 | if (status & (1 << 31)) { |
339 | if (status & (1 << 31)) { |
371 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
340 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
372 | return -1; |
341 | return -1; |
373 | } |
342 | } |
374 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
343 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
Line 383... | Line 352... | ||
383 | { |
352 | { |
384 | uint32_t tmp; |
353 | uint32_t tmp; |
Line 385... | Line 354... | ||
385 | 354 | ||
386 | rdev->mc.vram_width = 128; |
355 | rdev->mc.vram_width = 128; |
387 | rdev->mc.vram_is_ddr = true; |
- | |
388 | tmp = RREG32_MC(RV515_MC_CNTL); |
356 | rdev->mc.vram_is_ddr = true; |
389 | tmp &= RV515_MEM_NUM_CHANNELS_MASK; |
357 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
390 | switch (tmp) { |
358 | switch (tmp) { |
391 | case 0: |
359 | case 0: |
392 | rdev->mc.vram_width = 64; |
360 | rdev->mc.vram_width = 64; |
393 | break; |
361 | break; |
Line 400... | Line 368... | ||
400 | } |
368 | } |
401 | } |
369 | } |
Line 402... | Line 370... | ||
402 | 370 | ||
403 | void rv515_vram_info(struct radeon_device *rdev) |
371 | void rv515_vram_info(struct radeon_device *rdev) |
- | 372 | { |
|
- | 373 | fixed20_12 a; |
|
404 | { |
374 | |
405 | rv515_vram_get_type(rdev); |
- | |
Line -... | Line 375... | ||
- | 375 | rv515_vram_get_type(rdev); |
|
- | 376 | ||
- | 377 | r100_vram_init_sizes(rdev); |
|
- | 378 | /* FIXME: we should enforce default clock in case GPU is not in |
|
- | 379 | * default setup |
|
406 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
380 | */ |
407 | 381 | a.full = rfixed_const(100); |
|
408 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
382 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
Line 409... | Line 383... | ||
409 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
383 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
410 | } |
384 | } |
411 | 385 | ||
412 | 386 | ||
413 | /* |
387 | /* |
414 | * Indirect registers accessor |
388 | * Indirect registers accessor |
Line 415... | Line 389... | ||
415 | */ |
389 | */ |
416 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
390 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
417 | { |
391 | { |
418 | uint32_t r; |
392 | uint32_t r; |
419 | 393 | ||
Line 420... | Line 394... | ||
420 | WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
394 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
421 | r = RREG32(R520_MC_IND_DATA); |
395 | r = RREG32(MC_IND_DATA); |
422 | WREG32(R520_MC_IND_INDEX, 0); |
396 | WREG32(MC_IND_INDEX, 0); |
423 | return r; |
397 | return r; |
424 | } |
398 | } |
425 | - | ||
426 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
- | |
427 | { |
- | |
428 | WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
- | |
429 | WREG32(R520_MC_IND_DATA, (v)); |
- | |
430 | WREG32(R520_MC_IND_INDEX, 0); |
- | |
431 | } |
- | |
432 | - | ||
433 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
- | |
434 | { |
- | |
435 | uint32_t r; |
- | |
436 | - | ||
437 | WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff)); |
- | |
438 | (void)RREG32(RADEON_PCIE_INDEX); |
- | |
439 | r = RREG32(RADEON_PCIE_DATA); |
- | |
440 | return r; |
- | |
441 | } |
- | |
442 | - | ||
443 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
399 | |
Line 444... | Line -... | ||
444 | { |
- | |
445 | WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff)); |
400 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
446 | (void)RREG32(RADEON_PCIE_INDEX); |
401 | { |
447 | WREG32(RADEON_PCIE_DATA, (v)); |
402 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
448 | (void)RREG32(RADEON_PCIE_DATA); |
403 | WREG32(MC_IND_DATA, (v)); |
449 | } |
404 | WREG32(MC_IND_INDEX, 0); |
Line 458... | Line 413... | ||
458 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
413 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
459 | struct drm_device *dev = node->minor->dev; |
414 | struct drm_device *dev = node->minor->dev; |
460 | struct radeon_device *rdev = dev->dev_private; |
415 | struct radeon_device *rdev = dev->dev_private; |
461 | uint32_t tmp; |
416 | uint32_t tmp; |
Line 462... | Line 417... | ||
462 | 417 | ||
463 | tmp = RREG32(R400_GB_PIPE_SELECT); |
418 | tmp = RREG32(GB_PIPE_SELECT); |
464 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
419 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
465 | tmp = RREG32(R500_SU_REG_DEST); |
420 | tmp = RREG32(SU_REG_DEST); |
466 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
421 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
467 | tmp = RREG32(R300_GB_TILE_CONFIG); |
422 | tmp = RREG32(GB_TILE_CONFIG); |
468 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
423 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
469 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
424 | tmp = RREG32(DST_PIPE_CONFIG); |
470 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
425 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
471 | return 0; |
426 | return 0; |
Line 472... | Line 427... | ||
472 | } |
427 | } |
Line 511... | Line 466... | ||
511 | #else |
466 | #else |
512 | return 0; |
467 | return 0; |
513 | #endif |
468 | #endif |
514 | } |
469 | } |
Line 515... | Line -... | ||
515 | - | ||
516 | 470 | ||
517 | /* |
471 | /* |
518 | * Asic initialization |
472 | * Asic initialization |
560 | 0x0003FC01, 0x3FFFFCF8, 0xFE800B19, |
723 | fixed20_12 sclk; |
Line -... | Line 724... | ||
- | 724 | }; |
|
- | 725 | ||
- | 726 | void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
|
- | 727 | struct radeon_crtc *crtc, |
|
- | 728 | struct rv515_watermark *wm) |
|
- | 729 | { |
|
- | 730 | struct drm_display_mode *mode = &crtc->base.mode; |
|
- | 731 | fixed20_12 a, b, c; |
|
- | 732 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
|
- | 733 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
|
- | 734 | ||
- | 735 | if (!crtc->base.enabled) { |
|
- | 736 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
|
- | 737 | wm->lb_request_fifo_depth = 4; |
|
Line -... | Line 738... | ||
- | 738 | return; |
|
- | 739 | } |
|
- | 740 | ||
- | 741 | if (crtc->vsc.full > rfixed_const(2)) |
|
- | 742 | wm->num_line_pair.full = rfixed_const(2); |
|
- | 743 | else |
|
- | 744 | wm->num_line_pair.full = rfixed_const(1); |
|
- | 745 | ||
- | 746 | b.full = rfixed_const(mode->crtc_hdisplay); |
|
- | 747 | c.full = rfixed_const(256); |
|
- | 748 | a.full = rfixed_mul(wm->num_line_pair, b); |
|
- | 749 | request_fifo_depth.full = rfixed_div(a, c); |
|
- | 750 | if (a.full < rfixed_const(4)) { |
|
- | 751 | wm->lb_request_fifo_depth = 4; |
|
Line -... | Line 752... | ||
- | 752 | } else { |
|
- | 753 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); |
|
- | 754 | } |
|
- | 755 | ||
- | 756 | /* Determine consumption rate |
|
- | 757 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
|
- | 758 | * vtaps = number of vertical taps, |
|
- | 759 | * vsc = vertical scaling ratio, defined as source/destination |
|
- | 760 | * hsc = horizontal scaling ration, defined as source/destination |
|
- | 761 | */ |
|
- | 762 | a.full = rfixed_const(mode->clock); |
|
- | 763 | b.full = rfixed_const(1000); |
|
- | 764 | a.full = rfixed_div(a, b); |
|
- | 765 | pclk.full = rfixed_div(b, a); |
|
- | 766 | if (crtc->rmx_type != RMX_OFF) { |
|
- | 767 | b.full = rfixed_const(2); |
|
- | 768 | if (crtc->vsc.full > b.full) |
|
- | 769 | b.full = crtc->vsc.full; |
|
- | 770 | b.full = rfixed_mul(b, crtc->hsc); |
|
- | 771 | c.full = rfixed_const(2); |
|
- | 772 | b.full = rfixed_div(b, c); |
|
- | 773 | consumption_time.full = rfixed_div(pclk, b); |
|
- | 774 | } else { |
|
- | 775 | consumption_time.full = pclk.full; |
|
- | 776 | } |
|
- | 777 | a.full = rfixed_const(1); |
|
- | 778 | wm->consumption_rate.full = rfixed_div(a, consumption_time); |
|
- | 779 | ||
- | 780 | ||
- | 781 | /* Determine line time |
|
- | 782 | * LineTime = total time for one line of displayhtotal |
|
- | 783 | * LineTime = total number of horizontal pixels |
|
- | 784 | * pclk = pixel clock period(ns) |
|
- | 785 | */ |
|
- | 786 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
|
- | 787 | line_time.full = rfixed_mul(a, pclk); |
|
- | 788 | ||
- | 789 | /* Determine active time |
|
- | 790 | * ActiveTime = time of active region of display within one line, |
|
- | 791 | * hactive = total number of horizontal active pixels |
|
- | 792 | * htotal = total number of horizontal pixels |
|
- | 793 | */ |
|
- | 794 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
|
- | 795 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
|
- | 796 | wm->active_time.full = rfixed_mul(line_time, b); |
|
- | 797 | wm->active_time.full = rfixed_div(wm->active_time, a); |
|
- | 798 | ||
- | 799 | /* Determine chunk time |
|
- | 800 | * ChunkTime = the time it takes the DCP to send one chunk of data |
|
- | 801 | * to the LB which consists of pipeline delay and inter chunk gap |
|
- | 802 | * sclk = system clock(Mhz) |
|
- | 803 | */ |
|
- | 804 | a.full = rfixed_const(600 * 1000); |
|
- | 805 | chunk_time.full = rfixed_div(a, rdev->pm.sclk); |
|
- | 806 | read_delay_latency.full = rfixed_const(1000); |
|
- | 807 | ||
- | 808 | /* Determine the worst case latency |
|
- | 809 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
|
- | 810 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
|
- | 811 | * to return data |
|
- | 812 | * READ_DELAY_IDLE_MAX = constant of 1us |
|
- | 813 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
|
- | 814 | * which consists of pipeline delay and inter chunk gap |
|
- | 815 | */ |
|
- | 816 | if (rfixed_trunc(wm->num_line_pair) > 1) { |
|
- | 817 | a.full = rfixed_const(3); |
|
- | 818 | wm->worst_case_latency.full = rfixed_mul(a, chunk_time); |
|
- | 819 | wm->worst_case_latency.full += read_delay_latency.full; |
|
- | 820 | } else { |
|
- | 821 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
|
- | 822 | } |
|
- | 823 | ||
- | 824 | /* Determine the tolerable latency |
|
- | 825 | * TolerableLatency = Any given request has only 1 line time |
|
- | 826 | * for the data to be returned |
|
- | 827 | * LBRequestFifoDepth = Number of chunk requests the LB can |
|
- | 828 | * put into the request FIFO for a display |
|
- | 829 | * LineTime = total time for one line of display |
|
- | 830 | * ChunkTime = the time it takes the DCP to send one chunk |
|
- | 831 | * of data to the LB which consists of |
|
- | 832 | * pipeline delay and inter chunk gap |
|
- | 833 | */ |
|
- | 834 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { |
|
- | 835 | tolerable_latency.full = line_time.full; |
|
- | 836 | } else { |
|
- | 837 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); |
|
- | 838 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
|
- | 839 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); |
|
- | 840 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
|
- | 841 | } |
|
- | 842 | /* We assume worst case 32bits (4 bytes) */ |
|
- | 843 | wm->dbpp.full = rfixed_const(2 * 16); |
|
- | 844 | ||
- | 845 | /* Determine the maximum priority mark |
|
- | 846 | * width = viewport width in pixels |
|
- | 847 | */ |
|
- | 848 | a.full = rfixed_const(16); |
|
- | 849 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
|
- | 850 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); |
|
- | 851 | ||
- | 852 | /* Determine estimated width */ |
|
- | 853 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
|
- | 854 | estimated_width.full = rfixed_div(estimated_width, consumption_time); |
|
- | 855 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
|
- | 856 | wm->priority_mark.full = rfixed_const(10); |
|
- | 857 | } else { |
|
- | 858 | a.full = rfixed_const(16); |
|
- | 859 | wm->priority_mark.full = rfixed_div(estimated_width, a); |
|
- | 860 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
|
- | 861 | } |
|
- | 862 | } |
|
- | 863 | ||
- | 864 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
|
- | 865 | { |
|
- | 866 | struct drm_display_mode *mode0 = NULL; |
|
- | 867 | struct drm_display_mode *mode1 = NULL; |
|
- | 868 | struct rv515_watermark wm0; |
|
- | 869 | struct rv515_watermark wm1; |
|
- | 870 | u32 tmp; |
|
- | 871 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
|
- | 872 | fixed20_12 a, b; |
|
- | 873 | ||
- | 874 | if (rdev->mode_info.crtcs[0]->base.enabled) |
|
- | 875 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
|
- | 876 | if (rdev->mode_info.crtcs[1]->base.enabled) |
|
- | 877 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
|
- | 878 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
|
- | 879 | ||
- | 880 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
|
- | 881 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
|
- | 882 | ||
- | 883 | tmp = wm0.lb_request_fifo_depth; |
|
- | 884 | tmp |= wm1.lb_request_fifo_depth << 16; |
|
- | 885 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
|
- | 886 | ||
- | 887 | if (mode0 && mode1) { |
|
- | 888 | if (rfixed_trunc(wm0.dbpp) > 64) |
|
- | 889 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); |
|
- | 890 | else |
|
- | 891 | a.full = wm0.num_line_pair.full; |
|
- | 892 | if (rfixed_trunc(wm1.dbpp) > 64) |
|
- | 893 | b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); |
|
- | 894 | else |
|
- | 895 | b.full = wm1.num_line_pair.full; |
|
- | 896 | a.full += b.full; |
|
- | 897 | fill_rate.full = rfixed_div(wm0.sclk, a); |
|
- | 898 | if (wm0.consumption_rate.full > fill_rate.full) { |
|
- | 899 | b.full = wm0.consumption_rate.full - fill_rate.full; |
|
- | 900 | b.full = rfixed_mul(b, wm0.active_time); |
|
- | 901 | a.full = rfixed_const(16); |
|
- | 902 | b.full = rfixed_div(b, a); |
|
- | 903 | a.full = rfixed_mul(wm0.worst_case_latency, |
|
- | 904 | wm0.consumption_rate); |
|
- | 905 | priority_mark02.full = a.full + b.full; |
|
- | 906 | } else { |
|
- | 907 | a.full = rfixed_mul(wm0.worst_case_latency, |
|
- | 908 | wm0.consumption_rate); |
|
- | 909 | b.full = rfixed_const(16 * 1000); |
|
- | 910 | priority_mark02.full = rfixed_div(a, b); |
|
- | 911 | } |
|
- | 912 | if (wm1.consumption_rate.full > fill_rate.full) { |
|
- | 913 | b.full = wm1.consumption_rate.full - fill_rate.full; |
|
- | 914 | b.full = rfixed_mul(b, wm1.active_time); |
|
- | 915 | a.full = rfixed_const(16); |
|
- | 916 | b.full = rfixed_div(b, a); |
|
- | 917 | a.full = rfixed_mul(wm1.worst_case_latency, |
|
- | 918 | wm1.consumption_rate); |
|
- | 919 | priority_mark12.full = a.full + b.full; |
|
- | 920 | } else { |
|
- | 921 | a.full = rfixed_mul(wm1.worst_case_latency, |
|
- | 922 | wm1.consumption_rate); |
|
- | 923 | b.full = rfixed_const(16 * 1000); |
|
- | 924 | priority_mark12.full = rfixed_div(a, b); |
|
- | 925 | } |
|
- | 926 | if (wm0.priority_mark.full > priority_mark02.full) |
|
- | 927 | priority_mark02.full = wm0.priority_mark.full; |
|
- | 928 | if (rfixed_trunc(priority_mark02) < 0) |
|
- | 929 | priority_mark02.full = 0; |
|
- | 930 | if (wm0.priority_mark_max.full > priority_mark02.full) |
|
- | 931 | priority_mark02.full = wm0.priority_mark_max.full; |
|
- | 932 | if (wm1.priority_mark.full > priority_mark12.full) |
|
- | 933 | priority_mark12.full = wm1.priority_mark.full; |
|
- | 934 | if (rfixed_trunc(priority_mark12) < 0) |
|
- | 935 | priority_mark12.full = 0; |
|
- | 936 | if (wm1.priority_mark_max.full > priority_mark12.full) |
|
- | 937 | priority_mark12.full = wm1.priority_mark_max.full; |
|
- | 938 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
|
- | 939 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
|
- | 940 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
|
- | 941 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
|
- | 942 | } else if (mode0) { |
|
- | 943 | if (rfixed_trunc(wm0.dbpp) > 64) |
|
- | 944 | a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); |
|
- | 945 | else |
|
- | 946 | a.full = wm0.num_line_pair.full; |
|
- | 947 | fill_rate.full = rfixed_div(wm0.sclk, a); |
|
- | 948 | if (wm0.consumption_rate.full > fill_rate.full) { |
|
- | 949 | b.full = wm0.consumption_rate.full - fill_rate.full; |
|
- | 950 | b.full = rfixed_mul(b, wm0.active_time); |
|
- | 951 | a.full = rfixed_const(16); |
|
- | 952 | b.full = rfixed_div(b, a); |
|
- | 953 | a.full = rfixed_mul(wm0.worst_case_latency, |
|
- | 954 | wm0.consumption_rate); |
|
- | 955 | priority_mark02.full = a.full + b.full; |
|
- | 956 | } else { |
|
- | 957 | a.full = rfixed_mul(wm0.worst_case_latency, |
|
- | 958 | wm0.consumption_rate); |
|
- | 959 | b.full = rfixed_const(16); |
|
- | 960 | priority_mark02.full = rfixed_div(a, b); |
|
- | 961 | } |
|
- | 962 | if (wm0.priority_mark.full > priority_mark02.full) |
|
- | 963 | priority_mark02.full = wm0.priority_mark.full; |
|
- | 964 | if (rfixed_trunc(priority_mark02) < 0) |
|
- | 965 | priority_mark02.full = 0; |
|
- | 966 | if (wm0.priority_mark_max.full > priority_mark02.full) |
|
- | 967 | priority_mark02.full = wm0.priority_mark_max.full; |
|
- | 968 | WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
|
- | 969 | WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
|
- | 970 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
|
- | 971 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
|
- | 972 | } else { |
|
- | 973 | if (rfixed_trunc(wm1.dbpp) > 64) |
|
- | 974 | a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); |
|
- | 975 | else |
|
- | 976 | a.full = wm1.num_line_pair.full; |
|
- | 977 | fill_rate.full = rfixed_div(wm1.sclk, a); |
|
- | 978 | if (wm1.consumption_rate.full > fill_rate.full) { |
|
- | 979 | b.full = wm1.consumption_rate.full - fill_rate.full; |
|
- | 980 | b.full = rfixed_mul(b, wm1.active_time); |
|
- | 981 | a.full = rfixed_const(16); |
|
- | 982 | b.full = rfixed_div(b, a); |
|
- | 983 | a.full = rfixed_mul(wm1.worst_case_latency, |
|
- | 984 | wm1.consumption_rate); |
|
- | 985 | priority_mark12.full = a.full + b.full; |
|
- | 986 | } else { |
|
- | 987 | a.full = rfixed_mul(wm1.worst_case_latency, |
|
- | 988 | wm1.consumption_rate); |
|
- | 989 | b.full = rfixed_const(16 * 1000); |
|
- | 990 | priority_mark12.full = rfixed_div(a, b); |
|
- | 991 | } |
|
- | 992 | if (wm1.priority_mark.full > priority_mark12.full) |
|
- | 993 | priority_mark12.full = wm1.priority_mark.full; |
|
- | 994 | if (rfixed_trunc(priority_mark12) < 0) |
|
- | 995 | priority_mark12.full = 0; |
|
- | 996 | if (wm1.priority_mark_max.full > priority_mark12.full) |
|
- | 997 | priority_mark12.full = wm1.priority_mark_max.full; |
|
- | 998 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
|
- | 999 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
|
- | 1000 | WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
|
561 | }; |
1001 | WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
562 | 1002 | } |
|
- | 1003 | } |
|
- | 1004 | ||
563 | 1005 | void rv515_bandwidth_update(struct radeon_device *rdev) |
|
Line -... | Line 1006... | ||
- | 1006 | { |
|
564 | 1007 | uint32_t tmp; |
|
- | 1008 | struct drm_display_mode *mode0 = NULL; |
|
- | 1009 | struct drm_display_mode *mode1 = NULL; |
|
- | 1010 | ||
- | 1011 | if (rdev->mode_info.crtcs[0]->base.enabled) |
|
565 | int rv515_init(struct radeon_device *rdev) |
1012 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
- | 1013 | if (rdev->mode_info.crtcs[1]->base.enabled) |
|
- | 1014 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
|
- | 1015 | /* |
|
- | 1016 | * Set display0/1 priority up in the memory controller for |
|
- | 1017 | * modes if the user specifies HIGH for displaypriority |
|
- | 1018 | * option. |
|
- | 1019 | */ |
|
- | 1020 | if (rdev->disp_priority == 2) { |
|
566 | { |
1021 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
- | 1022 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
|
- | 1023 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
|
- | 1024 | if (mode1) |
|
- | 1025 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
|
567 | dbgprintf("%s\n",__FUNCTION__); |
1026 | if (mode0) |