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Rev 1117 | Rev 1119 | ||
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Line 128... | Line 128... | ||
128 | rv370_pcie_gart_disable(rdev); |
128 | rv370_pcie_gart_disable(rdev); |
129 | radeon_gart_table_vram_free(rdev); |
129 | radeon_gart_table_vram_free(rdev); |
130 | radeon_gart_fini(rdev); |
130 | radeon_gart_fini(rdev); |
131 | } |
131 | } |
Line -... | Line 132... | ||
- | 132 | ||
Line 132... | Line 133... | ||
132 | 133 | #endif |
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133 | 134 | ||
134 | /* |
135 | /* |
135 | * Global GPU functions |
136 | * Global GPU functions |
136 | */ |
137 | */ |
137 | void rv515_ring_start(struct radeon_device *rdev) |
138 | void rv515_ring_start(struct radeon_device *rdev) |
138 | { |
139 | { |
Line -... | Line 140... | ||
- | 140 | unsigned gb_tile_config; |
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139 | unsigned gb_tile_config; |
141 | int r; |
140 | int r; |
142 | |
141 | 143 | dbgprintf("%s\n\r",__FUNCTION__); |
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142 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
144 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
143 | gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16; |
145 | gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16; |
Line 226... | Line 228... | ||
226 | R300_GEOMETRY_ROUND_NEAREST | |
228 | R300_GEOMETRY_ROUND_NEAREST | |
227 | R300_COLOR_ROUND_NEAREST); |
229 | R300_COLOR_ROUND_NEAREST); |
228 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
230 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
229 | radeon_ring_write(rdev, 0); |
231 | radeon_ring_write(rdev, 0); |
230 | radeon_ring_unlock_commit(rdev); |
232 | radeon_ring_unlock_commit(rdev); |
- | 233 | ||
- | 234 | dbgprintf("done %s\n\r",__FUNCTION__); |
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- | 235 | ||
231 | } |
236 | } |
Line 232... | Line 237... | ||
232 | 237 | ||
233 | void rv515_errata(struct radeon_device *rdev) |
238 | void rv515_errata(struct radeon_device *rdev) |
234 | { |
239 | { |
Line 249... | Line 254... | ||
249 | DRM_UDELAY(1); |
254 | DRM_UDELAY(1); |
250 | } |
255 | } |
251 | return -1; |
256 | return -1; |
252 | } |
257 | } |
Line -... | Line 258... | ||
- | 258 | ||
253 | 259 | #if 0 |
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254 | void rv515_gpu_init(struct radeon_device *rdev) |
260 | void rv515_gpu_init(struct radeon_device *rdev) |
255 | { |
261 | { |
Line 256... | Line 262... | ||
256 | unsigned pipe_select_current, gb_pipe_select, tmp; |
262 | unsigned pipe_select_current, gb_pipe_select, tmp; |
Line 338... | Line 344... | ||
338 | tmp = RREG32(RADEON_RBBM_STATUS); |
344 | tmp = RREG32(RADEON_RBBM_STATUS); |
339 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
345 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
340 | return -1; |
346 | return -1; |
341 | } |
347 | } |
Line 342... | Line -... | ||
342 | - | ||
343 | 348 | ||
344 | int rv515_gpu_reset(struct radeon_device *rdev) |
349 | int rv515_gpu_reset(struct radeon_device *rdev) |
345 | { |
350 | { |
Line 346... | Line 351... | ||
346 | uint32_t status; |
351 | uint32_t status; |
Line 372... | Line 377... | ||
372 | } |
377 | } |
373 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
378 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
374 | return 0; |
379 | return 0; |
375 | } |
380 | } |
Line 376... | Line -... | ||
376 | - | ||
Line 377... | Line 381... | ||
377 | #if 0 |
381 | |
378 | 382 | ||
379 | /* |
383 | /* |
380 | * VRAM info |
384 | * VRAM info |
Line 407... | Line 411... | ||
407 | 411 | ||
408 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
412 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
409 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
413 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
Line 410... | Line -... | ||
410 | } |
- | |
Line 411... | Line 414... | ||
411 | 414 | } |
|
412 | #endif |
415 | |
413 | 416 | ||
414 | /* |
417 | /* |