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Line 128... Line 128...
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	rv370_pcie_gart_disable(rdev);
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	rv370_pcie_gart_disable(rdev);
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	radeon_gart_table_vram_free(rdev);
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	radeon_gart_table_vram_free(rdev);
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	radeon_gart_fini(rdev);
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	radeon_gart_fini(rdev);
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}
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}
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#endif
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/*
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/*
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 * Global GPU functions
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 * Global GPU functions
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 */
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 */
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void rv515_ring_start(struct radeon_device *rdev)
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void rv515_ring_start(struct radeon_device *rdev)
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{
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{
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	unsigned gb_tile_config;
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	unsigned gb_tile_config;
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	int r;
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	int r;
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    dbgprintf("%s\n\r",__FUNCTION__);
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	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
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	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
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	gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
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	gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
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			  R300_GEOMETRY_ROUND_NEAREST |
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			  R300_GEOMETRY_ROUND_NEAREST |
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			  R300_COLOR_ROUND_NEAREST);
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			  R300_COLOR_ROUND_NEAREST);
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	radeon_ring_write(rdev, PACKET0(0x20C8, 0));
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	radeon_ring_write(rdev, PACKET0(0x20C8, 0));
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	radeon_ring_write(rdev, 0);
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	radeon_ring_write(rdev, 0);
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	radeon_ring_unlock_commit(rdev);
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	radeon_ring_unlock_commit(rdev);
-
 
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-
 
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    dbgprintf("done %s\n\r",__FUNCTION__);
-
 
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}
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}
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void rv515_errata(struct radeon_device *rdev)
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void rv515_errata(struct radeon_device *rdev)
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{
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{
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		DRM_UDELAY(1);
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		DRM_UDELAY(1);
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	}
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	}
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	return -1;
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	return -1;
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}
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}
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#if 0
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void rv515_gpu_init(struct radeon_device *rdev)
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void rv515_gpu_init(struct radeon_device *rdev)
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{
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{
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	unsigned pipe_select_current, gb_pipe_select, tmp;
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	unsigned pipe_select_current, gb_pipe_select, tmp;
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	tmp = RREG32(RADEON_RBBM_STATUS);
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	tmp = RREG32(RADEON_RBBM_STATUS);
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	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
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	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
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	return -1;
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	return -1;
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}
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}
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-
 
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int rv515_gpu_reset(struct radeon_device *rdev)
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int rv515_gpu_reset(struct radeon_device *rdev)
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{
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{
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	uint32_t status;
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	uint32_t status;
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	}
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	}
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	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
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	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
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	return 0;
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	return 0;
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}
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}
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-
 
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#if 0
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/*
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/*
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 * VRAM info
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 * VRAM info
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411
 
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	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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}
-
 
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}
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#endif
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/*
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/*