Rev 1430 | Rev 2005 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1430 | Rev 1963 | ||
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Line 25... | Line 25... | ||
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include "drmP.h" |
28 | #include "drmP.h" |
29 | #include "radeon.h" |
29 | #include "radeon.h" |
- | 30 | #include "radeon_asic.h" |
|
30 | #include "atom.h" |
31 | #include "atom.h" |
31 | #include "rs690d.h" |
32 | #include "rs690d.h" |
Line 32... | Line 33... | ||
32 | 33 | ||
33 | static int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
34 | static int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
Line 45... | Line 46... | ||
45 | return -1; |
46 | return -1; |
46 | } |
47 | } |
Line 47... | Line 48... | ||
47 | 48 | ||
48 | static void rs690_gpu_init(struct radeon_device *rdev) |
49 | static void rs690_gpu_init(struct radeon_device *rdev) |
49 | { |
- | |
50 | /* FIXME: HDP same place on rs690 ? */ |
- | |
51 | r100_hdp_reset(rdev); |
50 | { |
52 | /* FIXME: is this correct ? */ |
51 | /* FIXME: is this correct ? */ |
53 | r420_pipes_init(rdev); |
52 | r420_pipes_init(rdev); |
54 | if (rs690_mc_wait_for_idle(rdev)) { |
53 | if (rs690_mc_wait_for_idle(rdev)) { |
55 | printk(KERN_WARNING "Failed to wait MC idle while " |
54 | printk(KERN_WARNING "Failed to wait MC idle while " |
56 | "programming pipes. Bad things might happen.\n"); |
55 | "programming pipes. Bad things might happen.\n"); |
57 | } |
56 | } |
Line -... | Line 57... | ||
- | 57 | } |
|
- | 58 | ||
- | 59 | union igp_info { |
|
- | 60 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; |
|
- | 61 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; |
|
58 | } |
62 | }; |
59 | 63 | ||
60 | void rs690_pm_info(struct radeon_device *rdev) |
64 | void rs690_pm_info(struct radeon_device *rdev) |
61 | { |
- | |
62 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
- | |
63 | struct _ATOM_INTEGRATED_SYSTEM_INFO *info; |
65 | { |
64 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2; |
66 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
65 | void *ptr; |
67 | union igp_info *info; |
66 | uint16_t data_offset; |
68 | uint16_t data_offset; |
Line 67... | Line 69... | ||
67 | uint8_t frev, crev; |
69 | uint8_t frev, crev; |
68 | fixed20_12 tmp; |
70 | fixed20_12 tmp; |
69 | 71 | ||
70 | atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, |
- | |
71 | &frev, &crev, &data_offset); |
- | |
- | 72 | if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, |
|
72 | ptr = rdev->mode_info.atom_context->bios + data_offset; |
73 | &frev, &crev, &data_offset)) { |
73 | info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr; |
74 | info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); |
74 | info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr; |
75 | |
75 | /* Get various system informations from bios */ |
76 | /* Get various system informations from bios */ |
76 | switch (crev) { |
77 | switch (crev) { |
77 | case 1: |
78 | case 1: |
- | 79 | tmp.full = dfixed_const(100); |
|
78 | tmp.full = rfixed_const(100); |
80 | rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); |
- | 81 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
|
- | 82 | if (le16_to_cpu(info->info.usK8MemoryClock)) |
|
- | 83 | rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); |
|
- | 84 | else if (rdev->clock.default_mclk) { |
|
- | 85 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); |
|
79 | rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock); |
86 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); |
80 | rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
87 | } else |
81 | rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock)); |
88 | rdev->pm.igp_system_mclk.full = dfixed_const(400); |
82 | rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock)); |
89 | rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); |
83 | rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth); |
90 | rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); |
84 | break; |
91 | break; |
85 | case 2: |
92 | case 2: |
- | 93 | tmp.full = dfixed_const(100); |
|
86 | tmp.full = rfixed_const(100); |
94 | rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); |
- | 95 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
|
- | 96 | if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) |
|
- | 97 | rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); |
|
- | 98 | else if (rdev->clock.default_mclk) |
|
87 | rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock); |
99 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); |
88 | rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
100 | else |
89 | rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock); |
101 | rdev->pm.igp_system_mclk.full = dfixed_const(66700); |
90 | rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); |
102 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); |
91 | rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq); |
103 | rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); |
92 | rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp); |
104 | rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); |
93 | rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth)); |
- | |
94 | break; |
105 | rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); |
95 | default: |
- | |
96 | tmp.full = rfixed_const(100); |
106 | break; |
97 | /* We assume the slower possible clock ie worst case */ |
- | |
98 | /* DDR 333Mhz */ |
107 | default: |
99 | rdev->pm.igp_sideport_mclk.full = rfixed_const(333); |
- | |
100 | /* FIXME: system clock ? */ |
108 | /* We assume the slower possible clock ie worst case */ |
101 | rdev->pm.igp_system_mclk.full = rfixed_const(100); |
109 | rdev->pm.igp_sideport_mclk.full = dfixed_const(200); |
102 | rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); |
110 | rdev->pm.igp_system_mclk.full = dfixed_const(200); |
103 | rdev->pm.igp_ht_link_clk.full = rfixed_const(200); |
111 | rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); |
104 | rdev->pm.igp_ht_link_width.full = rfixed_const(8); |
112 | rdev->pm.igp_ht_link_width.full = dfixed_const(8); |
- | 113 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
|
- | 114 | break; |
|
- | 115 | } |
|
- | 116 | } else { |
|
- | 117 | /* We assume the slower possible clock ie worst case */ |
|
- | 118 | rdev->pm.igp_sideport_mclk.full = dfixed_const(200); |
|
- | 119 | rdev->pm.igp_system_mclk.full = dfixed_const(200); |
|
- | 120 | rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); |
|
105 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
121 | rdev->pm.igp_ht_link_width.full = dfixed_const(8); |
106 | break; |
122 | DRM_ERROR("No integrated system info for your GPU, using safe default\n"); |
107 | } |
123 | } |
108 | /* Compute various bandwidth */ |
124 | /* Compute various bandwidth */ |
109 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ |
125 | /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ |
110 | tmp.full = rfixed_const(4); |
126 | tmp.full = dfixed_const(4); |
111 | rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp); |
127 | rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); |
112 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 |
128 | /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 |
113 | * = ht_clk * ht_width / 5 |
129 | * = ht_clk * ht_width / 5 |
114 | */ |
130 | */ |
115 | tmp.full = rfixed_const(5); |
131 | tmp.full = dfixed_const(5); |
116 | rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk, |
132 | rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, |
117 | rdev->pm.igp_ht_link_width); |
133 | rdev->pm.igp_ht_link_width); |
118 | rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp); |
134 | rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); |
119 | if (tmp.full < rdev->pm.max_bandwidth.full) { |
135 | if (tmp.full < rdev->pm.max_bandwidth.full) { |
120 | /* HT link is a limiting factor */ |
136 | /* HT link is a limiting factor */ |
121 | rdev->pm.max_bandwidth.full = tmp.full; |
137 | rdev->pm.max_bandwidth.full = tmp.full; |
122 | } |
138 | } |
123 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 |
139 | /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 |
124 | * = (sideport_clk * 14) / 10 |
140 | * = (sideport_clk * 14) / 10 |
125 | */ |
141 | */ |
126 | tmp.full = rfixed_const(14); |
142 | tmp.full = dfixed_const(14); |
127 | rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp); |
143 | rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); |
Line 128... | Line 144... | ||
128 | tmp.full = rfixed_const(10); |
144 | tmp.full = dfixed_const(10); |
129 | rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); |
145 | rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); |
130 | } |
- | |
131 | 146 | } |
|
Line 132... | Line 147... | ||
132 | void rs690_mc_init(struct radeon_device *rdev) |
147 | |
133 | { |
148 | void rs690_mc_init(struct radeon_device *rdev) |
134 | fixed20_12 a; |
149 | { |
135 | u64 base; |
150 | u64 base; |
136 | 151 | ||
137 | rs400_gart_adjust_size(rdev); |
152 | rs400_gart_adjust_size(rdev); |
138 | rdev->mc.vram_is_ddr = true; |
153 | rdev->mc.vram_is_ddr = true; |
139 | rdev->mc.vram_width = 128; |
154 | rdev->mc.vram_width = 128; |
140 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
155 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
141 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
156 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
142 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
- | |
143 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
- | |
144 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
- | |
145 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); |
- | |
146 | base = G_000100_MC_FB_START(base) << 16; |
- | |
147 | rs690_pm_info(rdev); |
- | |
148 | /* FIXME: we should enforce default clock in case GPU is not in |
- | |
149 | * default setup |
- | |
150 | */ |
- | |
151 | a.full = rfixed_const(100); |
- | |
152 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
157 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
- | 158 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
|
153 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
159 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
- | 160 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); |
|
154 | a.full = rfixed_const(16); |
161 | base = G_000100_MC_FB_START(base) << 16; |
- | 162 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
|
155 | /* core_bandwidth = sclk(Mhz) * 16 */ |
163 | rs690_pm_info(rdev); |
Line 156... | Line 164... | ||
156 | rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); |
164 | radeon_vram_location(rdev, &rdev->mc, base); |
157 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
165 | rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; |
158 | radeon_vram_location(rdev, &rdev->mc, base); |
166 | radeon_gtt_location(rdev, &rdev->mc); |
Line 222... | Line 230... | ||
222 | { |
230 | { |
223 | struct drm_display_mode *mode = &crtc->base.mode; |
231 | struct drm_display_mode *mode = &crtc->base.mode; |
224 | fixed20_12 a, b, c; |
232 | fixed20_12 a, b, c; |
225 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
233 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
226 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
234 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
227 | /* FIXME: detect IGP with sideport memory, i don't think there is any |
- | |
228 | * such product available |
- | |
229 | */ |
- | |
230 | bool sideport = false; |
- | |
Line 231... | Line 235... | ||
231 | 235 | ||
232 | if (!crtc->base.enabled) { |
236 | if (!crtc->base.enabled) { |
233 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
237 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
234 | wm->lb_request_fifo_depth = 4; |
238 | wm->lb_request_fifo_depth = 4; |
235 | return; |
239 | return; |
Line 236... | Line 240... | ||
236 | } |
240 | } |
237 | 241 | ||
238 | if (crtc->vsc.full > rfixed_const(2)) |
242 | if (crtc->vsc.full > dfixed_const(2)) |
239 | wm->num_line_pair.full = rfixed_const(2); |
243 | wm->num_line_pair.full = dfixed_const(2); |
Line 240... | Line 244... | ||
240 | else |
244 | else |
241 | wm->num_line_pair.full = rfixed_const(1); |
245 | wm->num_line_pair.full = dfixed_const(1); |
242 | 246 | ||
243 | b.full = rfixed_const(mode->crtc_hdisplay); |
247 | b.full = dfixed_const(mode->crtc_hdisplay); |
244 | c.full = rfixed_const(256); |
248 | c.full = dfixed_const(256); |
245 | a.full = rfixed_div(b, c); |
249 | a.full = dfixed_div(b, c); |
246 | request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); |
250 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); |
247 | request_fifo_depth.full = rfixed_ceil(request_fifo_depth); |
251 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); |
248 | if (a.full < rfixed_const(4)) { |
252 | if (a.full < dfixed_const(4)) { |
249 | wm->lb_request_fifo_depth = 4; |
253 | wm->lb_request_fifo_depth = 4; |
Line 250... | Line 254... | ||
250 | } else { |
254 | } else { |
251 | wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); |
255 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
252 | } |
256 | } |
253 | 257 | ||
254 | /* Determine consumption rate |
258 | /* Determine consumption rate |
255 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
259 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
256 | * vtaps = number of vertical taps, |
260 | * vtaps = number of vertical taps, |
257 | * vsc = vertical scaling ratio, defined as source/destination |
261 | * vsc = vertical scaling ratio, defined as source/destination |
258 | * hsc = horizontal scaling ration, defined as source/destination |
262 | * hsc = horizontal scaling ration, defined as source/destination |
259 | */ |
263 | */ |
260 | a.full = rfixed_const(mode->clock); |
264 | a.full = dfixed_const(mode->clock); |
261 | b.full = rfixed_const(1000); |
265 | b.full = dfixed_const(1000); |
262 | a.full = rfixed_div(a, b); |
266 | a.full = dfixed_div(a, b); |
263 | pclk.full = rfixed_div(b, a); |
267 | pclk.full = dfixed_div(b, a); |
264 | if (crtc->rmx_type != RMX_OFF) { |
268 | if (crtc->rmx_type != RMX_OFF) { |
265 | b.full = rfixed_const(2); |
269 | b.full = dfixed_const(2); |
266 | if (crtc->vsc.full > b.full) |
270 | if (crtc->vsc.full > b.full) |
267 | b.full = crtc->vsc.full; |
271 | b.full = crtc->vsc.full; |
268 | b.full = rfixed_mul(b, crtc->hsc); |
272 | b.full = dfixed_mul(b, crtc->hsc); |
269 | c.full = rfixed_const(2); |
273 | c.full = dfixed_const(2); |
270 | b.full = rfixed_div(b, c); |
274 | b.full = dfixed_div(b, c); |
271 | consumption_time.full = rfixed_div(pclk, b); |
275 | consumption_time.full = dfixed_div(pclk, b); |
272 | } else { |
276 | } else { |
Line 273... | Line 277... | ||
273 | consumption_time.full = pclk.full; |
277 | consumption_time.full = pclk.full; |
274 | } |
278 | } |
275 | a.full = rfixed_const(1); |
279 | a.full = dfixed_const(1); |
276 | wm->consumption_rate.full = rfixed_div(a, consumption_time); |
280 | wm->consumption_rate.full = dfixed_div(a, consumption_time); |
277 | 281 | ||
278 | 282 | ||
279 | /* Determine line time |
283 | /* Determine line time |
Line 280... | Line 284... | ||
280 | * LineTime = total time for one line of displayhtotal |
284 | * LineTime = total time for one line of displayhtotal |
281 | * LineTime = total number of horizontal pixels |
285 | * LineTime = total number of horizontal pixels |
282 | * pclk = pixel clock period(ns) |
286 | * pclk = pixel clock period(ns) |
283 | */ |
287 | */ |
284 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
288 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
285 | line_time.full = rfixed_mul(a, pclk); |
289 | line_time.full = dfixed_mul(a, pclk); |
286 | 290 | ||
287 | /* Determine active time |
291 | /* Determine active time |
288 | * ActiveTime = time of active region of display within one line, |
292 | * ActiveTime = time of active region of display within one line, |
Line 289... | Line 293... | ||
289 | * hactive = total number of horizontal active pixels |
293 | * hactive = total number of horizontal active pixels |
290 | * htotal = total number of horizontal pixels |
294 | * htotal = total number of horizontal pixels |
291 | */ |
295 | */ |
292 | a.full = rfixed_const(crtc->base.mode.crtc_htotal); |
296 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
293 | b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
297 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
294 | wm->active_time.full = rfixed_mul(line_time, b); |
298 | wm->active_time.full = dfixed_mul(line_time, b); |
295 | wm->active_time.full = rfixed_div(wm->active_time, a); |
299 | wm->active_time.full = dfixed_div(wm->active_time, a); |
296 | 300 | ||
297 | /* Maximun bandwidth is the minimun bandwidth of all component */ |
301 | /* Maximun bandwidth is the minimun bandwidth of all component */ |
298 | rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; |
302 | rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; |
299 | if (sideport) { |
303 | if (rdev->mc.igp_sideport_enabled) { |
300 | if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && |
304 | if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && |
301 | rdev->pm.sideport_bandwidth.full) |
305 | rdev->pm.sideport_bandwidth.full) |
302 | rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; |
306 | rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; |
303 | read_delay_latency.full = rfixed_const(370 * 800 * 1000); |
307 | read_delay_latency.full = dfixed_const(370 * 800 * 1000); |
304 | read_delay_latency.full = rfixed_div(read_delay_latency, |
308 | read_delay_latency.full = dfixed_div(read_delay_latency, |
305 | rdev->pm.igp_sideport_mclk); |
309 | rdev->pm.igp_sideport_mclk); |
306 | } else { |
310 | } else { |
Line 307... | Line 311... | ||
307 | if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && |
311 | if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && |
308 | rdev->pm.k8_bandwidth.full) |
312 | rdev->pm.k8_bandwidth.full) |
309 | rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; |
313 | rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; |
310 | if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && |
314 | if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && |
311 | rdev->pm.ht_bandwidth.full) |
315 | rdev->pm.ht_bandwidth.full) |
312 | rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; |
316 | rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; |
313 | read_delay_latency.full = rfixed_const(5000); |
317 | read_delay_latency.full = dfixed_const(5000); |
314 | } |
318 | } |
315 | 319 | ||
316 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ |
320 | /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ |
317 | a.full = rfixed_const(16); |
321 | a.full = dfixed_const(16); |
318 | rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a); |
322 | rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a); |
319 | a.full = rfixed_const(1000); |
323 | a.full = dfixed_const(1000); |
320 | rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk); |
324 | rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk); |
Line 321... | Line 325... | ||
321 | /* Determine chunk time |
325 | /* Determine chunk time |
322 | * ChunkTime = the time it takes the DCP to send one chunk of data |
326 | * ChunkTime = the time it takes the DCP to send one chunk of data |
323 | * to the LB which consists of pipeline delay and inter chunk gap |
327 | * to the LB which consists of pipeline delay and inter chunk gap |
324 | * sclk = system clock(ns) |
328 | * sclk = system clock(ns) |
325 | */ |
329 | */ |
326 | a.full = rfixed_const(256 * 13); |
330 | a.full = dfixed_const(256 * 13); |
327 | chunk_time.full = rfixed_mul(rdev->pm.sclk, a); |
331 | chunk_time.full = dfixed_mul(rdev->pm.sclk, a); |
328 | a.full = rfixed_const(10); |
332 | a.full = dfixed_const(10); |
329 | chunk_time.full = rfixed_div(chunk_time, a); |
333 | chunk_time.full = dfixed_div(chunk_time, a); |
330 | 334 | ||
331 | /* Determine the worst case latency |
335 | /* Determine the worst case latency |
332 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
336 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
333 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
337 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
334 | * to return data |
338 | * to return data |
335 | * READ_DELAY_IDLE_MAX = constant of 1us |
339 | * READ_DELAY_IDLE_MAX = constant of 1us |
336 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
340 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
337 | * which consists of pipeline delay and inter chunk gap |
341 | * which consists of pipeline delay and inter chunk gap |
Line 338... | Line 342... | ||
338 | */ |
342 | */ |
339 | if (rfixed_trunc(wm->num_line_pair) > 1) { |
343 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
Line 354... | Line 358... | ||
354 | * LineTime = total time for one line of display |
358 | * LineTime = total time for one line of display |
355 | * ChunkTime = the time it takes the DCP to send one chunk |
359 | * ChunkTime = the time it takes the DCP to send one chunk |
356 | * of data to the LB which consists of |
360 | * of data to the LB which consists of |
357 | * pipeline delay and inter chunk gap |
361 | * pipeline delay and inter chunk gap |
358 | */ |
362 | */ |
359 | if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { |
363 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
360 | tolerable_latency.full = line_time.full; |
364 | tolerable_latency.full = line_time.full; |
361 | } else { |
365 | } else { |
362 | tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); |
366 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
363 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
367 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
364 | tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); |
368 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
365 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
369 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
366 | } |
370 | } |
367 | /* We assume worst case 32bits (4 bytes) */ |
371 | /* We assume worst case 32bits (4 bytes) */ |
368 | wm->dbpp.full = rfixed_const(4 * 8); |
372 | wm->dbpp.full = dfixed_const(4 * 8); |
Line 369... | Line 373... | ||
369 | 373 | ||
370 | /* Determine the maximum priority mark |
374 | /* Determine the maximum priority mark |
371 | * width = viewport width in pixels |
375 | * width = viewport width in pixels |
372 | */ |
376 | */ |
373 | a.full = rfixed_const(16); |
377 | a.full = dfixed_const(16); |
374 | wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); |
378 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
375 | wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); |
379 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); |
Line 376... | Line 380... | ||
376 | wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); |
380 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); |
377 | 381 | ||
378 | /* Determine estimated width */ |
382 | /* Determine estimated width */ |
379 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
383 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
380 | estimated_width.full = rfixed_div(estimated_width, consumption_time); |
384 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
381 | if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
385 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
382 | wm->priority_mark.full = rfixed_const(10); |
386 | wm->priority_mark.full = dfixed_const(10); |
383 | } else { |
387 | } else { |
384 | a.full = rfixed_const(16); |
388 | a.full = dfixed_const(16); |
385 | wm->priority_mark.full = rfixed_div(estimated_width, a); |
389 | wm->priority_mark.full = dfixed_div(estimated_width, a); |
386 | wm->priority_mark.full = rfixed_ceil(wm->priority_mark); |
390 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
387 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
391 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
Line 388... | Line 392... | ||
388 | } |
392 | } |
Line 393... | Line 397... | ||
393 | struct drm_display_mode *mode0 = NULL; |
397 | struct drm_display_mode *mode0 = NULL; |
394 | struct drm_display_mode *mode1 = NULL; |
398 | struct drm_display_mode *mode1 = NULL; |
395 | struct rs690_watermark wm0; |
399 | struct rs690_watermark wm0; |
396 | struct rs690_watermark wm1; |
400 | struct rs690_watermark wm1; |
397 | u32 tmp; |
401 | u32 tmp; |
- | 402 | u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); |
|
- | 403 | u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); |
|
398 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
404 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
399 | fixed20_12 a, b; |
405 | fixed20_12 a, b; |
Line -... | Line 406... | ||
- | 406 | ||
- | 407 | radeon_update_display_priority(rdev); |
|
400 | 408 | ||
401 | if (rdev->mode_info.crtcs[0]->base.enabled) |
409 | if (rdev->mode_info.crtcs[0]->base.enabled) |
402 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
410 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
403 | if (rdev->mode_info.crtcs[1]->base.enabled) |
411 | if (rdev->mode_info.crtcs[1]->base.enabled) |
404 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
412 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
405 | /* |
413 | /* |
406 | * Set display0/1 priority up in the memory controller for |
414 | * Set display0/1 priority up in the memory controller for |
407 | * modes if the user specifies HIGH for displaypriority |
415 | * modes if the user specifies HIGH for displaypriority |
408 | * option. |
416 | * option. |
409 | */ |
417 | */ |
- | 418 | if ((rdev->disp_priority == 2) && |
|
410 | if (rdev->disp_priority == 2) { |
419 | ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { |
411 | tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); |
420 | tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); |
412 | tmp &= C_000104_MC_DISP0R_INIT_LAT; |
421 | tmp &= C_000104_MC_DISP0R_INIT_LAT; |
413 | tmp &= C_000104_MC_DISP1R_INIT_LAT; |
422 | tmp &= C_000104_MC_DISP1R_INIT_LAT; |
414 | if (mode0) |
423 | if (mode0) |
Line 430... | Line 439... | ||
430 | tmp = (wm0.lb_request_fifo_depth - 1); |
439 | tmp = (wm0.lb_request_fifo_depth - 1); |
431 | tmp |= (wm1.lb_request_fifo_depth - 1) << 16; |
440 | tmp |= (wm1.lb_request_fifo_depth - 1) << 16; |
432 | WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); |
441 | WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); |
Line 433... | Line 442... | ||
433 | 442 | ||
434 | if (mode0 && mode1) { |
443 | if (mode0 && mode1) { |
435 | if (rfixed_trunc(wm0.dbpp) > 64) |
444 | if (dfixed_trunc(wm0.dbpp) > 64) |
436 | a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); |
445 | a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); |
437 | else |
446 | else |
438 | a.full = wm0.num_line_pair.full; |
447 | a.full = wm0.num_line_pair.full; |
439 | if (rfixed_trunc(wm1.dbpp) > 64) |
448 | if (dfixed_trunc(wm1.dbpp) > 64) |
440 | b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); |
449 | b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); |
441 | else |
450 | else |
442 | b.full = wm1.num_line_pair.full; |
451 | b.full = wm1.num_line_pair.full; |
443 | a.full += b.full; |
452 | a.full += b.full; |
444 | fill_rate.full = rfixed_div(wm0.sclk, a); |
453 | fill_rate.full = dfixed_div(wm0.sclk, a); |
445 | if (wm0.consumption_rate.full > fill_rate.full) { |
454 | if (wm0.consumption_rate.full > fill_rate.full) { |
446 | b.full = wm0.consumption_rate.full - fill_rate.full; |
455 | b.full = wm0.consumption_rate.full - fill_rate.full; |
447 | b.full = rfixed_mul(b, wm0.active_time); |
456 | b.full = dfixed_mul(b, wm0.active_time); |
448 | a.full = rfixed_mul(wm0.worst_case_latency, |
457 | a.full = dfixed_mul(wm0.worst_case_latency, |
449 | wm0.consumption_rate); |
458 | wm0.consumption_rate); |
450 | a.full = a.full + b.full; |
459 | a.full = a.full + b.full; |
451 | b.full = rfixed_const(16 * 1000); |
460 | b.full = dfixed_const(16 * 1000); |
452 | priority_mark02.full = rfixed_div(a, b); |
461 | priority_mark02.full = dfixed_div(a, b); |
453 | } else { |
462 | } else { |
454 | a.full = rfixed_mul(wm0.worst_case_latency, |
463 | a.full = dfixed_mul(wm0.worst_case_latency, |
455 | wm0.consumption_rate); |
464 | wm0.consumption_rate); |
456 | b.full = rfixed_const(16 * 1000); |
465 | b.full = dfixed_const(16 * 1000); |
457 | priority_mark02.full = rfixed_div(a, b); |
466 | priority_mark02.full = dfixed_div(a, b); |
458 | } |
467 | } |
459 | if (wm1.consumption_rate.full > fill_rate.full) { |
468 | if (wm1.consumption_rate.full > fill_rate.full) { |
460 | b.full = wm1.consumption_rate.full - fill_rate.full; |
469 | b.full = wm1.consumption_rate.full - fill_rate.full; |
461 | b.full = rfixed_mul(b, wm1.active_time); |
470 | b.full = dfixed_mul(b, wm1.active_time); |
462 | a.full = rfixed_mul(wm1.worst_case_latency, |
471 | a.full = dfixed_mul(wm1.worst_case_latency, |
463 | wm1.consumption_rate); |
472 | wm1.consumption_rate); |
464 | a.full = a.full + b.full; |
473 | a.full = a.full + b.full; |
465 | b.full = rfixed_const(16 * 1000); |
474 | b.full = dfixed_const(16 * 1000); |
466 | priority_mark12.full = rfixed_div(a, b); |
475 | priority_mark12.full = dfixed_div(a, b); |
467 | } else { |
476 | } else { |
468 | a.full = rfixed_mul(wm1.worst_case_latency, |
477 | a.full = dfixed_mul(wm1.worst_case_latency, |
469 | wm1.consumption_rate); |
478 | wm1.consumption_rate); |
470 | b.full = rfixed_const(16 * 1000); |
479 | b.full = dfixed_const(16 * 1000); |
471 | priority_mark12.full = rfixed_div(a, b); |
480 | priority_mark12.full = dfixed_div(a, b); |
472 | } |
481 | } |
473 | if (wm0.priority_mark.full > priority_mark02.full) |
482 | if (wm0.priority_mark.full > priority_mark02.full) |
474 | priority_mark02.full = wm0.priority_mark.full; |
483 | priority_mark02.full = wm0.priority_mark.full; |
475 | if (rfixed_trunc(priority_mark02) < 0) |
484 | if (dfixed_trunc(priority_mark02) < 0) |
476 | priority_mark02.full = 0; |
485 | priority_mark02.full = 0; |
477 | if (wm0.priority_mark_max.full > priority_mark02.full) |
486 | if (wm0.priority_mark_max.full > priority_mark02.full) |
478 | priority_mark02.full = wm0.priority_mark_max.full; |
487 | priority_mark02.full = wm0.priority_mark_max.full; |
479 | if (wm1.priority_mark.full > priority_mark12.full) |
488 | if (wm1.priority_mark.full > priority_mark12.full) |
480 | priority_mark12.full = wm1.priority_mark.full; |
489 | priority_mark12.full = wm1.priority_mark.full; |
481 | if (rfixed_trunc(priority_mark12) < 0) |
490 | if (dfixed_trunc(priority_mark12) < 0) |
482 | priority_mark12.full = 0; |
491 | priority_mark12.full = 0; |
483 | if (wm1.priority_mark_max.full > priority_mark12.full) |
492 | if (wm1.priority_mark_max.full > priority_mark12.full) |
484 | priority_mark12.full = wm1.priority_mark_max.full; |
493 | priority_mark12.full = wm1.priority_mark_max.full; |
485 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
494 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
- | 495 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
|
486 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
496 | if (rdev->disp_priority == 2) { |
487 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
497 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
- | 498 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
|
488 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
499 | } |
489 | } else if (mode0) { |
500 | } else if (mode0) { |
490 | if (rfixed_trunc(wm0.dbpp) > 64) |
501 | if (dfixed_trunc(wm0.dbpp) > 64) |
491 | a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); |
502 | a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); |
492 | else |
503 | else |
493 | a.full = wm0.num_line_pair.full; |
504 | a.full = wm0.num_line_pair.full; |
494 | fill_rate.full = rfixed_div(wm0.sclk, a); |
505 | fill_rate.full = dfixed_div(wm0.sclk, a); |
495 | if (wm0.consumption_rate.full > fill_rate.full) { |
506 | if (wm0.consumption_rate.full > fill_rate.full) { |
496 | b.full = wm0.consumption_rate.full - fill_rate.full; |
507 | b.full = wm0.consumption_rate.full - fill_rate.full; |
497 | b.full = rfixed_mul(b, wm0.active_time); |
508 | b.full = dfixed_mul(b, wm0.active_time); |
498 | a.full = rfixed_mul(wm0.worst_case_latency, |
509 | a.full = dfixed_mul(wm0.worst_case_latency, |
499 | wm0.consumption_rate); |
510 | wm0.consumption_rate); |
500 | a.full = a.full + b.full; |
511 | a.full = a.full + b.full; |
501 | b.full = rfixed_const(16 * 1000); |
512 | b.full = dfixed_const(16 * 1000); |
502 | priority_mark02.full = rfixed_div(a, b); |
513 | priority_mark02.full = dfixed_div(a, b); |
503 | } else { |
514 | } else { |
504 | a.full = rfixed_mul(wm0.worst_case_latency, |
515 | a.full = dfixed_mul(wm0.worst_case_latency, |
505 | wm0.consumption_rate); |
516 | wm0.consumption_rate); |
506 | b.full = rfixed_const(16 * 1000); |
517 | b.full = dfixed_const(16 * 1000); |
507 | priority_mark02.full = rfixed_div(a, b); |
518 | priority_mark02.full = dfixed_div(a, b); |
508 | } |
519 | } |
509 | if (wm0.priority_mark.full > priority_mark02.full) |
520 | if (wm0.priority_mark.full > priority_mark02.full) |
510 | priority_mark02.full = wm0.priority_mark.full; |
521 | priority_mark02.full = wm0.priority_mark.full; |
511 | if (rfixed_trunc(priority_mark02) < 0) |
522 | if (dfixed_trunc(priority_mark02) < 0) |
512 | priority_mark02.full = 0; |
523 | priority_mark02.full = 0; |
513 | if (wm0.priority_mark_max.full > priority_mark02.full) |
524 | if (wm0.priority_mark_max.full > priority_mark02.full) |
514 | priority_mark02.full = wm0.priority_mark_max.full; |
- | |
515 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
525 | priority_mark02.full = wm0.priority_mark_max.full; |
516 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
526 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
517 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, |
527 | if (rdev->disp_priority == 2) |
518 | S_006D48_D2MODE_PRIORITY_A_OFF(1)); |
- | |
519 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, |
- | |
520 | S_006D4C_D2MODE_PRIORITY_B_OFF(1)); |
528 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
521 | } else { |
529 | } else if (mode1) { |
522 | if (rfixed_trunc(wm1.dbpp) > 64) |
530 | if (dfixed_trunc(wm1.dbpp) > 64) |
523 | a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); |
531 | a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); |
524 | else |
532 | else |
525 | a.full = wm1.num_line_pair.full; |
533 | a.full = wm1.num_line_pair.full; |
526 | fill_rate.full = rfixed_div(wm1.sclk, a); |
534 | fill_rate.full = dfixed_div(wm1.sclk, a); |
527 | if (wm1.consumption_rate.full > fill_rate.full) { |
535 | if (wm1.consumption_rate.full > fill_rate.full) { |
528 | b.full = wm1.consumption_rate.full - fill_rate.full; |
536 | b.full = wm1.consumption_rate.full - fill_rate.full; |
529 | b.full = rfixed_mul(b, wm1.active_time); |
537 | b.full = dfixed_mul(b, wm1.active_time); |
530 | a.full = rfixed_mul(wm1.worst_case_latency, |
538 | a.full = dfixed_mul(wm1.worst_case_latency, |
531 | wm1.consumption_rate); |
539 | wm1.consumption_rate); |
532 | a.full = a.full + b.full; |
540 | a.full = a.full + b.full; |
533 | b.full = rfixed_const(16 * 1000); |
541 | b.full = dfixed_const(16 * 1000); |
534 | priority_mark12.full = rfixed_div(a, b); |
542 | priority_mark12.full = dfixed_div(a, b); |
535 | } else { |
543 | } else { |
536 | a.full = rfixed_mul(wm1.worst_case_latency, |
544 | a.full = dfixed_mul(wm1.worst_case_latency, |
537 | wm1.consumption_rate); |
545 | wm1.consumption_rate); |
538 | b.full = rfixed_const(16 * 1000); |
546 | b.full = dfixed_const(16 * 1000); |
539 | priority_mark12.full = rfixed_div(a, b); |
547 | priority_mark12.full = dfixed_div(a, b); |
540 | } |
548 | } |
541 | if (wm1.priority_mark.full > priority_mark12.full) |
549 | if (wm1.priority_mark.full > priority_mark12.full) |
542 | priority_mark12.full = wm1.priority_mark.full; |
550 | priority_mark12.full = wm1.priority_mark.full; |
543 | if (rfixed_trunc(priority_mark12) < 0) |
551 | if (dfixed_trunc(priority_mark12) < 0) |
544 | priority_mark12.full = 0; |
552 | priority_mark12.full = 0; |
545 | if (wm1.priority_mark_max.full > priority_mark12.full) |
553 | if (wm1.priority_mark_max.full > priority_mark12.full) |
546 | priority_mark12.full = wm1.priority_mark_max.full; |
- | |
547 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, |
554 | priority_mark12.full = wm1.priority_mark_max.full; |
548 | S_006548_D1MODE_PRIORITY_A_OFF(1)); |
555 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
549 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, |
556 | if (rdev->disp_priority == 2) |
550 | S_00654C_D1MODE_PRIORITY_B_OFF(1)); |
- | |
551 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
- | |
552 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
557 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
- | 558 | } |
|
- | 559 | ||
- | 560 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
|
- | 561 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
|
- | 562 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
|
553 | } |
563 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
Line 554... | Line 564... | ||
554 | } |
564 | } |
555 | 565 | ||
556 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
566 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
Line 609... | Line 619... | ||
609 | // rs600_irq_set(rdev); |
619 | // rs600_irq_set(rdev); |
610 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
620 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
611 | /* 1M ring buffer */ |
621 | /* 1M ring buffer */ |
612 | r = r100_cp_init(rdev, 1024 * 1024); |
622 | r = r100_cp_init(rdev, 1024 * 1024); |
613 | if (r) { |
623 | if (r) { |
614 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
624 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
615 | return r; |
625 | return r; |
616 | } |
626 | } |
617 | // r = r100_wb_init(rdev); |
- | |
618 | // if (r) |
- | |
619 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
- | |
620 | // r = r100_ib_init(rdev); |
627 | // r = r100_ib_init(rdev); |
621 | // if (r) { |
628 | // if (r) { |
622 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
629 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
623 | // return r; |
630 | // return r; |
624 | // } |
631 | // } |
Line 636... | Line 643... | ||
636 | rv515_vga_render_disable(rdev); |
643 | rv515_vga_render_disable(rdev); |
637 | /* Initialize scratch registers */ |
644 | /* Initialize scratch registers */ |
638 | radeon_scratch_init(rdev); |
645 | radeon_scratch_init(rdev); |
639 | /* Initialize surface registers */ |
646 | /* Initialize surface registers */ |
640 | radeon_surface_init(rdev); |
647 | radeon_surface_init(rdev); |
- | 648 | /* restore some register to sane defaults */ |
|
- | 649 | r100_restore_sanity(rdev); |
|
641 | /* TODO: disable VGA need to use VGA request */ |
650 | /* TODO: disable VGA need to use VGA request */ |
642 | /* BIOS*/ |
651 | /* BIOS*/ |
643 | if (!radeon_get_bios(rdev)) { |
652 | if (!radeon_get_bios(rdev)) { |
644 | if (ASIC_IS_AVIVO(rdev)) |
653 | if (ASIC_IS_AVIVO(rdev)) |
645 | return -EINVAL; |
654 | return -EINVAL; |
Line 651... | Line 660... | ||
651 | } else { |
660 | } else { |
652 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
661 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
653 | return -EINVAL; |
662 | return -EINVAL; |
654 | } |
663 | } |
655 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
664 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
656 | if (radeon_gpu_reset(rdev)) { |
665 | if (radeon_asic_reset(rdev)) { |
657 | dev_warn(rdev->dev, |
666 | dev_warn(rdev->dev, |
658 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
667 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
659 | RREG32(R_000E40_RBBM_STATUS), |
668 | RREG32(R_000E40_RBBM_STATUS), |
660 | RREG32(R_0007C0_CP_STAT)); |
669 | RREG32(R_0007C0_CP_STAT)); |
661 | } |
670 | } |
Line 663... | Line 672... | ||
663 | if (radeon_boot_test_post_card(rdev) == false) |
672 | if (radeon_boot_test_post_card(rdev) == false) |
664 | return -EINVAL; |
673 | return -EINVAL; |
Line 665... | Line 674... | ||
665 | 674 | ||
666 | /* Initialize clocks */ |
675 | /* Initialize clocks */ |
667 | radeon_get_clock_info(rdev->ddev); |
- | |
668 | /* Initialize power management */ |
- | |
669 | radeon_pm_init(rdev); |
676 | radeon_get_clock_info(rdev->ddev); |
670 | /* initialize memory controller */ |
677 | /* initialize memory controller */ |
671 | rs690_mc_init(rdev); |
678 | rs690_mc_init(rdev); |
672 | rv515_debugfs(rdev); |
679 | rv515_debugfs(rdev); |
673 | /* Fence driver */ |
680 | /* Fence driver */ |