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Rev 3764 | Rev 5078 | ||
---|---|---|---|
Line 104... | Line 104... | ||
104 | while (!avivo_is_in_vblank(rdev, crtc)) { |
104 | while (!avivo_is_in_vblank(rdev, crtc)) { |
105 | if (i++ % 100 == 0) { |
105 | if (i++ % 100 == 0) { |
106 | if (!avivo_is_counter_moving(rdev, crtc)) |
106 | if (!avivo_is_counter_moving(rdev, crtc)) |
107 | break; |
107 | break; |
108 | } |
108 | } |
- | 109 | } |
|
- | 110 | } |
|
- | 111 | void avivo_program_fmt(struct drm_encoder *encoder) |
|
- | 112 | { |
|
- | 113 | struct drm_device *dev = encoder->dev; |
|
- | 114 | struct radeon_device *rdev = dev->dev_private; |
|
- | 115 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 116 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
|
- | 117 | int bpc = 0; |
|
- | 118 | u32 tmp = 0; |
|
- | 119 | enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; |
|
- | 120 | ||
- | 121 | if (connector) { |
|
- | 122 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
- | 123 | bpc = radeon_get_monitor_bpc(connector); |
|
- | 124 | dither = radeon_connector->dither; |
|
- | 125 | } |
|
- | 126 | ||
- | 127 | /* LVDS FMT is set up by atom */ |
|
- | 128 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
|
- | 129 | return; |
|
- | 130 | ||
- | 131 | if (bpc == 0) |
|
- | 132 | return; |
|
- | 133 | ||
- | 134 | switch (bpc) { |
|
- | 135 | case 6: |
|
- | 136 | if (dither == RADEON_FMT_DITHER_ENABLE) |
|
109 | for (i = 0; i < rdev->usec_timeout; i++) { |
137 | /* XXX sort out optimal dither settings */ |
110 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
138 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
- | 139 | else |
|
- | 140 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
|
111 | break; |
141 | break; |
- | 142 | case 8: |
|
- | 143 | if (dither == RADEON_FMT_DITHER_ENABLE) |
|
- | 144 | /* XXX sort out optimal dither settings */ |
|
- | 145 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | |
|
- | 146 | AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); |
|
- | 147 | else |
|
- | 148 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | |
|
- | 149 | AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); |
|
112 | udelay(1); |
150 | break; |
- | 151 | case 10: |
|
- | 152 | default: |
|
- | 153 | /* not needed */ |
|
- | 154 | break; |
|
- | 155 | } |
|
- | 156 | ||
- | 157 | switch (radeon_encoder->encoder_id) { |
|
- | 158 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
|
- | 159 | WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); |
|
- | 160 | break; |
|
- | 161 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
|
- | 162 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); |
|
- | 163 | break; |
|
- | 164 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
|
- | 165 | WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); |
|
- | 166 | break; |
|
- | 167 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
|
- | 168 | WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); |
|
- | 169 | break; |
|
- | 170 | default: |
|
- | 171 | break; |
|
- | 172 | } |
|
- | 173 | } |
|
- | 174 | ||
- | 175 | void rs600_pm_misc(struct radeon_device *rdev) |
|
- | 176 | { |
|
- | 177 | int requested_index = rdev->pm.requested_power_state_index; |
|
- | 178 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; |
|
- | 179 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; |
|
- | 180 | u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; |
|
- | 181 | u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; |
|
- | 182 | ||
- | 183 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { |
|
- | 184 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { |
|
- | 185 | tmp = RREG32(voltage->gpio.reg); |
|
- | 186 | if (voltage->active_high) |
|
- | 187 | tmp |= voltage->gpio.mask; |
|
- | 188 | else |
|
- | 189 | tmp &= ~(voltage->gpio.mask); |
|
- | 190 | WREG32(voltage->gpio.reg, tmp); |
|
- | 191 | if (voltage->delay) |
|
- | 192 | udelay(voltage->delay); |
|
- | 193 | } else { |
|
- | 194 | tmp = RREG32(voltage->gpio.reg); |
|
- | 195 | if (voltage->active_high) |
|
- | 196 | tmp &= ~voltage->gpio.mask; |
|
- | 197 | else |
|
- | 198 | tmp |= voltage->gpio.mask; |
|
- | 199 | WREG32(voltage->gpio.reg, tmp); |
|
- | 200 | if (voltage->delay) |
|
- | 201 | udelay(voltage->delay); |
|
- | 202 | } |
|
- | 203 | } else if (voltage->type == VOLTAGE_VDDC) |
|
- | 204 | radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); |
|
- | 205 | ||
- | 206 | dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); |
|
- | 207 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); |
|
- | 208 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); |
|
- | 209 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { |
|
- | 210 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { |
|
- | 211 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); |
|
- | 212 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); |
|
- | 213 | } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { |
|
- | 214 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); |
|
- | 215 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); |
|
- | 216 | } |
|
- | 217 | } else { |
|
- | 218 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); |
|
- | 219 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); |
|
- | 220 | } |
|
- | 221 | WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); |
|
- | 222 | ||
- | 223 | dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); |
|
- | 224 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { |
|
- | 225 | dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; |
|
- | 226 | if (voltage->delay) { |
|
- | 227 | dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; |
|
- | 228 | dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); |
|
- | 229 | } else |
|
- | 230 | dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; |
|
- | 231 | } else |
|
- | 232 | dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; |
|
- | 233 | WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); |
|
- | 234 | ||
- | 235 | hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); |
|
- | 236 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) |
|
- | 237 | hdp_dyn_cntl &= ~HDP_FORCEON; |
|
- | 238 | else |
|
- | 239 | hdp_dyn_cntl |= HDP_FORCEON; |
|
- | 240 | WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); |
|
- | 241 | #if 0 |
|
- | 242 | /* mc_host_dyn seems to cause hangs from time to time */ |
|
- | 243 | mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); |
|
- | 244 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) |
|
- | 245 | mc_host_dyn_cntl &= ~MC_HOST_FORCEON; |
|
- | 246 | else |
|
- | 247 | mc_host_dyn_cntl |= MC_HOST_FORCEON; |
|
- | 248 | WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); |
|
- | 249 | #endif |
|
- | 250 | dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); |
|
- | 251 | if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) |
|
- | 252 | dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; |
|
- | 253 | else |
|
- | 254 | dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; |
|
- | 255 | WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); |
|
- | 256 | ||
- | 257 | /* set pcie lanes */ |
|
- | 258 | if ((rdev->flags & RADEON_IS_PCIE) && |
|
- | 259 | !(rdev->flags & RADEON_IS_IGP) && |
|
- | 260 | rdev->asic->pm.set_pcie_lanes && |
|
- | 261 | (ps->pcie_lanes != |
|
- | 262 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { |
|
- | 263 | radeon_set_pcie_lanes(rdev, |
|
- | 264 | ps->pcie_lanes); |
|
- | 265 | DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); |
|
- | 266 | } |
|
- | 267 | } |
|
- | 268 | ||
- | 269 | void rs600_pm_prepare(struct radeon_device *rdev) |
|
- | 270 | { |
|
- | 271 | struct drm_device *ddev = rdev->ddev; |
|
- | 272 | struct drm_crtc *crtc; |
|
- | 273 | struct radeon_crtc *radeon_crtc; |
|
- | 274 | u32 tmp; |
|
- | 275 | ||
- | 276 | /* disable any active CRTCs */ |
|
- | 277 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
|
- | 278 | radeon_crtc = to_radeon_crtc(crtc); |
|
- | 279 | if (radeon_crtc->enabled) { |
|
- | 280 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); |
|
- | 281 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
|
- | 282 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
|
- | 283 | } |
|
- | 284 | } |
|
- | 285 | } |
|
- | 286 | ||
- | 287 | void rs600_pm_finish(struct radeon_device *rdev) |
|
- | 288 | { |
|
- | 289 | struct drm_device *ddev = rdev->ddev; |
|
- | 290 | struct drm_crtc *crtc; |
|
- | 291 | struct radeon_crtc *radeon_crtc; |
|
- | 292 | u32 tmp; |
|
- | 293 | ||
- | 294 | /* enable any active CRTCs */ |
|
- | 295 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
|
- | 296 | radeon_crtc = to_radeon_crtc(crtc); |
|
- | 297 | if (radeon_crtc->enabled) { |
|
- | 298 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); |
|
- | 299 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
|
- | 300 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
|
113 | } |
301 | } |
114 | } |
302 | } |
115 | } |
303 | } |
- | 304 | ||
116 | /* hpd for digital panel detect/disconnect */ |
305 | /* hpd for digital panel detect/disconnect */ |
117 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
306 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
118 | { |
307 | { |
119 | u32 tmp; |
308 | u32 tmp; |
120 | bool connected = false; |
309 | bool connected = false; |
Line 325... | Line 514... | ||
325 | return -EINVAL; |
514 | return -EINVAL; |
326 | } |
515 | } |
327 | r = radeon_gart_table_vram_pin(rdev); |
516 | r = radeon_gart_table_vram_pin(rdev); |
328 | if (r) |
517 | if (r) |
329 | return r; |
518 | return r; |
330 | radeon_gart_restore(rdev); |
- | |
331 | /* Enable bus master */ |
519 | /* Enable bus master */ |
332 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
520 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
333 | WREG32(RADEON_BUS_CNTL, tmp); |
521 | WREG32(RADEON_BUS_CNTL, tmp); |
334 | /* FIXME: setup default page */ |
522 | /* FIXME: setup default page */ |
335 | WREG32_MC(R_000100_MC_PT0_CNTL, |
523 | WREG32_MC(R_000100_MC_PT0_CNTL, |
Line 396... | Line 584... | ||
396 | radeon_gart_fini(rdev); |
584 | radeon_gart_fini(rdev); |
397 | rs600_gart_disable(rdev); |
585 | rs600_gart_disable(rdev); |
398 | radeon_gart_table_vram_free(rdev); |
586 | radeon_gart_table_vram_free(rdev); |
399 | } |
587 | } |
Line 400... | Line -... | ||
400 | - | ||
401 | #define R600_PTE_VALID (1 << 0) |
- | |
402 | #define R600_PTE_SYSTEM (1 << 1) |
- | |
403 | #define R600_PTE_SNOOPED (1 << 2) |
- | |
404 | #define R600_PTE_READABLE (1 << 5) |
- | |
405 | #define R600_PTE_WRITEABLE (1 << 6) |
- | |
406 | 588 | ||
- | 589 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
|
407 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
590 | uint64_t addr, uint32_t flags) |
408 | { |
591 | { |
Line 409... | Line -... | ||
409 | void __iomem *ptr = (void *)rdev->gart.ptr; |
- | |
410 | - | ||
411 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
- | |
412 | return -EINVAL; |
592 | void __iomem *ptr = (void *)rdev->gart.ptr; |
413 | } |
593 | |
- | 594 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
|
- | 595 | addr |= R600_PTE_SYSTEM; |
|
- | 596 | if (flags & RADEON_GART_PAGE_VALID) |
|
- | 597 | addr |= R600_PTE_VALID; |
|
- | 598 | if (flags & RADEON_GART_PAGE_READ) |
|
414 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
599 | addr |= R600_PTE_READABLE; |
- | 600 | if (flags & RADEON_GART_PAGE_WRITE) |
|
- | 601 | addr |= R600_PTE_WRITEABLE; |
|
415 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
602 | if (flags & RADEON_GART_PAGE_SNOOP) |
416 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
- | |
417 | writeq(addr, ptr + (i * 8)); |
603 | addr |= R600_PTE_SNOOPED; |
Line 418... | Line 604... | ||
418 | return 0; |
604 | writeq(addr, ptr + (i * 8)); |
419 | } |
605 | } |
420 | 606 | ||
Line 675... | Line 861... | ||
675 | } |
861 | } |
676 | } |
862 | } |
Line 677... | Line 863... | ||
677 | 863 | ||
678 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
864 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
- | 865 | { |
|
- | 866 | unsigned long flags; |
|
- | 867 | u32 r; |
|
- | 868 | ||
679 | { |
869 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
680 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
870 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
681 | S_000070_MC_IND_CITF_ARB0(1)); |
871 | S_000070_MC_IND_CITF_ARB0(1)); |
- | 872 | r = RREG32(R_000074_MC_IND_DATA); |
|
- | 873 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
|
682 | return RREG32(R_000074_MC_IND_DATA); |
874 | return r; |
Line 683... | Line 875... | ||
683 | } |
875 | } |
684 | 876 | ||
- | 877 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
|
- | 878 | { |
|
- | 879 | unsigned long flags; |
|
685 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
880 | |
686 | { |
881 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
687 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
882 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
- | 883 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
|
688 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
884 | WREG32(R_000074_MC_IND_DATA, v); |
Line 689... | Line 885... | ||
689 | WREG32(R_000074_MC_IND_DATA, v); |
885 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
690 | } |
886 | } |
691 | 887 | ||
Line 772... | Line 968... | ||
772 | if (r) { |
968 | if (r) { |
773 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
969 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
774 | return r; |
970 | return r; |
775 | } |
971 | } |
Line -... | Line 972... | ||
- | 972 | ||
- | 973 | r = r600_audio_init(rdev); |
|
- | 974 | if (r) { |
|
- | 975 | dev_err(rdev->dev, "failed initializing audio\n"); |
|
- | 976 | return r; |
|
Line 776... | Line 977... | ||
776 | 977 | } |
|
777 | 978 | ||
Line 832... | Line 1033... | ||
832 | r = rs600_gart_init(rdev); |
1033 | r = rs600_gart_init(rdev); |
833 | if (r) |
1034 | if (r) |
834 | return r; |
1035 | return r; |
835 | rs600_set_safe_registers(rdev); |
1036 | rs600_set_safe_registers(rdev); |
Line -... | Line 1037... | ||
- | 1037 | ||
- | 1038 | /* Initialize power management */ |
|
- | 1039 | radeon_pm_init(rdev); |
|
836 | 1040 | ||
837 | rdev->accel_working = true; |
1041 | rdev->accel_working = true; |
838 | r = rs600_startup(rdev); |
1042 | r = rs600_startup(rdev); |
839 | if (r) { |
1043 | if (r) { |
840 | /* Somethings want wront with the accel init stop accel */ |
1044 | /* Somethings want wront with the accel init stop accel */ |