WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rs600.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
/* RS600 / Radeon X1250/X1270 integrated GPU
 *
 * This file gather function specific to RS600 which is the IGP of
 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
 * is the X1250/X1270 supporting AMD CPU). The display engine are
 * the avivo one, bios is an atombios, 3D block are the one of the
 * R4XX family. The GART is different from the RS400 one and is very
 * close to the one of the R600 family (R600 likely being an evolution
 * of the RS600 GART block).
 */
#include 
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "rs600d.h"
 
#include "rs600_reg_safe.h"
 
static void rs600_gpu_init(struct radeon_device *rdev);
int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 
static const u32 crtc_offsets[2] =
{
	0,
	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
};
 
static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
{
	if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
		return true;
	else
		return false;
}
 
static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
{
	u32 pos1, pos2;
 
	pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
	pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
 
	if (pos1 != pos2)
		return true;
	else
		return false;
}
 
/**
 * avivo_wait_for_vblank - vblank wait asic callback.
 *
 * @rdev: radeon_device pointer
 * @crtc: crtc to wait for vblank on
 *
 * Wait for vblank on the requested crtc (r5xx-r7xx).
 */
void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
{
	unsigned i = 0;
 
	if (crtc >= rdev->num_crtc)
		return;
 
	if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
		return;
 
	/* depending on when we hit vblank, we may be close to active; if so,
	 * wait for another frame.
	 */
	while (avivo_is_in_vblank(rdev, crtc)) {
		if (i++ % 100 == 0) {
			if (!avivo_is_counter_moving(rdev, crtc))
				break;
		}
	}
 
	while (!avivo_is_in_vblank(rdev, crtc)) {
		if (i++ % 100 == 0) {
			if (!avivo_is_counter_moving(rdev, crtc))
 
				break;
		}
		for (i = 0; i < rdev->usec_timeout; i++) {
			if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
				break;
			udelay(1);
		}
	}
}
/* hpd for digital panel detect/disconnect */
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
{
	u32 tmp;
	bool connected = false;
 
	switch (hpd) {
	case RADEON_HPD_1:
		tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
		if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
			connected = true;
		break;
	case RADEON_HPD_2:
		tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
		if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
			connected = true;
		break;
	default:
		break;
	}
	return connected;
}
 
void rs600_hpd_set_polarity(struct radeon_device *rdev,
			    enum radeon_hpd_id hpd)
{
	u32 tmp;
	bool connected = rs600_hpd_sense(rdev, hpd);
 
	switch (hpd) {
	case RADEON_HPD_1:
		tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
		if (connected)
			tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
		else
			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
		WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		break;
	case RADEON_HPD_2:
		tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
		if (connected)
			tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
		else
			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
		WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		break;
	default:
		break;
	}
}
 
void rs600_hpd_init(struct radeon_device *rdev)
{
	struct drm_device *dev = rdev->ddev;
	struct drm_connector *connector;
	unsigned enable = 0;
 
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		switch (radeon_connector->hpd.hpd) {
		case RADEON_HPD_1:
			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
			       S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
			break;
		case RADEON_HPD_2:
			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
			       S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
			break;
		default:
			break;
		}
		enable |= 1 << radeon_connector->hpd.hpd;
		radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
	}
//	radeon_irq_kms_enable_hpd(rdev, enable);
}
 
void rs600_hpd_fini(struct radeon_device *rdev)
{
	struct drm_device *dev = rdev->ddev;
	struct drm_connector *connector;
	unsigned disable = 0;
 
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		switch (radeon_connector->hpd.hpd) {
		case RADEON_HPD_1:
			WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
			       S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
			break;
		case RADEON_HPD_2:
			WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
			       S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
			break;
		default:
			break;
		}
		disable |= 1 << radeon_connector->hpd.hpd;
	}
//	radeon_irq_kms_disable_hpd(rdev, disable);
}
 
int rs600_asic_reset(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
	u32 status, tmp;
	int ret = 0;
 
	status = RREG32(R_000E40_RBBM_STATUS);
	if (!G_000E40_GUI_ACTIVE(status)) {
		return 0;
	}
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* stop CP */
	WREG32(RADEON_CP_CSQ_CNTL, 0);
	tmp = RREG32(RADEON_CP_RB_CNTL);
	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
	WREG32(RADEON_CP_RB_RPTR_WR, 0);
	WREG32(RADEON_CP_RB_WPTR, 0);
	WREG32(RADEON_CP_RB_CNTL, tmp);
//   pci_save_state(rdev->pdev);
	/* disable bus mastering */
//	pci_clear_master(rdev->pdev);
	mdelay(1);
	/* reset GA+VAP */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
					S_0000F0_SOFT_RESET_GA(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* reset CP */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* reset MC */
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
	RREG32(R_0000F0_RBBM_SOFT_RESET);
	mdelay(500);
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
	mdelay(1);
	status = RREG32(R_000E40_RBBM_STATUS);
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
	/* restore PCI & busmastering */
//   pci_restore_state(rdev->pdev);
	/* Check if GPU is idle */
	if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
		dev_err(rdev->dev, "failed to reset GPU\n");
		ret = -1;
	} else
		dev_info(rdev->dev, "GPU reset succeed\n");
	rv515_mc_resume(rdev, &save);
	return ret;
}
 
/*
 * GART.
 */
void rs600_gart_tlb_flush(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
}
 
static int rs600_gart_init(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->gart.robj) {
		WARN(1, "RS600 GART already initialized\n");
		return 0;
	}
	/* Initialize common gart structure */
	r = radeon_gart_init(rdev);
	if (r) {
		return r;
	}
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
	return radeon_gart_table_vram_alloc(rdev);
}
 
static int rs600_gart_enable(struct radeon_device *rdev)
{
	u32 tmp;
	int r, i;
 
	if (rdev->gart.robj == NULL) {
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		return -EINVAL;
	}
	r = radeon_gart_table_vram_pin(rdev);
	if (r)
		return r;
	radeon_gart_restore(rdev);
	/* Enable bus master */
	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
	WREG32(RADEON_BUS_CNTL, tmp);
	/* FIXME: setup default page */
	WREG32_MC(R_000100_MC_PT0_CNTL,
		 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
		  S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 
	for (i = 0; i < 19; i++) {
		WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
			S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
			S_00016C_SYSTEM_ACCESS_MODE_MASK(
				  V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
			S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
				  V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
			  S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
			S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
			  S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
	}
	/* enable first context */
	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
			S_000102_ENABLE_PAGE_TABLE(1) |
			S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 
	/* disable all other contexts */
	for (i = 1; i < 8; i++)
		WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 
	/* setup the page table */
	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
		 rdev->gart.table_addr);
	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 
	/* System context maps to VRAM space */
	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 
	/* enable page tables */
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
	tmp = RREG32_MC(R_000009_MC_CNTL1);
	WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
	rs600_gart_tlb_flush(rdev);
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
		 (unsigned)(rdev->mc.gtt_size >> 20),
		 (unsigned long long)rdev->gart.table_addr);
	rdev->gart.ready = true;
	return 0;
}
 
static void rs600_gart_disable(struct radeon_device *rdev)
{
	u32 tmp;
 
	/* FIXME: disable out of gart access */
	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
	tmp = RREG32_MC(R_000009_MC_CNTL1);
	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
	radeon_gart_table_vram_unpin(rdev);
}
 
static void rs600_gart_fini(struct radeon_device *rdev)
{
	radeon_gart_fini(rdev);
	rs600_gart_disable(rdev);
	radeon_gart_table_vram_free(rdev);
}
 
#define R600_PTE_VALID     (1 << 0)
#define R600_PTE_SYSTEM    (1 << 1)
#define R600_PTE_SNOOPED   (1 << 2)
#define R600_PTE_READABLE  (1 << 5)
#define R600_PTE_WRITEABLE (1 << 6)
 
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
{
	void __iomem *ptr = (void *)rdev->gart.ptr;
 
	if (i < 0 || i > rdev->gart.num_gpu_pages) {
		return -EINVAL;
	}
	addr = addr & 0xFFFFFFFFFFFFF000ULL;
	addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
	addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
	writeq(addr, ptr + (i * 8));
	return 0;
}
 
int rs600_irq_set(struct radeon_device *rdev)
{
	uint32_t tmp = 0;
	uint32_t mode_int = 0;
	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
		~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
		~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
	u32 hdmi0;
	if (ASIC_IS_DCE2(rdev))
		hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
			~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
	else
		hdmi0 = 0;
 
   if (!rdev->irq.installed) {
		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
		WREG32(R_000040_GEN_INT_CNTL, 0);
		return -EINVAL;
	}
	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
		tmp |= S_000040_SW_INT_EN(1);
	}
	if (rdev->irq.crtc_vblank_int[0] ||
	    atomic_read(&rdev->irq.pflip[0])) {
		mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
	}
	if (rdev->irq.crtc_vblank_int[1] ||
	    atomic_read(&rdev->irq.pflip[1])) {
		mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
	}
	if (rdev->irq.hpd[0]) {
		hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
	}
	if (rdev->irq.hpd[1]) {
		hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
	}
	if (rdev->irq.afmt[0]) {
		hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
	}
	WREG32(R_000040_GEN_INT_CNTL, tmp);
	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
	if (ASIC_IS_DCE2(rdev))
		WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
	return 0;
}
 
static inline u32 rs600_irq_ack(struct radeon_device *rdev)
{
	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
	uint32_t irq_mask = S_000044_SW_INT(1);
	u32 tmp;
 
	if (G_000044_DISPLAY_INT_STAT(irqs)) {
		rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			WREG32(R_006534_D1MODE_VBLANK_STATUS,
				S_006534_D1MODE_VBLANK_ACK(1));
		}
		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			WREG32(R_006D34_D2MODE_VBLANK_STATUS,
				S_006D34_D2MODE_VBLANK_ACK(1));
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
			WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
			WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		}
	} else {
		rdev->irq.stat_regs.r500.disp_int = 0;
	}
 
	if (ASIC_IS_DCE2(rdev)) {
		rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
			S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
		if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
			tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
			tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
			WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
		}
	} else
		rdev->irq.stat_regs.r500.hdmi0_status = 0;
 
	if (irqs) {
		WREG32(R_000044_GEN_INT_STATUS, irqs);
	}
	return irqs & irq_mask;
}
 
void rs600_irq_disable(struct radeon_device *rdev)
{
	u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
		~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
	WREG32(R_000040_GEN_INT_CNTL, 0);
	WREG32(R_006540_DxMODE_INT_MASK, 0);
	/* Wait and acknowledge irq */
	mdelay(1);
	rs600_irq_ack(rdev);
}
 
int rs600_irq_process(struct radeon_device *rdev)
{
	u32 status, msi_rearm;
	bool queue_hotplug = false;
	bool queue_hdmi = false;
 
	status = rs600_irq_ack(rdev);
	if (!status &&
	    !rdev->irq.stat_regs.r500.disp_int &&
	    !rdev->irq.stat_regs.r500.hdmi0_status) {
		return IRQ_NONE;
	}
	while (status ||
	       rdev->irq.stat_regs.r500.disp_int ||
	       rdev->irq.stat_regs.r500.hdmi0_status) {
		/* SW interrupt */
		if (G_000044_SW_INT(status)) {
			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
		}
		/* Vertical blank interrupts */
		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			if (rdev->irq.crtc_vblank_int[0]) {
//				drm_handle_vblank(rdev->ddev, 0);
				rdev->pm.vblank_sync = true;
//				wake_up(&rdev->irq.vblank_queue);
			}
//			if (rdev->irq.pflip[0])
//				radeon_crtc_handle_flip(rdev, 0);
		}
		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			if (rdev->irq.crtc_vblank_int[1]) {
//				drm_handle_vblank(rdev->ddev, 1);
				rdev->pm.vblank_sync = true;
//				wake_up(&rdev->irq.vblank_queue);
			}
//			if (rdev->irq.pflip[1])
//				radeon_crtc_handle_flip(rdev, 1);
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			queue_hotplug = true;
			DRM_DEBUG("HPD1\n");
		}
		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
			queue_hotplug = true;
			DRM_DEBUG("HPD2\n");
		}
		if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
			queue_hdmi = true;
			DRM_DEBUG("HDMI0\n");
		}
		status = rs600_irq_ack(rdev);
	}
//	if (queue_hotplug)
//		schedule_work(&rdev->hotplug_work);
//	if (queue_hdmi)
//		schedule_work(&rdev->audio_work);
	if (rdev->msi_enabled) {
		switch (rdev->family) {
		case CHIP_RS600:
		case CHIP_RS690:
		case CHIP_RS740:
			msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
			WREG32(RADEON_BUS_CNTL, msi_rearm);
			WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
			break;
		default:
			WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
			break;
		}
	}
	return IRQ_HANDLED;
}
 
u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
{
	if (crtc == 0)
		return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
	else
		return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
}
 
int rs600_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
 
	for (i = 0; i < rdev->usec_timeout; i++) {
		if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
			return 0;
		udelay(1);
	}
	return -1;
}
 
static void rs600_gpu_init(struct radeon_device *rdev)
{
	r420_pipes_init(rdev);
	/* Wait for mc idle */
	if (rs600_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
}
 
static void rs600_mc_init(struct radeon_device *rdev)
{
	u64 base;
 
	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
	rdev->mc.vram_is_ddr = true;
	rdev->mc.vram_width = 128;
	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
	rdev->mc.visible_vram_size = rdev->mc.aper_size;
	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
	base = RREG32_MC(R_000004_MC_FB_LOCATION);
	base = G_000004_MC_FB_START(base) << 16;
	radeon_vram_location(rdev, &rdev->mc, base);
	rdev->mc.gtt_base_align = 0;
	radeon_gtt_location(rdev, &rdev->mc);
	radeon_update_bandwidth_info(rdev);
}
 
void rs600_bandwidth_update(struct radeon_device *rdev)
{
	struct drm_display_mode *mode0 = NULL;
	struct drm_display_mode *mode1 = NULL;
	u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
	/* FIXME: implement full support */
 
	radeon_update_display_priority(rdev);
 
	if (rdev->mode_info.crtcs[0]->base.enabled)
		mode0 = &rdev->mode_info.crtcs[0]->base.mode;
	if (rdev->mode_info.crtcs[1]->base.enabled)
		mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 
	rs690_line_buffer_adjust(rdev, mode0, mode1);
 
	if (rdev->disp_priority == 2) {
		d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
		d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
		d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
		d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
		WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
		WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
		WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
		WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
	}
}
 
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
		S_000070_MC_IND_CITF_ARB0(1));
	return RREG32(R_000074_MC_IND_DATA);
}
 
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
		S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
	WREG32(R_000074_MC_IND_DATA, v);
}
 
static void rs600_debugfs(struct radeon_device *rdev)
{
	if (r100_debugfs_rbbm_init(rdev))
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
}
 
void rs600_set_safe_registers(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
}
 
static void rs600_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
 
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
 
	/* Wait for mc idle */
	if (rs600_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 
	/* FIXME: What does AGP means for such chipset ? */
	WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
	WREG32_MC(R_000006_AGP_BASE, 0);
	WREG32_MC(R_000007_AGP_BASE_2, 0);
	/* Program MC */
	WREG32_MC(R_000004_MC_FB_LOCATION,
			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	WREG32(R_000134_HDP_FB_LOCATION,
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 
	rv515_mc_resume(rdev, &save);
}
 
static int rs600_startup(struct radeon_device *rdev)
{
	int r;
 
	rs600_mc_program(rdev);
	/* Resume clock */
	rv515_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	rs600_gpu_init(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	r = rs600_gart_enable(rdev);
	if (r)
	return r;
 
	/* allocate wb buffer */
	r = radeon_wb_init(rdev);
	if (r)
		return r;
 
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		return r;
	}
 
	/* Enable IRQ */
	if (!rdev->irq.installed) {
		r = radeon_irq_kms_init(rdev);
		if (r)
			return r;
	}
 
	rs600_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
		return r;
	}
 
	r = radeon_ib_pool_init(rdev);
	if (r) {
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
		return r;
	}
 
 
	return 0;
}
 
 
 
int rs600_init(struct radeon_device *rdev)
{
	int r;
 
	/* Disable VGA */
	rv515_vga_render_disable(rdev);
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* restore some register to sane defaults */
	r100_restore_sanity(rdev);
	/* BIOS */
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r)
			return r;
	} else {
		dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
		return -EINVAL;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;
 
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* initialize memory controller */
	rs600_mc_init(rdev);
	rs600_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
 
 
 
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	r = rs600_gart_init(rdev);
	if (r)
		return r;
	rs600_set_safe_registers(rdev);
 
	rdev->accel_working = true;
	r = rs600_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
//		r100_cp_fini(rdev);
//		r100_wb_fini(rdev);
//		r100_ib_fini(rdev);
		rs600_gart_fini(rdev);
//		radeon_irq_kms_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}

Rev 3192	Rev 3764
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	/* RS600 / Radeon X1250/X1270 integrated GPU	28	/* RS600 / Radeon X1250/X1270 integrated GPU
29	*	29	*
30	* This file gather function specific to RS600 which is the IGP of	30	* This file gather function specific to RS600 which is the IGP of
31	* the X1250/X1270 family supporting intel CPU (while RS690/RS740	31	* the X1250/X1270 family supporting intel CPU (while RS690/RS740
32	* is the X1250/X1270 supporting AMD CPU). The display engine are	32	* is the X1250/X1270 supporting AMD CPU). The display engine are
33	* the avivo one, bios is an atombios, 3D block are the one of the	33	* the avivo one, bios is an atombios, 3D block are the one of the
34	* R4XX family. The GART is different from the RS400 one and is very	34	* R4XX family. The GART is different from the RS400 one and is very
35	* close to the one of the R600 family (R600 likely being an evolution	35	* close to the one of the R600 family (R600 likely being an evolution
36	* of the RS600 GART block).	36	* of the RS600 GART block).
37	*/	37	*/
38	#include	38	#include
39	#include "radeon.h"	39	#include "radeon.h"
40	#include "radeon_asic.h"	40	#include "radeon_asic.h"
41	#include "atom.h"	41	#include "atom.h"
42	#include "rs600d.h"	42	#include "rs600d.h"
43		43
44	#include "rs600_reg_safe.h"	44	#include "rs600_reg_safe.h"
45		45
46	static void rs600_gpu_init(struct radeon_device *rdev);	46	static void rs600_gpu_init(struct radeon_device *rdev);
47	int rs600_mc_wait_for_idle(struct radeon_device *rdev);	47	int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48		48
49	static const u32 crtc_offsets[2] =	49	static const u32 crtc_offsets[2] =
50	{	50	{
51	0,	51	0,
52	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL	52	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
53	};	53	};
-		54
-		55	static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
-		56	{
-		57	if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
-		58	return true;
-		59	else
-		60	return false;
-		61	}
-		62
-		63	static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
-		64	{
-		65	u32 pos1, pos2;
-		66
-		67	pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
-		68	pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
-		69
-		70	if (pos1 != pos2)
-		71	return true;
-		72	else
-		73	return false;
-		74	}
-		75
-		76	/**
-		77	* avivo_wait_for_vblank - vblank wait asic callback.
-		78	*
-		79	* @rdev: radeon_device pointer
-		80	* @crtc: crtc to wait for vblank on
-		81	*
-		82	* Wait for vblank on the requested crtc (r5xx-r7xx).
54		83	*/
55	void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)	84	void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
56	{	85	{
57	int i;	86	unsigned i = 0;
58		87
59	if (crtc >= rdev->num_crtc)	88	if (crtc >= rdev->num_crtc)
60	return;	89	return;
61		90
-		91	if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
-		92	return;
-		93
-		94	/* depending on when we hit vblank, we may be close to active; if so,
-		95	* wait for another frame.
-		96	*/
-		97	while (avivo_is_in_vblank(rdev, crtc)) {
-		98	if (i++ % 100 == 0) {
-		99	if (!avivo_is_counter_moving(rdev, crtc))
-		100	break;
-		101	}
-		102	}
62	if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) {	103
-		104	while (!avivo_is_in_vblank(rdev, crtc)) {
63	for (i = 0; i < rdev->usec_timeout; i++) {	105	if (i++ % 100 == 0) {
64	if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK))	106	if (!avivo_is_counter_moving(rdev, crtc))
65	break;	-
66	udelay(1);	107	break;
67	}	108	}
68	for (i = 0; i < rdev->usec_timeout; i++) {	109	for (i = 0; i < rdev->usec_timeout; i++) {
69	if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)	110	if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
70	break;	111	break;
71	udelay(1);	112	udelay(1);
72	}	113	}
73	}	114	}
74	}	115	}
75	/* hpd for digital panel detect/disconnect */	116	/* hpd for digital panel detect/disconnect */
76	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)	117	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
77	{	118	{
78	u32 tmp;	119	u32 tmp;
79	bool connected = false;	120	bool connected = false;
80		121
81	switch (hpd) {	122	switch (hpd) {
82	case RADEON_HPD_1:	123	case RADEON_HPD_1:
83	tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);	124	tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
84	if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))	125	if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
85	connected = true;	126	connected = true;
86	break;	127	break;
87	case RADEON_HPD_2:	128	case RADEON_HPD_2:
88	tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);	129	tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
89	if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))	130	if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
90	connected = true;	131	connected = true;
91	break;	132	break;
92	default:	133	default:
93	break;	134	break;
94	}	135	}
95	return connected;	136	return connected;
96	}	137	}
97		138
98	void rs600_hpd_set_polarity(struct radeon_device *rdev,	139	void rs600_hpd_set_polarity(struct radeon_device *rdev,
99	enum radeon_hpd_id hpd)	140	enum radeon_hpd_id hpd)
100	{	141	{
101	u32 tmp;	142	u32 tmp;
102	bool connected = rs600_hpd_sense(rdev, hpd);	143	bool connected = rs600_hpd_sense(rdev, hpd);
103		144
104	switch (hpd) {	145	switch (hpd) {
105	case RADEON_HPD_1:	146	case RADEON_HPD_1:
106	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);	147	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
107	if (connected)	148	if (connected)
108	tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);	149	tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
109	else	150	else
110	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);	151	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
111	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);	152	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
112	break;	153	break;
113	case RADEON_HPD_2:	154	case RADEON_HPD_2:
114	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);	155	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
115	if (connected)	156	if (connected)
116	tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);	157	tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
117	else	158	else
118	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);	159	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
119	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);	160	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
120	break;	161	break;
121	default:	162	default:
122	break;	163	break;
123	}	164	}
124	}	165	}
125		166
126	void rs600_hpd_init(struct radeon_device *rdev)	167	void rs600_hpd_init(struct radeon_device *rdev)
127	{	168	{
128	struct drm_device *dev = rdev->ddev;	169	struct drm_device *dev = rdev->ddev;
129	struct drm_connector *connector;	170	struct drm_connector *connector;
130	unsigned enable = 0;	171	unsigned enable = 0;
131		172
132	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	173	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
133	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	174	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
134	switch (radeon_connector->hpd.hpd) {	175	switch (radeon_connector->hpd.hpd) {
135	case RADEON_HPD_1:	176	case RADEON_HPD_1:
136	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,	177	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
137	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));	178	S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
138	break;	179	break;
139	case RADEON_HPD_2:	180	case RADEON_HPD_2:
140	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,	181	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
141	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));	182	S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
142	break;	183	break;
143	default:	184	default:
144	break;	185	break;
145	}	186	}
146	enable \|= 1 << radeon_connector->hpd.hpd;	187	enable \|= 1 << radeon_connector->hpd.hpd;
147	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);	188	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
148	}	189	}
149	// radeon_irq_kms_enable_hpd(rdev, enable);	190	// radeon_irq_kms_enable_hpd(rdev, enable);
150	}	191	}
151		192
152	void rs600_hpd_fini(struct radeon_device *rdev)	193	void rs600_hpd_fini(struct radeon_device *rdev)
153	{	194	{
154	struct drm_device *dev = rdev->ddev;	195	struct drm_device *dev = rdev->ddev;
155	struct drm_connector *connector;	196	struct drm_connector *connector;
156	unsigned disable = 0;	197	unsigned disable = 0;
157		198
158	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	199	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
159	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	200	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
160	switch (radeon_connector->hpd.hpd) {	201	switch (radeon_connector->hpd.hpd) {
161	case RADEON_HPD_1:	202	case RADEON_HPD_1:
162	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,	203	WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
163	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));	204	S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
164	break;	205	break;
165	case RADEON_HPD_2:	206	case RADEON_HPD_2:
166	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,	207	WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
167	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));	208	S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
168	break;	209	break;
169	default:	210	default:
170	break;	211	break;
171	}	212	}
172	disable \|= 1 << radeon_connector->hpd.hpd;	213	disable \|= 1 << radeon_connector->hpd.hpd;
173	}	214	}
174	// radeon_irq_kms_disable_hpd(rdev, disable);	215	// radeon_irq_kms_disable_hpd(rdev, disable);
175	}	216	}
176		217
177	int rs600_asic_reset(struct radeon_device *rdev)	218	int rs600_asic_reset(struct radeon_device *rdev)
178	{	219	{
179	struct rv515_mc_save save;	220	struct rv515_mc_save save;
180	u32 status, tmp;	221	u32 status, tmp;
181	int ret = 0;	222	int ret = 0;
182		223
183	status = RREG32(R_000E40_RBBM_STATUS);	224	status = RREG32(R_000E40_RBBM_STATUS);
184	if (!G_000E40_GUI_ACTIVE(status)) {	225	if (!G_000E40_GUI_ACTIVE(status)) {
185	return 0;	226	return 0;
186	}	227	}
187	/* Stops all mc clients */	228	/* Stops all mc clients */
188	rv515_mc_stop(rdev, &save);	229	rv515_mc_stop(rdev, &save);
189	status = RREG32(R_000E40_RBBM_STATUS);	230	status = RREG32(R_000E40_RBBM_STATUS);
190	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	231	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
191	/* stop CP */	232	/* stop CP */
192	WREG32(RADEON_CP_CSQ_CNTL, 0);	233	WREG32(RADEON_CP_CSQ_CNTL, 0);
193	tmp = RREG32(RADEON_CP_RB_CNTL);	234	tmp = RREG32(RADEON_CP_RB_CNTL);
194	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);	235	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
195	WREG32(RADEON_CP_RB_RPTR_WR, 0);	236	WREG32(RADEON_CP_RB_RPTR_WR, 0);
196	WREG32(RADEON_CP_RB_WPTR, 0);	237	WREG32(RADEON_CP_RB_WPTR, 0);
197	WREG32(RADEON_CP_RB_CNTL, tmp);	238	WREG32(RADEON_CP_RB_CNTL, tmp);
198	// pci_save_state(rdev->pdev);	239	// pci_save_state(rdev->pdev);
199	/* disable bus mastering */	240	/* disable bus mastering */
200	// pci_clear_master(rdev->pdev);	241	// pci_clear_master(rdev->pdev);
201	mdelay(1);	242	mdelay(1);
202	/* reset GA+VAP */	243	/* reset GA+VAP */
203	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) \|	244	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) \|
204	S_0000F0_SOFT_RESET_GA(1));	245	S_0000F0_SOFT_RESET_GA(1));
205	RREG32(R_0000F0_RBBM_SOFT_RESET);	246	RREG32(R_0000F0_RBBM_SOFT_RESET);
206	mdelay(500);	247	mdelay(500);
207	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	248	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
208	mdelay(1);	249	mdelay(1);
209	status = RREG32(R_000E40_RBBM_STATUS);	250	status = RREG32(R_000E40_RBBM_STATUS);
210	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	251	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
211	/* reset CP */	252	/* reset CP */
212	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));	253	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
213	RREG32(R_0000F0_RBBM_SOFT_RESET);	254	RREG32(R_0000F0_RBBM_SOFT_RESET);
214	mdelay(500);	255	mdelay(500);
215	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	256	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
216	mdelay(1);	257	mdelay(1);
217	status = RREG32(R_000E40_RBBM_STATUS);	258	status = RREG32(R_000E40_RBBM_STATUS);
218	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	259	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
219	/* reset MC */	260	/* reset MC */
220	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));	261	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
221	RREG32(R_0000F0_RBBM_SOFT_RESET);	262	RREG32(R_0000F0_RBBM_SOFT_RESET);
222	mdelay(500);	263	mdelay(500);
223	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);	264	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
224	mdelay(1);	265	mdelay(1);
225	status = RREG32(R_000E40_RBBM_STATUS);	266	status = RREG32(R_000E40_RBBM_STATUS);
226	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);	267	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
227	/* restore PCI & busmastering */	268	/* restore PCI & busmastering */
228	// pci_restore_state(rdev->pdev);	269	// pci_restore_state(rdev->pdev);
229	/* Check if GPU is idle */	270	/* Check if GPU is idle */
230	if (G_000E40_GA_BUSY(status) \|\| G_000E40_VAP_BUSY(status)) {	271	if (G_000E40_GA_BUSY(status) \|\| G_000E40_VAP_BUSY(status)) {
231	dev_err(rdev->dev, "failed to reset GPU\n");	272	dev_err(rdev->dev, "failed to reset GPU\n");
232	ret = -1;	273	ret = -1;
233	} else	274	} else
234	dev_info(rdev->dev, "GPU reset succeed\n");	275	dev_info(rdev->dev, "GPU reset succeed\n");
235	rv515_mc_resume(rdev, &save);	276	rv515_mc_resume(rdev, &save);
236	return ret;	277	return ret;
237	}	278	}
238		279
239	/*	280	/*
240	* GART.	281	* GART.
241	*/	282	*/
242	void rs600_gart_tlb_flush(struct radeon_device *rdev)	283	void rs600_gart_tlb_flush(struct radeon_device *rdev)
243	{	284	{
244	uint32_t tmp;	285	uint32_t tmp;
245		286
246	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	287	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
247	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;	288	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
248	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	289	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
249		290
250	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	291	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
251	tmp \|= S_000100_INVALIDATE_ALL_L1_TLBS(1) \| S_000100_INVALIDATE_L2_CACHE(1);	292	tmp \|= S_000100_INVALIDATE_ALL_L1_TLBS(1) \| S_000100_INVALIDATE_L2_CACHE(1);
252	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	293	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
253		294
254	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	295	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
255	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;	296	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
256	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);	297	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
257	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	298	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
258	}	299	}
259		300
260	static int rs600_gart_init(struct radeon_device *rdev)	301	static int rs600_gart_init(struct radeon_device *rdev)
261	{	302	{
262	int r;	303	int r;
263		304
264	if (rdev->gart.robj) {	305	if (rdev->gart.robj) {
265	WARN(1, "RS600 GART already initialized\n");	306	WARN(1, "RS600 GART already initialized\n");
266	return 0;	307	return 0;
267	}	308	}
268	/* Initialize common gart structure */	309	/* Initialize common gart structure */
269	r = radeon_gart_init(rdev);	310	r = radeon_gart_init(rdev);
270	if (r) {	311	if (r) {
271	return r;	312	return r;
272	}	313	}
273	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;	314	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
274	return radeon_gart_table_vram_alloc(rdev);	315	return radeon_gart_table_vram_alloc(rdev);
275	}	316	}
276		317
277	static int rs600_gart_enable(struct radeon_device *rdev)	318	static int rs600_gart_enable(struct radeon_device *rdev)
278	{	319	{
279	u32 tmp;	320	u32 tmp;
280	int r, i;	321	int r, i;
281		322
282	if (rdev->gart.robj == NULL) {	323	if (rdev->gart.robj == NULL) {
283	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");	324	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
284	return -EINVAL;	325	return -EINVAL;
285	}	326	}
286	r = radeon_gart_table_vram_pin(rdev);	327	r = radeon_gart_table_vram_pin(rdev);
287	if (r)	328	if (r)
288	return r;	329	return r;
289	radeon_gart_restore(rdev);	330	radeon_gart_restore(rdev);
290	/* Enable bus master */	331	/* Enable bus master */
291	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;	332	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
292	WREG32(RADEON_BUS_CNTL, tmp);	333	WREG32(RADEON_BUS_CNTL, tmp);
293	/* FIXME: setup default page */	334	/* FIXME: setup default page */
294	WREG32_MC(R_000100_MC_PT0_CNTL,	335	WREG32_MC(R_000100_MC_PT0_CNTL,
295	(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) \|	336	(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) \|
296	S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));	337	S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
297		338
298	for (i = 0; i < 19; i++) {	339	for (i = 0; i < 19; i++) {
299	WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,	340	WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
300	S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) \|	341	S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) \|
301	S_00016C_SYSTEM_ACCESS_MODE_MASK(	342	S_00016C_SYSTEM_ACCESS_MODE_MASK(
302	V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) \|	343	V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) \|
303	S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(	344	S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
304	V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) \|	345	V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) \|
305	S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) \|	346	S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) \|
306	S_00016C_ENABLE_FRAGMENT_PROCESSING(1) \|	347	S_00016C_ENABLE_FRAGMENT_PROCESSING(1) \|
307	S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));	348	S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
308	}	349	}
309	/* enable first context */	350	/* enable first context */
310	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,	351	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
311	S_000102_ENABLE_PAGE_TABLE(1) \|	352	S_000102_ENABLE_PAGE_TABLE(1) \|
312	S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));	353	S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
313		354
314	/* disable all other contexts */	355	/* disable all other contexts */
315	for (i = 1; i < 8; i++)	356	for (i = 1; i < 8; i++)
316	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);	357	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
317		358
318	/* setup the page table */	359	/* setup the page table */
319	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,	360	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
320	rdev->gart.table_addr);	361	rdev->gart.table_addr);
321	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);	362	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
322	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);	363	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
323	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);	364	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
324		365
325	/* System context maps to VRAM space */	366	/* System context maps to VRAM space */
326	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);	367	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
327	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);	368	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
328		369
329	/* enable page tables */	370	/* enable page tables */
330	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);	371	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
331	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp \| S_000100_ENABLE_PT(1)));	372	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp \| S_000100_ENABLE_PT(1)));
332	tmp = RREG32_MC(R_000009_MC_CNTL1);	373	tmp = RREG32_MC(R_000009_MC_CNTL1);
333	WREG32_MC(R_000009_MC_CNTL1, (tmp \| S_000009_ENABLE_PAGE_TABLES(1)));	374	WREG32_MC(R_000009_MC_CNTL1, (tmp \| S_000009_ENABLE_PAGE_TABLES(1)));
334	rs600_gart_tlb_flush(rdev);	375	rs600_gart_tlb_flush(rdev);
335	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",	376	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
336	(unsigned)(rdev->mc.gtt_size >> 20),	377	(unsigned)(rdev->mc.gtt_size >> 20),
337	(unsigned long long)rdev->gart.table_addr);	378	(unsigned long long)rdev->gart.table_addr);
338	rdev->gart.ready = true;	379	rdev->gart.ready = true;
339	return 0;	380	return 0;
340	}	381	}
341		382
342	static void rs600_gart_disable(struct radeon_device *rdev)	383	static void rs600_gart_disable(struct radeon_device *rdev)
343	{	384	{
344	u32 tmp;	385	u32 tmp;
345		386
346	/* FIXME: disable out of gart access */	387	/* FIXME: disable out of gart access */
347	WREG32_MC(R_000100_MC_PT0_CNTL, 0);	388	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
348	tmp = RREG32_MC(R_000009_MC_CNTL1);	389	tmp = RREG32_MC(R_000009_MC_CNTL1);
349	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);	390	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
350	radeon_gart_table_vram_unpin(rdev);	391	radeon_gart_table_vram_unpin(rdev);
351	}	392	}
352		393
353	static void rs600_gart_fini(struct radeon_device *rdev)	394	static void rs600_gart_fini(struct radeon_device *rdev)
354	{	395	{
355	radeon_gart_fini(rdev);	396	radeon_gart_fini(rdev);
356	rs600_gart_disable(rdev);	397	rs600_gart_disable(rdev);
357	radeon_gart_table_vram_free(rdev);	398	radeon_gart_table_vram_free(rdev);
358	}	399	}
359		400
360	#define R600_PTE_VALID (1 << 0)	401	#define R600_PTE_VALID (1 << 0)
361	#define R600_PTE_SYSTEM (1 << 1)	402	#define R600_PTE_SYSTEM (1 << 1)
362	#define R600_PTE_SNOOPED (1 << 2)	403	#define R600_PTE_SNOOPED (1 << 2)
363	#define R600_PTE_READABLE (1 << 5)	404	#define R600_PTE_READABLE (1 << 5)
364	#define R600_PTE_WRITEABLE (1 << 6)	405	#define R600_PTE_WRITEABLE (1 << 6)
365		406
366	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)	407	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
367	{	408	{
368	void __iomem ptr = (void )rdev->gart.ptr;	409	void __iomem ptr = (void )rdev->gart.ptr;
369		410
370	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {	411	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
371	return -EINVAL;	412	return -EINVAL;
372	}	413	}
373	addr = addr & 0xFFFFFFFFFFFFF000ULL;	414	addr = addr & 0xFFFFFFFFFFFFF000ULL;
374	addr \|= R600_PTE_VALID \| R600_PTE_SYSTEM \| R600_PTE_SNOOPED;	415	addr \|= R600_PTE_VALID \| R600_PTE_SYSTEM \| R600_PTE_SNOOPED;
375	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;	416	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;
376	writeq(addr, ptr + (i * 8));	417	writeq(addr, ptr + (i * 8));
377	return 0;	418	return 0;
378	}	419	}
379		420
380	int rs600_irq_set(struct radeon_device *rdev)	421	int rs600_irq_set(struct radeon_device *rdev)
381	{	422	{
382	uint32_t tmp = 0;	423	uint32_t tmp = 0;
383	uint32_t mode_int = 0;	424	uint32_t mode_int = 0;
384	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &	425	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
385	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);	426	~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
386	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &	427	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
387	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);	428	~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
388	u32 hdmi0;	429	u32 hdmi0;
389	if (ASIC_IS_DCE2(rdev))	430	if (ASIC_IS_DCE2(rdev))
390	hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &	431	hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
391	~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);	432	~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
392	else	433	else
393	hdmi0 = 0;	434	hdmi0 = 0;
394		435
395	if (!rdev->irq.installed) {	436	if (!rdev->irq.installed) {
396	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");	437	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
397	WREG32(R_000040_GEN_INT_CNTL, 0);	438	WREG32(R_000040_GEN_INT_CNTL, 0);
398	return -EINVAL;	439	return -EINVAL;
399	}	440	}
400	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {	441	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
401	tmp \|= S_000040_SW_INT_EN(1);	442	tmp \|= S_000040_SW_INT_EN(1);
402	}	443	}
403	if (rdev->irq.crtc_vblank_int[0] \|\|	444	if (rdev->irq.crtc_vblank_int[0] \|\|
404	atomic_read(&rdev->irq.pflip[0])) {	445	atomic_read(&rdev->irq.pflip[0])) {
405	mode_int \|= S_006540_D1MODE_VBLANK_INT_MASK(1);	446	mode_int \|= S_006540_D1MODE_VBLANK_INT_MASK(1);
406	}	447	}
407	if (rdev->irq.crtc_vblank_int[1] \|\|	448	if (rdev->irq.crtc_vblank_int[1] \|\|
408	atomic_read(&rdev->irq.pflip[1])) {	449	atomic_read(&rdev->irq.pflip[1])) {
409	mode_int \|= S_006540_D2MODE_VBLANK_INT_MASK(1);	450	mode_int \|= S_006540_D2MODE_VBLANK_INT_MASK(1);
410	}	451	}
411	if (rdev->irq.hpd[0]) {	452	if (rdev->irq.hpd[0]) {
412	hpd1 \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);	453	hpd1 \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
413	}	454	}
414	if (rdev->irq.hpd[1]) {	455	if (rdev->irq.hpd[1]) {
415	hpd2 \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);	456	hpd2 \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
416	}	457	}
417	if (rdev->irq.afmt[0]) {	458	if (rdev->irq.afmt[0]) {
418	hdmi0 \|= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);	459	hdmi0 \|= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
419	}	460	}
420	WREG32(R_000040_GEN_INT_CNTL, tmp);	461	WREG32(R_000040_GEN_INT_CNTL, tmp);
421	WREG32(R_006540_DxMODE_INT_MASK, mode_int);	462	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
422	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);	463	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
423	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);	464	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
424	if (ASIC_IS_DCE2(rdev))	465	if (ASIC_IS_DCE2(rdev))
425	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);	466	WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
426	return 0;	467	return 0;
427	}	468	}
428		469
429	static inline u32 rs600_irq_ack(struct radeon_device *rdev)	470	static inline u32 rs600_irq_ack(struct radeon_device *rdev)
430	{	471	{
431	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);	472	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
432	uint32_t irq_mask = S_000044_SW_INT(1);	473	uint32_t irq_mask = S_000044_SW_INT(1);
433	u32 tmp;	474	u32 tmp;
434		475
435	if (G_000044_DISPLAY_INT_STAT(irqs)) {	476	if (G_000044_DISPLAY_INT_STAT(irqs)) {
436	rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);	477	rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
437	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	478	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
438	WREG32(R_006534_D1MODE_VBLANK_STATUS,	479	WREG32(R_006534_D1MODE_VBLANK_STATUS,
439	S_006534_D1MODE_VBLANK_ACK(1));	480	S_006534_D1MODE_VBLANK_ACK(1));
440	}	481	}
441	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	482	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
442	WREG32(R_006D34_D2MODE_VBLANK_STATUS,	483	WREG32(R_006D34_D2MODE_VBLANK_STATUS,
443	S_006D34_D2MODE_VBLANK_ACK(1));	484	S_006D34_D2MODE_VBLANK_ACK(1));
444	}	485	}
445	if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	486	if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
446	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);	487	tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
447	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);	488	tmp \|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
448	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);	489	WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
449	}	490	}
450	if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {	491	if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
451	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);	492	tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
452	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);	493	tmp \|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
453	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);	494	WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
454	}	495	}
455	} else {	496	} else {
456	rdev->irq.stat_regs.r500.disp_int = 0;	497	rdev->irq.stat_regs.r500.disp_int = 0;
457	}	498	}
458		499

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rs600.c – Rev 3192 → 3764