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Rev 3192 | Rev 3764 | ||
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Line 50... | Line 50... | ||
50 | { |
50 | { |
51 | 0, |
51 | 0, |
52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
53 | }; |
53 | }; |
Line -... | Line 54... | ||
- | 54 | ||
- | 55 | static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) |
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- | 56 | { |
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- | 57 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
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- | 58 | return true; |
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- | 59 | else |
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- | 60 | return false; |
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- | 61 | } |
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- | 62 | ||
- | 63 | static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) |
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- | 64 | { |
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- | 65 | u32 pos1, pos2; |
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- | 66 | ||
- | 67 | pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
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- | 68 | pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
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- | 69 | ||
- | 70 | if (pos1 != pos2) |
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- | 71 | return true; |
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- | 72 | else |
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- | 73 | return false; |
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- | 74 | } |
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- | 75 | ||
- | 76 | /** |
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- | 77 | * avivo_wait_for_vblank - vblank wait asic callback. |
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- | 78 | * |
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- | 79 | * @rdev: radeon_device pointer |
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- | 80 | * @crtc: crtc to wait for vblank on |
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- | 81 | * |
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- | 82 | * Wait for vblank on the requested crtc (r5xx-r7xx). |
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54 | 83 | */ |
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55 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
84 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
56 | { |
85 | { |
Line 57... | Line 86... | ||
57 | int i; |
86 | unsigned i = 0; |
58 | 87 | ||
Line 59... | Line 88... | ||
59 | if (crtc >= rdev->num_crtc) |
88 | if (crtc >= rdev->num_crtc) |
- | 89 | return; |
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- | 90 | ||
- | 91 | if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) |
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- | 92 | return; |
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- | 93 | ||
- | 94 | /* depending on when we hit vblank, we may be close to active; if so, |
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- | 95 | * wait for another frame. |
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- | 96 | */ |
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- | 97 | while (avivo_is_in_vblank(rdev, crtc)) { |
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- | 98 | if (i++ % 100 == 0) { |
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- | 99 | if (!avivo_is_counter_moving(rdev, crtc)) |
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- | 100 | break; |
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60 | return; |
101 | } |
- | 102 | } |
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61 | 103 | ||
62 | if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { |
104 | while (!avivo_is_in_vblank(rdev, crtc)) { |
63 | for (i = 0; i < rdev->usec_timeout; i++) { |
- | |
64 | if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) |
105 | if (i++ % 100 == 0) { |
65 | break; |
106 | if (!avivo_is_counter_moving(rdev, crtc)) |
66 | udelay(1); |
107 | break; |
67 | } |
108 | } |
68 | for (i = 0; i < rdev->usec_timeout; i++) { |
109 | for (i = 0; i < rdev->usec_timeout; i++) { |
Line 710... | Line 751... | ||
710 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
751 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
711 | return r; |
752 | return r; |
712 | } |
753 | } |
Line 713... | Line 754... | ||
713 | 754 | ||
- | 755 | /* Enable IRQ */ |
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- | 756 | if (!rdev->irq.installed) { |
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- | 757 | r = radeon_irq_kms_init(rdev); |
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- | 758 | if (r) |
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- | 759 | return r; |
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- | 760 | } |
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714 | /* Enable IRQ */ |
761 | |
715 | rs600_irq_set(rdev); |
762 | rs600_irq_set(rdev); |
716 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
763 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
717 | /* 1M ring buffer */ |
764 | /* 1M ring buffer */ |
718 | r = r100_cp_init(rdev, 1024 * 1024); |
765 | r = r100_cp_init(rdev, 1024 * 1024); |
Line 776... | Line 823... | ||
776 | rs600_debugfs(rdev); |
823 | rs600_debugfs(rdev); |
777 | /* Fence driver */ |
824 | /* Fence driver */ |
778 | r = radeon_fence_driver_init(rdev); |
825 | r = radeon_fence_driver_init(rdev); |
779 | if (r) |
826 | if (r) |
780 | return r; |
827 | return r; |
781 | r = radeon_irq_kms_init(rdev); |
- | |
782 | if (r) |
- | |
783 | return r; |
- | |
784 | /* Memory manager */ |
828 | /* Memory manager */ |
785 | r = radeon_bo_init(rdev); |
829 | r = radeon_bo_init(rdev); |
786 | if (r) |
830 | if (r) |
787 | return r; |
831 | return r; |
788 | r = rs600_gart_init(rdev); |
832 | r = rs600_gart_init(rdev); |