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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * |
29 | * |
30 | * This file gather function specific to RS600 which is the IGP of |
30 | * This file gather function specific to RS600 which is the IGP of |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
33 | * the avivo one, bios is an atombios, 3D block are the one of the |
33 | * the avivo one, bios is an atombios, 3D block are the one of the |
34 | * R4XX family. The GART is different from the RS400 one and is very |
34 | * R4XX family. The GART is different from the RS400 one and is very |
35 | * close to the one of the R600 family (R600 likely being an evolution |
35 | * close to the one of the R600 family (R600 likely being an evolution |
36 | * of the RS600 GART block). |
36 | * of the RS600 GART block). |
37 | */ |
37 | */ |
38 | #include |
38 | #include |
39 | #include "radeon.h" |
39 | #include "radeon.h" |
40 | #include "radeon_asic.h" |
40 | #include "radeon_asic.h" |
41 | #include "atom.h" |
41 | #include "atom.h" |
42 | #include "rs600d.h" |
42 | #include "rs600d.h" |
43 | 43 | ||
44 | #include "rs600_reg_safe.h" |
44 | #include "rs600_reg_safe.h" |
45 | 45 | ||
46 | static void rs600_gpu_init(struct radeon_device *rdev); |
46 | static void rs600_gpu_init(struct radeon_device *rdev); |
47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
48 | 48 | ||
49 | static const u32 crtc_offsets[2] = |
49 | static const u32 crtc_offsets[2] = |
50 | { |
50 | { |
51 | 0, |
51 | 0, |
52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
52 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
53 | }; |
53 | }; |
54 | 54 | ||
55 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
55 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
56 | { |
56 | { |
57 | int i; |
57 | int i; |
58 | 58 | ||
59 | if (crtc >= rdev->num_crtc) |
59 | if (crtc >= rdev->num_crtc) |
60 | return; |
60 | return; |
61 | 61 | ||
62 | if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { |
62 | if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { |
63 | for (i = 0; i < rdev->usec_timeout; i++) { |
63 | for (i = 0; i < rdev->usec_timeout; i++) { |
64 | if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) |
64 | if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) |
65 | break; |
65 | break; |
66 | udelay(1); |
66 | udelay(1); |
67 | } |
67 | } |
68 | for (i = 0; i < rdev->usec_timeout; i++) { |
68 | for (i = 0; i < rdev->usec_timeout; i++) { |
69 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
69 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
70 | break; |
70 | break; |
71 | udelay(1); |
71 | udelay(1); |
72 | } |
72 | } |
73 | } |
73 | } |
74 | } |
74 | } |
75 | /* hpd for digital panel detect/disconnect */ |
75 | /* hpd for digital panel detect/disconnect */ |
76 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
76 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
77 | { |
77 | { |
78 | u32 tmp; |
78 | u32 tmp; |
79 | bool connected = false; |
79 | bool connected = false; |
80 | 80 | ||
81 | switch (hpd) { |
81 | switch (hpd) { |
82 | case RADEON_HPD_1: |
82 | case RADEON_HPD_1: |
83 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
83 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
84 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
84 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
85 | connected = true; |
85 | connected = true; |
86 | break; |
86 | break; |
87 | case RADEON_HPD_2: |
87 | case RADEON_HPD_2: |
88 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
88 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
89 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
89 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
90 | connected = true; |
90 | connected = true; |
91 | break; |
91 | break; |
92 | default: |
92 | default: |
93 | break; |
93 | break; |
94 | } |
94 | } |
95 | return connected; |
95 | return connected; |
96 | } |
96 | } |
97 | 97 | ||
98 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
98 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
99 | enum radeon_hpd_id hpd) |
99 | enum radeon_hpd_id hpd) |
100 | { |
100 | { |
101 | u32 tmp; |
101 | u32 tmp; |
102 | bool connected = rs600_hpd_sense(rdev, hpd); |
102 | bool connected = rs600_hpd_sense(rdev, hpd); |
103 | 103 | ||
104 | switch (hpd) { |
104 | switch (hpd) { |
105 | case RADEON_HPD_1: |
105 | case RADEON_HPD_1: |
106 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
106 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
107 | if (connected) |
107 | if (connected) |
108 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
108 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
109 | else |
109 | else |
110 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
110 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
111 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
111 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
112 | break; |
112 | break; |
113 | case RADEON_HPD_2: |
113 | case RADEON_HPD_2: |
114 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
114 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
115 | if (connected) |
115 | if (connected) |
116 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
116 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
117 | else |
117 | else |
118 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
118 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
119 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
119 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
120 | break; |
120 | break; |
121 | default: |
121 | default: |
122 | break; |
122 | break; |
123 | } |
123 | } |
124 | } |
124 | } |
125 | 125 | ||
126 | void rs600_hpd_init(struct radeon_device *rdev) |
126 | void rs600_hpd_init(struct radeon_device *rdev) |
127 | { |
127 | { |
128 | struct drm_device *dev = rdev->ddev; |
128 | struct drm_device *dev = rdev->ddev; |
129 | struct drm_connector *connector; |
129 | struct drm_connector *connector; |
130 | unsigned enable = 0; |
130 | unsigned enable = 0; |
131 | 131 | ||
132 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
132 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
133 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
133 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
134 | switch (radeon_connector->hpd.hpd) { |
134 | switch (radeon_connector->hpd.hpd) { |
135 | case RADEON_HPD_1: |
135 | case RADEON_HPD_1: |
136 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
136 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
137 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
137 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
138 | break; |
138 | break; |
139 | case RADEON_HPD_2: |
139 | case RADEON_HPD_2: |
140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
142 | break; |
142 | break; |
143 | default: |
143 | default: |
144 | break; |
144 | break; |
145 | } |
145 | } |
146 | enable |= 1 << radeon_connector->hpd.hpd; |
146 | enable |= 1 << radeon_connector->hpd.hpd; |
147 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
147 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
148 | } |
148 | } |
149 | // radeon_irq_kms_enable_hpd(rdev, enable); |
149 | // radeon_irq_kms_enable_hpd(rdev, enable); |
150 | } |
150 | } |
151 | 151 | ||
152 | void rs600_hpd_fini(struct radeon_device *rdev) |
152 | void rs600_hpd_fini(struct radeon_device *rdev) |
153 | { |
153 | { |
154 | struct drm_device *dev = rdev->ddev; |
154 | struct drm_device *dev = rdev->ddev; |
155 | struct drm_connector *connector; |
155 | struct drm_connector *connector; |
156 | unsigned disable = 0; |
156 | unsigned disable = 0; |
157 | 157 | ||
158 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
158 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
159 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
159 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
160 | switch (radeon_connector->hpd.hpd) { |
160 | switch (radeon_connector->hpd.hpd) { |
161 | case RADEON_HPD_1: |
161 | case RADEON_HPD_1: |
162 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
162 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
163 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
163 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
164 | break; |
164 | break; |
165 | case RADEON_HPD_2: |
165 | case RADEON_HPD_2: |
166 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
166 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
167 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
167 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
168 | break; |
168 | break; |
169 | default: |
169 | default: |
170 | break; |
170 | break; |
171 | } |
171 | } |
172 | disable |= 1 << radeon_connector->hpd.hpd; |
172 | disable |= 1 << radeon_connector->hpd.hpd; |
173 | } |
173 | } |
174 | // radeon_irq_kms_disable_hpd(rdev, disable); |
174 | // radeon_irq_kms_disable_hpd(rdev, disable); |
175 | } |
175 | } |
176 | 176 | ||
177 | int rs600_asic_reset(struct radeon_device *rdev) |
177 | int rs600_asic_reset(struct radeon_device *rdev) |
178 | { |
178 | { |
179 | struct rv515_mc_save save; |
179 | struct rv515_mc_save save; |
180 | u32 status, tmp; |
180 | u32 status, tmp; |
181 | int ret = 0; |
181 | int ret = 0; |
182 | 182 | ||
183 | status = RREG32(R_000E40_RBBM_STATUS); |
183 | status = RREG32(R_000E40_RBBM_STATUS); |
184 | if (!G_000E40_GUI_ACTIVE(status)) { |
184 | if (!G_000E40_GUI_ACTIVE(status)) { |
185 | return 0; |
185 | return 0; |
186 | } |
186 | } |
187 | /* Stops all mc clients */ |
187 | /* Stops all mc clients */ |
188 | rv515_mc_stop(rdev, &save); |
188 | rv515_mc_stop(rdev, &save); |
189 | status = RREG32(R_000E40_RBBM_STATUS); |
189 | status = RREG32(R_000E40_RBBM_STATUS); |
190 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
190 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
191 | /* stop CP */ |
191 | /* stop CP */ |
192 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
192 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
193 | tmp = RREG32(RADEON_CP_RB_CNTL); |
193 | tmp = RREG32(RADEON_CP_RB_CNTL); |
194 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
194 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
195 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
195 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
196 | WREG32(RADEON_CP_RB_WPTR, 0); |
196 | WREG32(RADEON_CP_RB_WPTR, 0); |
197 | WREG32(RADEON_CP_RB_CNTL, tmp); |
197 | WREG32(RADEON_CP_RB_CNTL, tmp); |
198 | // pci_save_state(rdev->pdev); |
198 | // pci_save_state(rdev->pdev); |
199 | /* disable bus mastering */ |
199 | /* disable bus mastering */ |
200 | // pci_clear_master(rdev->pdev); |
200 | // pci_clear_master(rdev->pdev); |
201 | mdelay(1); |
201 | mdelay(1); |
202 | /* reset GA+VAP */ |
202 | /* reset GA+VAP */ |
203 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
203 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
204 | S_0000F0_SOFT_RESET_GA(1)); |
204 | S_0000F0_SOFT_RESET_GA(1)); |
205 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
205 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
206 | mdelay(500); |
206 | mdelay(500); |
207 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
207 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
208 | mdelay(1); |
208 | mdelay(1); |
209 | status = RREG32(R_000E40_RBBM_STATUS); |
209 | status = RREG32(R_000E40_RBBM_STATUS); |
210 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
210 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
211 | /* reset CP */ |
211 | /* reset CP */ |
212 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
212 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
213 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
213 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
214 | mdelay(500); |
214 | mdelay(500); |
215 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
215 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
216 | mdelay(1); |
216 | mdelay(1); |
217 | status = RREG32(R_000E40_RBBM_STATUS); |
217 | status = RREG32(R_000E40_RBBM_STATUS); |
218 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
218 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
219 | /* reset MC */ |
219 | /* reset MC */ |
220 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
220 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
221 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
221 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
222 | mdelay(500); |
222 | mdelay(500); |
223 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
223 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
224 | mdelay(1); |
224 | mdelay(1); |
225 | status = RREG32(R_000E40_RBBM_STATUS); |
225 | status = RREG32(R_000E40_RBBM_STATUS); |
226 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
226 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
227 | /* restore PCI & busmastering */ |
227 | /* restore PCI & busmastering */ |
228 | // pci_restore_state(rdev->pdev); |
228 | // pci_restore_state(rdev->pdev); |
229 | /* Check if GPU is idle */ |
229 | /* Check if GPU is idle */ |
230 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
230 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
231 | dev_err(rdev->dev, "failed to reset GPU\n"); |
231 | dev_err(rdev->dev, "failed to reset GPU\n"); |
232 | ret = -1; |
232 | ret = -1; |
233 | } else |
233 | } else |
234 | dev_info(rdev->dev, "GPU reset succeed\n"); |
234 | dev_info(rdev->dev, "GPU reset succeed\n"); |
235 | rv515_mc_resume(rdev, &save); |
235 | rv515_mc_resume(rdev, &save); |
236 | return ret; |
236 | return ret; |
237 | } |
237 | } |
238 | 238 | ||
239 | /* |
239 | /* |
240 | * GART. |
240 | * GART. |
241 | */ |
241 | */ |
242 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
242 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
243 | { |
243 | { |
244 | uint32_t tmp; |
244 | uint32_t tmp; |
245 | 245 | ||
246 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
246 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
247 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
247 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
248 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
248 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
249 | 249 | ||
250 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
250 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
251 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
251 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
252 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
252 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
253 | 253 | ||
254 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
254 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
255 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
255 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
256 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
256 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
257 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
257 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
258 | } |
258 | } |
259 | 259 | ||
260 | static int rs600_gart_init(struct radeon_device *rdev) |
260 | static int rs600_gart_init(struct radeon_device *rdev) |
261 | { |
261 | { |
262 | int r; |
262 | int r; |
263 | 263 | ||
264 | if (rdev->gart.robj) { |
264 | if (rdev->gart.robj) { |
265 | WARN(1, "RS600 GART already initialized\n"); |
265 | WARN(1, "RS600 GART already initialized\n"); |
266 | return 0; |
266 | return 0; |
267 | } |
267 | } |
268 | /* Initialize common gart structure */ |
268 | /* Initialize common gart structure */ |
269 | r = radeon_gart_init(rdev); |
269 | r = radeon_gart_init(rdev); |
270 | if (r) { |
270 | if (r) { |
271 | return r; |
271 | return r; |
272 | } |
272 | } |
273 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
273 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
274 | return radeon_gart_table_vram_alloc(rdev); |
274 | return radeon_gart_table_vram_alloc(rdev); |
275 | } |
275 | } |
276 | 276 | ||
277 | static int rs600_gart_enable(struct radeon_device *rdev) |
277 | static int rs600_gart_enable(struct radeon_device *rdev) |
278 | { |
278 | { |
279 | u32 tmp; |
279 | u32 tmp; |
280 | int r, i; |
280 | int r, i; |
281 | 281 | ||
282 | if (rdev->gart.robj == NULL) { |
282 | if (rdev->gart.robj == NULL) { |
283 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
283 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
284 | return -EINVAL; |
284 | return -EINVAL; |
285 | } |
285 | } |
286 | r = radeon_gart_table_vram_pin(rdev); |
286 | r = radeon_gart_table_vram_pin(rdev); |
287 | if (r) |
287 | if (r) |
288 | return r; |
288 | return r; |
289 | radeon_gart_restore(rdev); |
289 | radeon_gart_restore(rdev); |
290 | /* Enable bus master */ |
290 | /* Enable bus master */ |
291 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
291 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
292 | WREG32(RADEON_BUS_CNTL, tmp); |
292 | WREG32(RADEON_BUS_CNTL, tmp); |
293 | /* FIXME: setup default page */ |
293 | /* FIXME: setup default page */ |
294 | WREG32_MC(R_000100_MC_PT0_CNTL, |
294 | WREG32_MC(R_000100_MC_PT0_CNTL, |
295 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
295 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
296 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
296 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
297 | 297 | ||
298 | for (i = 0; i < 19; i++) { |
298 | for (i = 0; i < 19; i++) { |
299 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
299 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
300 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
300 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
301 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
301 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
302 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
302 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
303 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
303 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
304 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
304 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
305 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
305 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
306 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
306 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
307 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
307 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
308 | } |
308 | } |
309 | /* enable first context */ |
309 | /* enable first context */ |
310 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
310 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
311 | S_000102_ENABLE_PAGE_TABLE(1) | |
311 | S_000102_ENABLE_PAGE_TABLE(1) | |
312 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
312 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
313 | 313 | ||
314 | /* disable all other contexts */ |
314 | /* disable all other contexts */ |
315 | for (i = 1; i < 8; i++) |
315 | for (i = 1; i < 8; i++) |
316 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
316 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
317 | 317 | ||
318 | /* setup the page table */ |
318 | /* setup the page table */ |
319 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
319 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
320 | rdev->gart.table_addr); |
320 | rdev->gart.table_addr); |
321 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
321 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
322 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
322 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
323 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
323 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
324 | 324 | ||
325 | /* System context maps to VRAM space */ |
325 | /* System context maps to VRAM space */ |
326 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
326 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
327 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
327 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
328 | 328 | ||
329 | /* enable page tables */ |
329 | /* enable page tables */ |
330 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
330 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
331 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
331 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
332 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
332 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
333 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
333 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
334 | rs600_gart_tlb_flush(rdev); |
334 | rs600_gart_tlb_flush(rdev); |
335 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
335 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
336 | (unsigned)(rdev->mc.gtt_size >> 20), |
336 | (unsigned)(rdev->mc.gtt_size >> 20), |
337 | (unsigned long long)rdev->gart.table_addr); |
337 | (unsigned long long)rdev->gart.table_addr); |
338 | rdev->gart.ready = true; |
338 | rdev->gart.ready = true; |
339 | return 0; |
339 | return 0; |
340 | } |
340 | } |
341 | 341 | ||
342 | static void rs600_gart_disable(struct radeon_device *rdev) |
342 | static void rs600_gart_disable(struct radeon_device *rdev) |
343 | { |
343 | { |
344 | u32 tmp; |
344 | u32 tmp; |
345 | 345 | ||
346 | /* FIXME: disable out of gart access */ |
346 | /* FIXME: disable out of gart access */ |
347 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
347 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
348 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
348 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
349 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
349 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
350 | radeon_gart_table_vram_unpin(rdev); |
350 | radeon_gart_table_vram_unpin(rdev); |
351 | } |
351 | } |
352 | 352 | ||
353 | static void rs600_gart_fini(struct radeon_device *rdev) |
353 | static void rs600_gart_fini(struct radeon_device *rdev) |
354 | { |
354 | { |
355 | radeon_gart_fini(rdev); |
355 | radeon_gart_fini(rdev); |
356 | rs600_gart_disable(rdev); |
356 | rs600_gart_disable(rdev); |
357 | radeon_gart_table_vram_free(rdev); |
357 | radeon_gart_table_vram_free(rdev); |
358 | } |
358 | } |
359 | 359 | ||
360 | #define R600_PTE_VALID (1 << 0) |
360 | #define R600_PTE_VALID (1 << 0) |
361 | #define R600_PTE_SYSTEM (1 << 1) |
361 | #define R600_PTE_SYSTEM (1 << 1) |
362 | #define R600_PTE_SNOOPED (1 << 2) |
362 | #define R600_PTE_SNOOPED (1 << 2) |
363 | #define R600_PTE_READABLE (1 << 5) |
363 | #define R600_PTE_READABLE (1 << 5) |
364 | #define R600_PTE_WRITEABLE (1 << 6) |
364 | #define R600_PTE_WRITEABLE (1 << 6) |
365 | 365 | ||
366 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
366 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
367 | { |
367 | { |
368 | void __iomem *ptr = (void *)rdev->gart.ptr; |
368 | void __iomem *ptr = (void *)rdev->gart.ptr; |
369 | 369 | ||
370 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
370 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
371 | return -EINVAL; |
371 | return -EINVAL; |
372 | } |
372 | } |
373 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
373 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
374 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
374 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
375 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
375 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
376 | writeq(addr, ptr + (i * 8)); |
376 | writeq(addr, ptr + (i * 8)); |
377 | return 0; |
377 | return 0; |
378 | } |
378 | } |
379 | 379 | ||
380 | int rs600_irq_set(struct radeon_device *rdev) |
380 | int rs600_irq_set(struct radeon_device *rdev) |
381 | { |
381 | { |
382 | uint32_t tmp = 0; |
382 | uint32_t tmp = 0; |
383 | uint32_t mode_int = 0; |
383 | uint32_t mode_int = 0; |
384 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
384 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
385 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
385 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
386 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
386 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
387 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
387 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
388 | u32 hdmi0; |
388 | u32 hdmi0; |
389 | if (ASIC_IS_DCE2(rdev)) |
389 | if (ASIC_IS_DCE2(rdev)) |
390 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
390 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
391 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
391 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
392 | else |
392 | else |
393 | hdmi0 = 0; |
393 | hdmi0 = 0; |
394 | 394 | ||
395 | if (!rdev->irq.installed) { |
395 | if (!rdev->irq.installed) { |
396 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
396 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
397 | WREG32(R_000040_GEN_INT_CNTL, 0); |
397 | WREG32(R_000040_GEN_INT_CNTL, 0); |
398 | return -EINVAL; |
398 | return -EINVAL; |
399 | } |
399 | } |
400 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
400 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
401 | tmp |= S_000040_SW_INT_EN(1); |
401 | tmp |= S_000040_SW_INT_EN(1); |
402 | } |
402 | } |
403 | if (rdev->irq.crtc_vblank_int[0] || |
403 | if (rdev->irq.crtc_vblank_int[0] || |
404 | atomic_read(&rdev->irq.pflip[0])) { |
404 | atomic_read(&rdev->irq.pflip[0])) { |
405 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
405 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
406 | } |
406 | } |
407 | if (rdev->irq.crtc_vblank_int[1] || |
407 | if (rdev->irq.crtc_vblank_int[1] || |
408 | atomic_read(&rdev->irq.pflip[1])) { |
408 | atomic_read(&rdev->irq.pflip[1])) { |
409 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
409 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
410 | } |
410 | } |
411 | if (rdev->irq.hpd[0]) { |
411 | if (rdev->irq.hpd[0]) { |
412 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
412 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
413 | } |
413 | } |
414 | if (rdev->irq.hpd[1]) { |
414 | if (rdev->irq.hpd[1]) { |
415 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
415 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
416 | } |
416 | } |
417 | if (rdev->irq.afmt[0]) { |
417 | if (rdev->irq.afmt[0]) { |
418 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
418 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
419 | } |
419 | } |
420 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
420 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
421 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
421 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
422 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
422 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
423 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
423 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
424 | if (ASIC_IS_DCE2(rdev)) |
424 | if (ASIC_IS_DCE2(rdev)) |
425 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
425 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
426 | return 0; |
426 | return 0; |
427 | } |
427 | } |
428 | 428 | ||
429 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
429 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
430 | { |
430 | { |
431 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
431 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
432 | uint32_t irq_mask = S_000044_SW_INT(1); |
432 | uint32_t irq_mask = S_000044_SW_INT(1); |
433 | u32 tmp; |
433 | u32 tmp; |
434 | 434 | ||
435 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
435 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
436 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
436 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
437 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
437 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
438 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
438 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
439 | S_006534_D1MODE_VBLANK_ACK(1)); |
439 | S_006534_D1MODE_VBLANK_ACK(1)); |
440 | } |
440 | } |
441 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
441 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
442 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
442 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
443 | S_006D34_D2MODE_VBLANK_ACK(1)); |
443 | S_006D34_D2MODE_VBLANK_ACK(1)); |
444 | } |
444 | } |
445 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
445 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
446 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
446 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
447 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
447 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
448 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
448 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
449 | } |
449 | } |
450 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
450 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
451 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
451 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
452 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
452 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
453 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
453 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
454 | } |
454 | } |
455 | } else { |
455 | } else { |
456 | rdev->irq.stat_regs.r500.disp_int = 0; |
456 | rdev->irq.stat_regs.r500.disp_int = 0; |
457 | } |
457 | } |
458 | 458 | ||
459 | if (ASIC_IS_DCE2(rdev)) { |
459 | if (ASIC_IS_DCE2(rdev)) { |
460 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
460 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
461 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
461 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
462 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
462 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
463 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
463 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
464 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
464 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
465 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
465 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
466 | } |
466 | } |
467 | } else |
467 | } else |
468 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
468 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
469 | 469 | ||
470 | if (irqs) { |
470 | if (irqs) { |
471 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
471 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
472 | } |
472 | } |
473 | return irqs & irq_mask; |
473 | return irqs & irq_mask; |
474 | } |
474 | } |
475 | 475 | ||
476 | void rs600_irq_disable(struct radeon_device *rdev) |
476 | void rs600_irq_disable(struct radeon_device *rdev) |
477 | { |
477 | { |
478 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
478 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
479 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
479 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
480 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
480 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
481 | WREG32(R_000040_GEN_INT_CNTL, 0); |
481 | WREG32(R_000040_GEN_INT_CNTL, 0); |
482 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
482 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
483 | /* Wait and acknowledge irq */ |
483 | /* Wait and acknowledge irq */ |
484 | mdelay(1); |
484 | mdelay(1); |
485 | rs600_irq_ack(rdev); |
485 | rs600_irq_ack(rdev); |
486 | } |
486 | } |
487 | 487 | ||
488 | int rs600_irq_process(struct radeon_device *rdev) |
488 | int rs600_irq_process(struct radeon_device *rdev) |
489 | { |
489 | { |
490 | u32 status, msi_rearm; |
490 | u32 status, msi_rearm; |
491 | bool queue_hotplug = false; |
491 | bool queue_hotplug = false; |
492 | bool queue_hdmi = false; |
492 | bool queue_hdmi = false; |
493 | 493 | ||
494 | status = rs600_irq_ack(rdev); |
494 | status = rs600_irq_ack(rdev); |
495 | if (!status && |
495 | if (!status && |
496 | !rdev->irq.stat_regs.r500.disp_int && |
496 | !rdev->irq.stat_regs.r500.disp_int && |
497 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
497 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
498 | return IRQ_NONE; |
498 | return IRQ_NONE; |
499 | } |
499 | } |
500 | while (status || |
500 | while (status || |
501 | rdev->irq.stat_regs.r500.disp_int || |
501 | rdev->irq.stat_regs.r500.disp_int || |
502 | rdev->irq.stat_regs.r500.hdmi0_status) { |
502 | rdev->irq.stat_regs.r500.hdmi0_status) { |
503 | /* SW interrupt */ |
503 | /* SW interrupt */ |
504 | if (G_000044_SW_INT(status)) { |
504 | if (G_000044_SW_INT(status)) { |
505 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
505 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
506 | } |
506 | } |
507 | /* Vertical blank interrupts */ |
507 | /* Vertical blank interrupts */ |
508 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
508 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
509 | if (rdev->irq.crtc_vblank_int[0]) { |
509 | if (rdev->irq.crtc_vblank_int[0]) { |
510 | // drm_handle_vblank(rdev->ddev, 0); |
510 | // drm_handle_vblank(rdev->ddev, 0); |
511 | rdev->pm.vblank_sync = true; |
511 | rdev->pm.vblank_sync = true; |
512 | // wake_up(&rdev->irq.vblank_queue); |
512 | // wake_up(&rdev->irq.vblank_queue); |
513 | } |
513 | } |
514 | // if (rdev->irq.pflip[0]) |
514 | // if (rdev->irq.pflip[0]) |
515 | // radeon_crtc_handle_flip(rdev, 0); |
515 | // radeon_crtc_handle_flip(rdev, 0); |
516 | } |
516 | } |
517 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
517 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
518 | if (rdev->irq.crtc_vblank_int[1]) { |
518 | if (rdev->irq.crtc_vblank_int[1]) { |
519 | // drm_handle_vblank(rdev->ddev, 1); |
519 | // drm_handle_vblank(rdev->ddev, 1); |
520 | rdev->pm.vblank_sync = true; |
520 | rdev->pm.vblank_sync = true; |
521 | // wake_up(&rdev->irq.vblank_queue); |
521 | // wake_up(&rdev->irq.vblank_queue); |
522 | } |
522 | } |
523 | // if (rdev->irq.pflip[1]) |
523 | // if (rdev->irq.pflip[1]) |
524 | // radeon_crtc_handle_flip(rdev, 1); |
524 | // radeon_crtc_handle_flip(rdev, 1); |
525 | } |
525 | } |
526 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
526 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
527 | queue_hotplug = true; |
527 | queue_hotplug = true; |
528 | DRM_DEBUG("HPD1\n"); |
528 | DRM_DEBUG("HPD1\n"); |
529 | } |
529 | } |
530 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
530 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
531 | queue_hotplug = true; |
531 | queue_hotplug = true; |
532 | DRM_DEBUG("HPD2\n"); |
532 | DRM_DEBUG("HPD2\n"); |
533 | } |
533 | } |
534 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
534 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
535 | queue_hdmi = true; |
535 | queue_hdmi = true; |
536 | DRM_DEBUG("HDMI0\n"); |
536 | DRM_DEBUG("HDMI0\n"); |
537 | } |
537 | } |
538 | status = rs600_irq_ack(rdev); |
538 | status = rs600_irq_ack(rdev); |
539 | } |
539 | } |
540 | // if (queue_hotplug) |
540 | // if (queue_hotplug) |
541 | // schedule_work(&rdev->hotplug_work); |
541 | // schedule_work(&rdev->hotplug_work); |
542 | // if (queue_hdmi) |
542 | // if (queue_hdmi) |
543 | // schedule_work(&rdev->audio_work); |
543 | // schedule_work(&rdev->audio_work); |
544 | if (rdev->msi_enabled) { |
544 | if (rdev->msi_enabled) { |
545 | switch (rdev->family) { |
545 | switch (rdev->family) { |
546 | case CHIP_RS600: |
546 | case CHIP_RS600: |
547 | case CHIP_RS690: |
547 | case CHIP_RS690: |
548 | case CHIP_RS740: |
548 | case CHIP_RS740: |
549 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
549 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
550 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
550 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
551 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
551 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
552 | break; |
552 | break; |
553 | default: |
553 | default: |
554 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
554 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
555 | break; |
555 | break; |
556 | } |
556 | } |
557 | } |
557 | } |
558 | return IRQ_HANDLED; |
558 | return IRQ_HANDLED; |
559 | } |
559 | } |
560 | 560 | ||
561 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
561 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
562 | { |
562 | { |
563 | if (crtc == 0) |
563 | if (crtc == 0) |
564 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
564 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
565 | else |
565 | else |
566 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
566 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
567 | } |
567 | } |
568 | 568 | ||
569 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
569 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
570 | { |
570 | { |
571 | unsigned i; |
571 | unsigned i; |
572 | 572 | ||
573 | for (i = 0; i < rdev->usec_timeout; i++) { |
573 | for (i = 0; i < rdev->usec_timeout; i++) { |
574 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
574 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
575 | return 0; |
575 | return 0; |
576 | udelay(1); |
576 | udelay(1); |
577 | } |
577 | } |
578 | return -1; |
578 | return -1; |
579 | } |
579 | } |
580 | 580 | ||
581 | static void rs600_gpu_init(struct radeon_device *rdev) |
581 | static void rs600_gpu_init(struct radeon_device *rdev) |
582 | { |
582 | { |
583 | r420_pipes_init(rdev); |
583 | r420_pipes_init(rdev); |
584 | /* Wait for mc idle */ |
584 | /* Wait for mc idle */ |
585 | if (rs600_mc_wait_for_idle(rdev)) |
585 | if (rs600_mc_wait_for_idle(rdev)) |
586 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
586 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
587 | } |
587 | } |
588 | 588 | ||
589 | static void rs600_mc_init(struct radeon_device *rdev) |
589 | static void rs600_mc_init(struct radeon_device *rdev) |
590 | { |
590 | { |
591 | u64 base; |
591 | u64 base; |
592 | 592 | ||
593 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
593 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
594 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
594 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
595 | rdev->mc.vram_is_ddr = true; |
595 | rdev->mc.vram_is_ddr = true; |
596 | rdev->mc.vram_width = 128; |
596 | rdev->mc.vram_width = 128; |
597 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
597 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
598 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
598 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
599 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
599 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
600 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
600 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
601 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
601 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
602 | base = G_000004_MC_FB_START(base) << 16; |
602 | base = G_000004_MC_FB_START(base) << 16; |
603 | radeon_vram_location(rdev, &rdev->mc, base); |
603 | radeon_vram_location(rdev, &rdev->mc, base); |
604 | rdev->mc.gtt_base_align = 0; |
604 | rdev->mc.gtt_base_align = 0; |
605 | radeon_gtt_location(rdev, &rdev->mc); |
605 | radeon_gtt_location(rdev, &rdev->mc); |
606 | radeon_update_bandwidth_info(rdev); |
606 | radeon_update_bandwidth_info(rdev); |
607 | } |
607 | } |
608 | 608 | ||
609 | void rs600_bandwidth_update(struct radeon_device *rdev) |
609 | void rs600_bandwidth_update(struct radeon_device *rdev) |
610 | { |
610 | { |
611 | struct drm_display_mode *mode0 = NULL; |
611 | struct drm_display_mode *mode0 = NULL; |
612 | struct drm_display_mode *mode1 = NULL; |
612 | struct drm_display_mode *mode1 = NULL; |
613 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
613 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
614 | /* FIXME: implement full support */ |
614 | /* FIXME: implement full support */ |
615 | 615 | ||
616 | radeon_update_display_priority(rdev); |
616 | radeon_update_display_priority(rdev); |
617 | 617 | ||
618 | if (rdev->mode_info.crtcs[0]->base.enabled) |
618 | if (rdev->mode_info.crtcs[0]->base.enabled) |
619 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
619 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
620 | if (rdev->mode_info.crtcs[1]->base.enabled) |
620 | if (rdev->mode_info.crtcs[1]->base.enabled) |
621 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
621 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
622 | 622 | ||
623 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
623 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
624 | 624 | ||
625 | if (rdev->disp_priority == 2) { |
625 | if (rdev->disp_priority == 2) { |
626 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
626 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
627 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
627 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
628 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
628 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
629 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
629 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
630 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
630 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
631 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
631 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
632 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
632 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
633 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
633 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
634 | } |
634 | } |
635 | } |
635 | } |
636 | 636 | ||
637 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
637 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
638 | { |
638 | { |
639 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
639 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
640 | S_000070_MC_IND_CITF_ARB0(1)); |
640 | S_000070_MC_IND_CITF_ARB0(1)); |
641 | return RREG32(R_000074_MC_IND_DATA); |
641 | return RREG32(R_000074_MC_IND_DATA); |
642 | } |
642 | } |
643 | 643 | ||
644 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
644 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
645 | { |
645 | { |
646 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
646 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
647 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
647 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
648 | WREG32(R_000074_MC_IND_DATA, v); |
648 | WREG32(R_000074_MC_IND_DATA, v); |
649 | } |
649 | } |
650 | 650 | ||
651 | static void rs600_debugfs(struct radeon_device *rdev) |
651 | static void rs600_debugfs(struct radeon_device *rdev) |
652 | { |
652 | { |
653 | if (r100_debugfs_rbbm_init(rdev)) |
653 | if (r100_debugfs_rbbm_init(rdev)) |
654 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
654 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
655 | } |
655 | } |
656 | 656 | ||
657 | void rs600_set_safe_registers(struct radeon_device *rdev) |
657 | void rs600_set_safe_registers(struct radeon_device *rdev) |
658 | { |
658 | { |
659 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
659 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
660 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
660 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
661 | } |
661 | } |
662 | 662 | ||
663 | static void rs600_mc_program(struct radeon_device *rdev) |
663 | static void rs600_mc_program(struct radeon_device *rdev) |
664 | { |
664 | { |
665 | struct rv515_mc_save save; |
665 | struct rv515_mc_save save; |
666 | 666 | ||
667 | /* Stops all mc clients */ |
667 | /* Stops all mc clients */ |
668 | rv515_mc_stop(rdev, &save); |
668 | rv515_mc_stop(rdev, &save); |
669 | 669 | ||
670 | /* Wait for mc idle */ |
670 | /* Wait for mc idle */ |
671 | if (rs600_mc_wait_for_idle(rdev)) |
671 | if (rs600_mc_wait_for_idle(rdev)) |
672 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
672 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
673 | 673 | ||
674 | /* FIXME: What does AGP means for such chipset ? */ |
674 | /* FIXME: What does AGP means for such chipset ? */ |
675 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
675 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
676 | WREG32_MC(R_000006_AGP_BASE, 0); |
676 | WREG32_MC(R_000006_AGP_BASE, 0); |
677 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
677 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
678 | /* Program MC */ |
678 | /* Program MC */ |
679 | WREG32_MC(R_000004_MC_FB_LOCATION, |
679 | WREG32_MC(R_000004_MC_FB_LOCATION, |
680 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
680 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
681 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
681 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
682 | WREG32(R_000134_HDP_FB_LOCATION, |
682 | WREG32(R_000134_HDP_FB_LOCATION, |
683 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
683 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
684 | 684 | ||
685 | rv515_mc_resume(rdev, &save); |
685 | rv515_mc_resume(rdev, &save); |
686 | } |
686 | } |
687 | 687 | ||
688 | static int rs600_startup(struct radeon_device *rdev) |
688 | static int rs600_startup(struct radeon_device *rdev) |
689 | { |
689 | { |
690 | int r; |
690 | int r; |
691 | 691 | ||
692 | rs600_mc_program(rdev); |
692 | rs600_mc_program(rdev); |
693 | /* Resume clock */ |
693 | /* Resume clock */ |
694 | rv515_clock_startup(rdev); |
694 | rv515_clock_startup(rdev); |
695 | /* Initialize GPU configuration (# pipes, ...) */ |
695 | /* Initialize GPU configuration (# pipes, ...) */ |
696 | rs600_gpu_init(rdev); |
696 | rs600_gpu_init(rdev); |
697 | /* Initialize GART (initialize after TTM so we can allocate |
697 | /* Initialize GART (initialize after TTM so we can allocate |
698 | * memory through TTM but finalize after TTM) */ |
698 | * memory through TTM but finalize after TTM) */ |
699 | r = rs600_gart_enable(rdev); |
699 | r = rs600_gart_enable(rdev); |
700 | if (r) |
700 | if (r) |
701 | return r; |
701 | return r; |
702 | 702 | ||
703 | /* allocate wb buffer */ |
703 | /* allocate wb buffer */ |
704 | r = radeon_wb_init(rdev); |
704 | r = radeon_wb_init(rdev); |
705 | if (r) |
705 | if (r) |
706 | return r; |
706 | return r; |
- | 707 | ||
- | 708 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
|
- | 709 | if (r) { |
|
- | 710 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
|
- | 711 | return r; |
|
- | 712 | } |
|
707 | 713 | ||
708 | /* Enable IRQ */ |
714 | /* Enable IRQ */ |
709 | rs600_irq_set(rdev); |
715 | rs600_irq_set(rdev); |
710 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
716 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
711 | /* 1M ring buffer */ |
717 | /* 1M ring buffer */ |
712 | r = r100_cp_init(rdev, 1024 * 1024); |
718 | r = r100_cp_init(rdev, 1024 * 1024); |
713 | if (r) { |
719 | if (r) { |
714 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
720 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
715 | return r; |
721 | return r; |
716 | } |
722 | } |
717 | 723 | ||
718 | r = radeon_ib_pool_init(rdev); |
724 | r = radeon_ib_pool_init(rdev); |
719 | if (r) { |
725 | if (r) { |
720 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
726 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
721 | return r; |
727 | return r; |
722 | } |
728 | } |
723 | 729 | ||
724 | 730 | ||
725 | return 0; |
731 | return 0; |
726 | } |
732 | } |
727 | 733 | ||
728 | 734 | ||
729 | 735 | ||
730 | int rs600_init(struct radeon_device *rdev) |
736 | int rs600_init(struct radeon_device *rdev) |
731 | { |
737 | { |
732 | int r; |
738 | int r; |
733 | 739 | ||
734 | /* Disable VGA */ |
740 | /* Disable VGA */ |
735 | rv515_vga_render_disable(rdev); |
741 | rv515_vga_render_disable(rdev); |
736 | /* Initialize scratch registers */ |
742 | /* Initialize scratch registers */ |
737 | radeon_scratch_init(rdev); |
743 | radeon_scratch_init(rdev); |
738 | /* Initialize surface registers */ |
744 | /* Initialize surface registers */ |
739 | radeon_surface_init(rdev); |
745 | radeon_surface_init(rdev); |
740 | /* restore some register to sane defaults */ |
746 | /* restore some register to sane defaults */ |
741 | r100_restore_sanity(rdev); |
747 | r100_restore_sanity(rdev); |
742 | /* BIOS */ |
748 | /* BIOS */ |
743 | if (!radeon_get_bios(rdev)) { |
749 | if (!radeon_get_bios(rdev)) { |
744 | if (ASIC_IS_AVIVO(rdev)) |
750 | if (ASIC_IS_AVIVO(rdev)) |
745 | return -EINVAL; |
751 | return -EINVAL; |
746 | } |
752 | } |
747 | if (rdev->is_atom_bios) { |
753 | if (rdev->is_atom_bios) { |
748 | r = radeon_atombios_init(rdev); |
754 | r = radeon_atombios_init(rdev); |
749 | if (r) |
755 | if (r) |
750 | return r; |
756 | return r; |
751 | } else { |
757 | } else { |
752 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
758 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
753 | return -EINVAL; |
759 | return -EINVAL; |
754 | } |
760 | } |
755 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
761 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
756 | if (radeon_asic_reset(rdev)) { |
762 | if (radeon_asic_reset(rdev)) { |
757 | dev_warn(rdev->dev, |
763 | dev_warn(rdev->dev, |
758 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
764 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
759 | RREG32(R_000E40_RBBM_STATUS), |
765 | RREG32(R_000E40_RBBM_STATUS), |
760 | RREG32(R_0007C0_CP_STAT)); |
766 | RREG32(R_0007C0_CP_STAT)); |
761 | } |
767 | } |
762 | /* check if cards are posted or not */ |
768 | /* check if cards are posted or not */ |
763 | if (radeon_boot_test_post_card(rdev) == false) |
769 | if (radeon_boot_test_post_card(rdev) == false) |
764 | return -EINVAL; |
770 | return -EINVAL; |
765 | 771 | ||
766 | /* Initialize clocks */ |
772 | /* Initialize clocks */ |
767 | radeon_get_clock_info(rdev->ddev); |
773 | radeon_get_clock_info(rdev->ddev); |
768 | /* initialize memory controller */ |
774 | /* initialize memory controller */ |
769 | rs600_mc_init(rdev); |
775 | rs600_mc_init(rdev); |
770 | rs600_debugfs(rdev); |
776 | rs600_debugfs(rdev); |
771 | /* Fence driver */ |
777 | /* Fence driver */ |
772 | r = radeon_fence_driver_init(rdev); |
778 | r = radeon_fence_driver_init(rdev); |
773 | if (r) |
779 | if (r) |
774 | return r; |
780 | return r; |
775 | r = radeon_irq_kms_init(rdev); |
781 | r = radeon_irq_kms_init(rdev); |
776 | if (r) |
782 | if (r) |
777 | return r; |
783 | return r; |
778 | /* Memory manager */ |
784 | /* Memory manager */ |
779 | r = radeon_bo_init(rdev); |
785 | r = radeon_bo_init(rdev); |
780 | if (r) |
786 | if (r) |
781 | return r; |
787 | return r; |
782 | r = rs600_gart_init(rdev); |
788 | r = rs600_gart_init(rdev); |
783 | if (r) |
789 | if (r) |
784 | return r; |
790 | return r; |
785 | rs600_set_safe_registers(rdev); |
791 | rs600_set_safe_registers(rdev); |
786 | 792 | ||
787 | rdev->accel_working = true; |
793 | rdev->accel_working = true; |
788 | r = rs600_startup(rdev); |
794 | r = rs600_startup(rdev); |
789 | if (r) { |
795 | if (r) { |
790 | /* Somethings want wront with the accel init stop accel */ |
796 | /* Somethings want wront with the accel init stop accel */ |
791 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
797 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
792 | // r100_cp_fini(rdev); |
798 | // r100_cp_fini(rdev); |
793 | // r100_wb_fini(rdev); |
799 | // r100_wb_fini(rdev); |
794 | // r100_ib_fini(rdev); |
800 | // r100_ib_fini(rdev); |
795 | rs600_gart_fini(rdev); |
801 | rs600_gart_fini(rdev); |
796 | // radeon_irq_kms_fini(rdev); |
802 | // radeon_irq_kms_fini(rdev); |
797 | rdev->accel_working = false; |
803 | rdev->accel_working = false; |
798 | } |
804 | } |
799 | return 0; |
805 | return 0; |
800 | }><>>>><>><>><>><>><>>>><>><>>> |
806 | }><>>>><>><>><>><>><>>>><>><>>> |