Rev 1268 | Rev 1403 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1268 | Rev 1321 | ||
|---|---|---|---|
| Line 43... | Line 43... | ||
| 43 | #include "rs600_reg_safe.h" |
43 | #include "rs600_reg_safe.h" |
| Line 44... | Line 44... | ||
| 44 | 44 | ||
| 45 | void rs600_gpu_init(struct radeon_device *rdev); |
45 | void rs600_gpu_init(struct radeon_device *rdev); |
| Line -... | Line 46... | ||
| - | 46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
|
| - | 47 | ||
| - | 48 | int rs600_mc_init(struct radeon_device *rdev) |
|
| - | 49 | { |
|
| - | 50 | /* read back the MC value from the hw */ |
|
| - | 51 | int r; |
|
| - | 52 | u32 tmp; |
|
| - | 53 | ||
| - | 54 | /* Setup GPU memory space */ |
|
| - | 55 | tmp = RREG32_MC(R_000004_MC_FB_LOCATION); |
|
| - | 56 | rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16; |
|
| - | 57 | rdev->mc.gtt_location = 0xffffffffUL; |
|
| - | 58 | r = radeon_mc_setup(rdev); |
|
| - | 59 | if (r) |
|
| - | 60 | return r; |
|
| - | 61 | return 0; |
|
| - | 62 | } |
|
| - | 63 | ||
| - | 64 | /* hpd for digital panel detect/disconnect */ |
|
| - | 65 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
|
| - | 66 | { |
|
| - | 67 | u32 tmp; |
|
| - | 68 | bool connected = false; |
|
| - | 69 | ||
| - | 70 | switch (hpd) { |
|
| - | 71 | case RADEON_HPD_1: |
|
| - | 72 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
|
| - | 73 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
|
| - | 74 | connected = true; |
|
| - | 75 | break; |
|
| - | 76 | case RADEON_HPD_2: |
|
| - | 77 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
|
| - | 78 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
|
| - | 79 | connected = true; |
|
| - | 80 | break; |
|
| - | 81 | default: |
|
| - | 82 | break; |
|
| - | 83 | } |
|
| - | 84 | return connected; |
|
| - | 85 | } |
|
| - | 86 | ||
| - | 87 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
|
| - | 88 | enum radeon_hpd_id hpd) |
|
| - | 89 | { |
|
| - | 90 | u32 tmp; |
|
| - | 91 | bool connected = rs600_hpd_sense(rdev, hpd); |
|
| - | 92 | ||
| - | 93 | switch (hpd) { |
|
| - | 94 | case RADEON_HPD_1: |
|
| - | 95 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
|
| - | 96 | if (connected) |
|
| - | 97 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
|
| - | 98 | else |
|
| - | 99 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
|
| - | 100 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
|
| - | 101 | break; |
|
| - | 102 | case RADEON_HPD_2: |
|
| - | 103 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
|
| - | 104 | if (connected) |
|
| - | 105 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
|
| - | 106 | else |
|
| - | 107 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
|
| - | 108 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
|
| - | 109 | break; |
|
| - | 110 | default: |
|
| - | 111 | break; |
|
| - | 112 | } |
|
| - | 113 | } |
|
| - | 114 | ||
| - | 115 | void rs600_hpd_init(struct radeon_device *rdev) |
|
| - | 116 | { |
|
| - | 117 | struct drm_device *dev = rdev->ddev; |
|
| - | 118 | struct drm_connector *connector; |
|
| - | 119 | ||
| - | 120 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
| - | 121 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| - | 122 | switch (radeon_connector->hpd.hpd) { |
|
| - | 123 | case RADEON_HPD_1: |
|
| - | 124 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
|
| - | 125 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
|
| - | 126 | rdev->irq.hpd[0] = true; |
|
| - | 127 | break; |
|
| - | 128 | case RADEON_HPD_2: |
|
| - | 129 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
|
| - | 130 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
|
| - | 131 | rdev->irq.hpd[1] = true; |
|
| - | 132 | break; |
|
| - | 133 | default: |
|
| - | 134 | break; |
|
| - | 135 | } |
|
| - | 136 | } |
|
| - | 137 | rs600_irq_set(rdev); |
|
| - | 138 | } |
|
| - | 139 | ||
| - | 140 | void rs600_hpd_fini(struct radeon_device *rdev) |
|
| - | 141 | { |
|
| - | 142 | struct drm_device *dev = rdev->ddev; |
|
| - | 143 | struct drm_connector *connector; |
|
| - | 144 | ||
| - | 145 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
| - | 146 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| - | 147 | switch (radeon_connector->hpd.hpd) { |
|
| - | 148 | case RADEON_HPD_1: |
|
| - | 149 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
|
| - | 150 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
|
| - | 151 | rdev->irq.hpd[0] = false; |
|
| - | 152 | break; |
|
| - | 153 | case RADEON_HPD_2: |
|
| - | 154 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
|
| - | 155 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
|
| - | 156 | rdev->irq.hpd[1] = false; |
|
| - | 157 | break; |
|
| - | 158 | default: |
|
| - | 159 | break; |
|
| - | 160 | } |
|
| - | 161 | } |
|
| 46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
162 | } |
| 47 | 163 | ||
| 48 | /* |
164 | /* |
| 49 | * GART. |
165 | * GART. |
| 50 | */ |
166 | */ |
| Line 100... | Line 216... | ||
| 100 | WREG32(R_00004C_BUS_CNTL, tmp); |
216 | WREG32(R_00004C_BUS_CNTL, tmp); |
| 101 | /* FIXME: setup default page */ |
217 | /* FIXME: setup default page */ |
| 102 | WREG32_MC(R_000100_MC_PT0_CNTL, |
218 | WREG32_MC(R_000100_MC_PT0_CNTL, |
| 103 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
219 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
| 104 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
220 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
| - | 221 | ||
| 105 | for (i = 0; i < 19; i++) { |
222 | for (i = 0; i < 19; i++) { |
| 106 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
223 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
| 107 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
224 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
| 108 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
225 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
| 109 | V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) | |
226 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
| 110 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
227 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
| 111 | V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) | |
228 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
| 112 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) | |
229 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
| 113 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
230 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
| 114 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1)); |
231 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
| 115 | } |
232 | } |
| 116 | - | ||
| 117 | /* System context map to GART space */ |
- | |
| 118 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start); |
- | |
| 119 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end); |
- | |
| 120 | - | ||
| 121 | /* enable first context */ |
233 | /* enable first context */ |
| 122 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
- | |
| 123 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
- | |
| 124 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
234 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
| 125 | S_000102_ENABLE_PAGE_TABLE(1) | |
235 | S_000102_ENABLE_PAGE_TABLE(1) | |
| 126 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
236 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
| - | 237 | ||
| 127 | /* disable all other contexts */ |
238 | /* disable all other contexts */ |
| 128 | for (i = 1; i < 8; i++) { |
239 | for (i = 1; i < 8; i++) |
| 129 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
240 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
| 130 | } |
- | |
| Line 131... | Line 241... | ||
| 131 | 241 | ||
| 132 | /* setup the page table */ |
242 | /* setup the page table */ |
| 133 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
243 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
| - | 244 | rdev->gart.table_addr); |
|
| - | 245 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
|
| 134 | rdev->gart.table_addr); |
246 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
| Line -... | Line 247... | ||
| - | 247 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
|
| - | 248 | ||
| - | 249 | /* System context maps to VRAM space */ |
|
| - | 250 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
|
| 135 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
251 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
| 136 | 252 | ||
| 137 | /* enable page tables */ |
253 | /* enable page tables */ |
| 138 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
254 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| 139 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
255 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
| Line 144... | Line 260... | ||
| 144 | return 0; |
260 | return 0; |
| 145 | } |
261 | } |
| Line 146... | Line 262... | ||
| 146 | 262 | ||
| 147 | void rs600_gart_disable(struct radeon_device *rdev) |
263 | void rs600_gart_disable(struct radeon_device *rdev) |
| 148 | { |
264 | { |
| - | 265 | u32 tmp; |
|
| Line 149... | Line 266... | ||
| 149 | uint32_t tmp; |
266 | int r; |
| 150 | 267 | ||
| 151 | /* FIXME: disable out of gart access */ |
268 | /* FIXME: disable out of gart access */ |
| 152 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
269 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
| Line 183... | Line 300... | ||
| 183 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
300 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
| 184 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
301 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
| 185 | return 0; |
302 | return 0; |
| 186 | } |
303 | } |
| Line -... | Line 304... | ||
| - | 304 | ||
| - | 305 | int rs600_irq_set(struct radeon_device *rdev) |
|
| - | 306 | { |
|
| - | 307 | uint32_t tmp = 0; |
|
| - | 308 | uint32_t mode_int = 0; |
|
| - | 309 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
|
| - | 310 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
|
| - | 311 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
|
| 187 | 312 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
|
| - | 313 | ||
| - | 314 | if (rdev->irq.sw_int) { |
|
| - | 315 | tmp |= S_000040_SW_INT_EN(1); |
|
| - | 316 | } |
|
| - | 317 | if (rdev->irq.crtc_vblank_int[0]) { |
|
| - | 318 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
|
| - | 319 | } |
|
| - | 320 | if (rdev->irq.crtc_vblank_int[1]) { |
|
| - | 321 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
|
| - | 322 | } |
|
| - | 323 | if (rdev->irq.hpd[0]) { |
|
| - | 324 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
|
| - | 325 | } |
|
| - | 326 | if (rdev->irq.hpd[1]) { |
|
| - | 327 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
|
| - | 328 | } |
|
| - | 329 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
|
| - | 330 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
|
| - | 331 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
|
| - | 332 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
|
| - | 333 | return 0; |
|
| Line 188... | Line 334... | ||
| 188 | 334 | } |
|
| 189 | 335 | ||
| 190 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) |
336 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) |
| 191 | { |
337 | { |
| - | 338 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
|
| Line 192... | Line 339... | ||
| 192 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
339 | uint32_t irq_mask = ~C_000044_SW_INT; |
| 193 | uint32_t irq_mask = ~C_000044_SW_INT; |
340 | u32 tmp; |
| 194 | 341 | ||
| 195 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
342 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
| Line 200... | Line 347... | ||
| 200 | } |
347 | } |
| 201 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
348 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
| 202 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
349 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
| 203 | S_006D34_D2MODE_VBLANK_ACK(1)); |
350 | S_006D34_D2MODE_VBLANK_ACK(1)); |
| 204 | } |
351 | } |
| - | 352 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) { |
|
| - | 353 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
|
| - | 354 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
|
| - | 355 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
|
| - | 356 | } |
|
| - | 357 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) { |
|
| - | 358 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
|
| - | 359 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
|
| - | 360 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
|
| - | 361 | } |
|
| 205 | } else { |
362 | } else { |
| 206 | *r500_disp_int = 0; |
363 | *r500_disp_int = 0; |
| 207 | } |
364 | } |
| Line 208... | Line 365... | ||
| 208 | 365 | ||
| Line 244... | Line 401... | ||
| 244 | return -1; |
401 | return -1; |
| 245 | } |
402 | } |
| Line 246... | Line 403... | ||
| 246 | 403 | ||
| 247 | void rs600_gpu_init(struct radeon_device *rdev) |
404 | void rs600_gpu_init(struct radeon_device *rdev) |
| 248 | { |
- | |
| 249 | /* FIXME: HDP same place on rs600 ? */ |
405 | { |
| 250 | r100_hdp_reset(rdev); |
- | |
| 251 | /* FIXME: is this correct ? */ |
406 | r100_hdp_reset(rdev); |
| 252 | r420_pipes_init(rdev); |
407 | r420_pipes_init(rdev); |
| 253 | /* Wait for mc idle */ |
408 | /* Wait for mc idle */ |
| 254 | if (rs600_mc_wait_for_idle(rdev)) |
409 | if (rs600_mc_wait_for_idle(rdev)) |
| 255 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
410 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| Line 256... | Line 411... | ||
| 256 | } |
411 | } |
| 257 | 412 | ||
| 258 | void rs600_vram_info(struct radeon_device *rdev) |
- | |
| 259 | { |
413 | void rs600_vram_info(struct radeon_device *rdev) |
| 260 | /* FIXME: to do or is these values sane ? */ |
414 | { |
| - | 415 | rdev->mc.vram_is_ddr = true; |
|
| - | 416 | rdev->mc.vram_width = 128; |
|
| - | 417 | ||
| - | 418 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
|
| - | 419 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
|
| - | 420 | ||
| - | 421 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
|
| - | 422 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
|
| - | 423 | ||
| - | 424 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) |
|
| - | 425 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
|
| - | 426 | ||
| 261 | rdev->mc.vram_is_ddr = true; |
427 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
| Line 262... | Line 428... | ||
| 262 | rdev->mc.vram_width = 128; |
428 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
| 263 | } |
429 | } |
| 264 | 430 | ||
| Line 331... | Line 497... | ||
| 331 | * memory through TTM but finalize after TTM) */ |
497 | * memory through TTM but finalize after TTM) */ |
| 332 | r = rs600_gart_enable(rdev); |
498 | r = rs600_gart_enable(rdev); |
| 333 | if (r) |
499 | if (r) |
| 334 | return r; |
500 | return r; |
| 335 | /* Enable IRQ */ |
501 | /* Enable IRQ */ |
| 336 | // rdev->irq.sw_int = true; |
- | |
| 337 | // rs600_irq_set(rdev); |
502 | // rs600_irq_set(rdev); |
| 338 | /* 1M ring buffer */ |
503 | /* 1M ring buffer */ |
| 339 | // r = r100_cp_init(rdev, 1024 * 1024); |
504 | // r = r100_cp_init(rdev, 1024 * 1024); |
| 340 | // if (r) { |
505 | // if (r) { |
| 341 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
506 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| Line 383... | Line 548... | ||
| 383 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
548 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 384 | RREG32(R_000E40_RBBM_STATUS), |
549 | RREG32(R_000E40_RBBM_STATUS), |
| 385 | RREG32(R_0007C0_CP_STAT)); |
550 | RREG32(R_0007C0_CP_STAT)); |
| 386 | } |
551 | } |
| 387 | /* check if cards are posted or not */ |
552 | /* check if cards are posted or not */ |
| 388 | if (!radeon_card_posted(rdev) && rdev->bios) { |
553 | if (radeon_boot_test_post_card(rdev) == false) |
| 389 | DRM_INFO("GPU not posted. posting now...\n"); |
- | |
| 390 | atom_asic_init(rdev->mode_info.atom_context); |
554 | return -EINVAL; |
| 391 | } |
555 | |
| 392 | /* Initialize clocks */ |
556 | /* Initialize clocks */ |
| 393 | radeon_get_clock_info(rdev->ddev); |
557 | radeon_get_clock_info(rdev->ddev); |
| 394 | /* Initialize power management */ |
558 | /* Initialize power management */ |
| 395 | radeon_pm_init(rdev); |
559 | radeon_pm_init(rdev); |
| 396 | /* Get vram informations */ |
560 | /* Get vram informations */ |
| 397 | rs600_vram_info(rdev); |
561 | rs600_vram_info(rdev); |
| 398 | /* Initialize memory controller (also test AGP) */ |
562 | /* Initialize memory controller (also test AGP) */ |
| 399 | r = r420_mc_init(rdev); |
563 | r = rs600_mc_init(rdev); |
| 400 | if (r) |
564 | if (r) |
| 401 | return r; |
565 | return r; |
| 402 | rs600_debugfs(rdev); |
566 | rs600_debugfs(rdev); |
| 403 | /* Fence driver */ |
567 | /* Fence driver */ |
| 404 | // r = radeon_fence_driver_init(rdev); |
568 | // r = radeon_fence_driver_init(rdev); |
| Line 406... | Line 570... | ||
| 406 | // return r; |
570 | // return r; |
| 407 | // r = radeon_irq_kms_init(rdev); |
571 | // r = radeon_irq_kms_init(rdev); |
| 408 | // if (r) |
572 | // if (r) |
| 409 | // return r; |
573 | // return r; |
| 410 | /* Memory manager */ |
574 | /* Memory manager */ |
| 411 | r = radeon_object_init(rdev); |
575 | r = radeon_bo_init(rdev); |
| 412 | if (r) |
576 | if (r) |
| 413 | return r; |
577 | return r; |
| 414 | r = rs600_gart_init(rdev); |
578 | r = rs600_gart_init(rdev); |
| 415 | if (r) |
579 | if (r) |
| 416 | return r; |
580 | return r; |