WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/rs400.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include 
#include 
#include 
#include "radeon.h"
#include "radeon_asic.h"
#include "rs400d.h"
 
/* This files gather functions specifics to : rs400,rs480 */
static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
 
void rs400_gart_adjust_size(struct radeon_device *rdev)
{
	/* Check gart size */
	switch (rdev->mc.gtt_size/(1024*1024)) {
	case 32:
	case 64:
	case 128:
	case 256:
	case 512:
	case 1024:
	case 2048:
		break;
	default:
		DRM_ERROR("Unable to use IGP GART size %uM\n",
			  (unsigned)(rdev->mc.gtt_size >> 20));
		DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
		DRM_ERROR("Forcing to 32M GART size\n");
		rdev->mc.gtt_size = 32 * 1024 * 1024;
		return;
	}
}
 
void rs400_gart_tlb_flush(struct radeon_device *rdev)
{
	uint32_t tmp;
	unsigned int timeout = rdev->usec_timeout;
 
	WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
	do {
		tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
		if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
			break;
		DRM_UDELAY(1);
		timeout--;
	} while (timeout > 0);
	WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
}
 
int rs400_gart_init(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->gart.ptr) {
		WARN(1, "RS400 GART already initialized\n");
		return 0;
	}
	/* Check gart size */
	switch(rdev->mc.gtt_size / (1024 * 1024)) {
	case 32:
	case 64:
	case 128:
	case 256:
	case 512:
	case 1024:
	case 2048:
		break;
	default:
		return -EINVAL;
	}
	/* Initialize common gart structure */
	r = radeon_gart_init(rdev);
	if (r)
		return r;
	if (rs400_debugfs_pcie_gart_info_init(rdev))
		DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
	return radeon_gart_table_ram_alloc(rdev);
}
 
int rs400_gart_enable(struct radeon_device *rdev)
{
	uint32_t size_reg;
	uint32_t tmp;
 
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
	/* Check gart size */
	switch(rdev->mc.gtt_size / (1024 * 1024)) {
	case 32:
		size_reg = RS480_VA_SIZE_32MB;
		break;
	case 64:
		size_reg = RS480_VA_SIZE_64MB;
		break;
	case 128:
		size_reg = RS480_VA_SIZE_128MB;
		break;
	case 256:
		size_reg = RS480_VA_SIZE_256MB;
		break;
	case 512:
		size_reg = RS480_VA_SIZE_512MB;
		break;
	case 1024:
		size_reg = RS480_VA_SIZE_1GB;
		break;
	case 2048:
		size_reg = RS480_VA_SIZE_2GB;
		break;
	default:
		return -EINVAL;
	}
	/* It should be fine to program it to max value */
	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
		WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
		WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
	} else {
		WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
		WREG32(RS480_AGP_BASE_2, 0);
	}
	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
		WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
		tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
		WREG32(RADEON_BUS_CNTL, tmp);
	} else {
		WREG32(RADEON_MC_AGP_LOCATION, tmp);
		tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		WREG32(RADEON_BUS_CNTL, tmp);
	}
	/* Table should be in 32bits address space so ignore bits above. */
	tmp = (u32)rdev->gart.table_addr & 0xfffff000;
	tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
 
	WREG32_MC(RS480_GART_BASE, tmp);
	/* TODO: more tweaking here */
	WREG32_MC(RS480_GART_FEATURE_ID,
		  (RS480_TLB_ENABLE |
		   RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
	/* Disable snooping */
	WREG32_MC(RS480_AGP_MODE_CNTL,
		  (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
	/* Disable AGP mode */
	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
	 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
		tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
	} else {
		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
		tmp |= RS480_GART_INDEX_REG_EN;
		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
	}
	/* Enable gart */
	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
	rs400_gart_tlb_flush(rdev);
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
		 (unsigned)(rdev->mc.gtt_size >> 20),
		 (unsigned long long)rdev->gart.table_addr);
	rdev->gart.ready = true;
	return 0;
}
 
void rs400_gart_disable(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
}
 
void rs400_gart_fini(struct radeon_device *rdev)
{
	radeon_gart_fini(rdev);
	rs400_gart_disable(rdev);
	radeon_gart_table_ram_free(rdev);
}
 
#define RS400_PTE_UNSNOOPED (1 << 0)
#define RS400_PTE_WRITEABLE (1 << 2)
#define RS400_PTE_READABLE  (1 << 3)
 
 
uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
{
 
	uint32_t entry;
 
	entry = (lower_32_bits(addr) & PAGE_MASK) |
		((upper_32_bits(addr) & 0xff) << 4);
	if (flags & RADEON_GART_PAGE_READ)
		entry |= RS400_PTE_READABLE;
	if (flags & RADEON_GART_PAGE_WRITE)
		entry |= RS400_PTE_WRITEABLE;
	if (!(flags & RADEON_GART_PAGE_SNOOP))
		entry |= RS400_PTE_UNSNOOPED;
	return entry;
}
 
void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
			 uint64_t entry)
{
	u32 *gtt = rdev->gart.ptr;
	gtt[i] = cpu_to_le32(lower_32_bits(entry));
}
 
int rs400_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	uint32_t tmp;
 
	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(RADEON_MC_STATUS);
		if (tmp & RADEON_MC_IDLE) {
			return 0;
		}
		DRM_UDELAY(1);
	}
	return -1;
}
 
static void rs400_gpu_init(struct radeon_device *rdev)
{
	/* FIXME: is this correct ? */
	r420_pipes_init(rdev);
	if (rs400_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "rs400: Failed to wait MC idle while "
		       "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
	}
}
 
static void rs400_mc_init(struct radeon_device *rdev)
{
	u64 base;
 
	rs400_gart_adjust_size(rdev);
	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
	/* DDR for all card after R300 & IGP */
	rdev->mc.vram_is_ddr = true;
	rdev->mc.vram_width = 128;
	r100_vram_init_sizes(rdev);
	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
	radeon_vram_location(rdev, &rdev->mc, base);
	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
	radeon_gtt_location(rdev, &rdev->mc);
	radeon_update_bandwidth_info(rdev);
}
 
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	unsigned long flags;
	uint32_t r;
 
	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
	r = RREG32(RS480_NB_MC_DATA);
	WREG32(RS480_NB_MC_INDEX, 0xff);
	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
	return r;
}
 
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	unsigned long flags;
 
	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
	WREG32(RS480_NB_MC_DATA, (v));
	WREG32(RS480_NB_MC_INDEX, 0xff);
	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
}
 
#if defined(CONFIG_DEBUG_FS)
static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;
 
	tmp = RREG32(RADEON_HOST_PATH_CNTL);
	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
	tmp = RREG32(RADEON_BUS_CNTL);
	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
		seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
		seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
		tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
		seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
		tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
		seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
		tmp = RREG32(RS690_HDP_FB_LOCATION);
		seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
	} else {
		tmp = RREG32(RADEON_AGP_BASE);
		seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		tmp = RREG32(RS480_AGP_BASE_2);
		seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
		tmp = RREG32(RADEON_MC_AGP_LOCATION);
		seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
	}
	tmp = RREG32_MC(RS480_GART_BASE);
	seq_printf(m, "GART_BASE 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_GART_FEATURE_ID);
	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
	tmp = RREG32_MC(0x5F);
	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
	tmp = RREG32_MC(0x3B);
	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
	tmp = RREG32_MC(0x3C);
	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
	tmp = RREG32_MC(0x30);
	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
	tmp = RREG32_MC(0x31);
	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
	tmp = RREG32_MC(0x32);
	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
	tmp = RREG32_MC(0x33);
	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
	tmp = RREG32_MC(0x34);
	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
	tmp = RREG32_MC(0x35);
	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
	tmp = RREG32_MC(0x36);
	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
	tmp = RREG32_MC(0x37);
	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
	return 0;
}
 
static struct drm_info_list rs400_gart_info_list[] = {
	{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
};
#endif
 
static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
#else
	return 0;
#endif
}
 
static void rs400_mc_program(struct radeon_device *rdev)
{
	struct r100_mc_save save;
 
	/* Stops all mc clients */
	r100_mc_stop(rdev, &save);
 
	/* Wait for mc idle */
	if (rs400_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
	WREG32(R_000148_MC_FB_LOCATION,
		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
 
	r100_mc_resume(rdev, &save);
}
 
static int rs400_startup(struct radeon_device *rdev)
{
	int r;
 
	r100_set_common_regs(rdev);
 
	rs400_mc_program(rdev);
	/* Resume clock */
	r300_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	rs400_gpu_init(rdev);
	r100_enable_bm(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	r = rs400_gart_enable(rdev);
	if (r)
		return r;
 
	/* allocate wb buffer */
	r = radeon_wb_init(rdev);
	if (r)
		return r;
 
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		return r;
	}
 
	/* Enable IRQ */
	if (!rdev->irq.installed) {
		r = radeon_irq_kms_init(rdev);
		if (r)
			return r;
	}
 
	r100_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
		return r;
	}
 
	r = radeon_ib_pool_init(rdev);
	if (r) {
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
		return r;
	}
 
	return 0;
}
 
 
 
void rs400_fini(struct radeon_device *rdev)
{
	radeon_pm_fini(rdev);
	r100_cp_fini(rdev);
	radeon_wb_fini(rdev);
	radeon_ib_pool_fini(rdev);
	radeon_gem_fini(rdev);
	rs400_gart_fini(rdev);
	radeon_irq_kms_fini(rdev);
	radeon_fence_driver_fini(rdev);
	radeon_bo_fini(rdev);
	radeon_atombios_fini(rdev);
	kfree(rdev->bios);
	rdev->bios = NULL;
}
 
int rs400_init(struct radeon_device *rdev)
{
	int r;
 
	/* Disable VGA */
	r100_vga_render_disable(rdev);
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* restore some register to sane defaults */
	r100_restore_sanity(rdev);
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		return -EINVAL;
	} else {
		r = radeon_combios_init(rdev);
		if (r)
			return r;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;
 
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* initialize memory controller */
	rs400_mc_init(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	r = rs400_gart_init(rdev);
	if (r)
		return r;
	r300_set_reg_safe(rdev);
 
	/* Initialize power management */
	radeon_pm_init(rdev);
 
	rdev->accel_working = true;
	r = rs400_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		r100_cp_fini(rdev);
		radeon_wb_fini(rdev);
		radeon_ib_pool_fini(rdev);
		rs400_gart_fini(rdev);
		radeon_irq_kms_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}

Rev 5139	Rev 6104
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include	28	#include
29	#include	29	#include
30	#include	30	#include
31	#include "radeon.h"	31	#include "radeon.h"
32	#include "radeon_asic.h"	32	#include "radeon_asic.h"
33	#include "rs400d.h"	33	#include "rs400d.h"
34		34
35	/* This files gather functions specifics to : rs400,rs480 */	35	/* This files gather functions specifics to : rs400,rs480 */
36	static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);	36	static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
37		37
38	void rs400_gart_adjust_size(struct radeon_device *rdev)	38	void rs400_gart_adjust_size(struct radeon_device *rdev)
39	{	39	{
40	/* Check gart size */	40	/* Check gart size */
41	switch (rdev->mc.gtt_size/(1024*1024)) {	41	switch (rdev->mc.gtt_size/(1024*1024)) {
42	case 32:	42	case 32:
43	case 64:	43	case 64:
44	case 128:	44	case 128:
45	case 256:	45	case 256:
46	case 512:	46	case 512:
47	case 1024:	47	case 1024:
48	case 2048:	48	case 2048:
49	break;	49	break;
50	default:	50	default:
51	DRM_ERROR("Unable to use IGP GART size %uM\n",	51	DRM_ERROR("Unable to use IGP GART size %uM\n",
52	(unsigned)(rdev->mc.gtt_size >> 20));	52	(unsigned)(rdev->mc.gtt_size >> 20));
53	DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");	53	DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
54	DRM_ERROR("Forcing to 32M GART size\n");	54	DRM_ERROR("Forcing to 32M GART size\n");
55	rdev->mc.gtt_size = 32 * 1024 * 1024;	55	rdev->mc.gtt_size = 32 * 1024 * 1024;
56	return;	56	return;
57	}	57	}
58	}	58	}
59		59
60	void rs400_gart_tlb_flush(struct radeon_device *rdev)	60	void rs400_gart_tlb_flush(struct radeon_device *rdev)
61	{	61	{
62	uint32_t tmp;	62	uint32_t tmp;
63	unsigned int timeout = rdev->usec_timeout;	63	unsigned int timeout = rdev->usec_timeout;
64		64
65	WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);	65	WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
66	do {	66	do {
67	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);	67	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
68	if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)	68	if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
69	break;	69	break;
70	DRM_UDELAY(1);	70	DRM_UDELAY(1);
71	timeout--;	71	timeout--;
72	} while (timeout > 0);	72	} while (timeout > 0);
73	WREG32_MC(RS480_GART_CACHE_CNTRL, 0);	73	WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
74	}	74	}
75		75
76	int rs400_gart_init(struct radeon_device *rdev)	76	int rs400_gart_init(struct radeon_device *rdev)
77	{	77	{
78	int r;	78	int r;
79		79
80	if (rdev->gart.ptr) {	80	if (rdev->gart.ptr) {
81	WARN(1, "RS400 GART already initialized\n");	81	WARN(1, "RS400 GART already initialized\n");
82	return 0;	82	return 0;
83	}	83	}
84	/* Check gart size */	84	/* Check gart size */
85	switch(rdev->mc.gtt_size / (1024 * 1024)) {	85	switch(rdev->mc.gtt_size / (1024 * 1024)) {
86	case 32:	86	case 32:
87	case 64:	87	case 64:
88	case 128:	88	case 128:
89	case 256:	89	case 256:
90	case 512:	90	case 512:
91	case 1024:	91	case 1024:
92	case 2048:	92	case 2048:
93	break;	93	break;
94	default:	94	default:
95	return -EINVAL;	95	return -EINVAL;
96	}	96	}
97	/* Initialize common gart structure */	97	/* Initialize common gart structure */
98	r = radeon_gart_init(rdev);	98	r = radeon_gart_init(rdev);
99	if (r)	99	if (r)
100	return r;	100	return r;
101	if (rs400_debugfs_pcie_gart_info_init(rdev))	101	if (rs400_debugfs_pcie_gart_info_init(rdev))
102	DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");	102	DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
103	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;	103	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
104	return radeon_gart_table_ram_alloc(rdev);	104	return radeon_gart_table_ram_alloc(rdev);
105	}	105	}
106		106
107	int rs400_gart_enable(struct radeon_device *rdev)	107	int rs400_gart_enable(struct radeon_device *rdev)
108	{	108	{
109	uint32_t size_reg;	109	uint32_t size_reg;
110	uint32_t tmp;	110	uint32_t tmp;
111		111
112	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);	112	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
113	tmp \|= RS690_DIS_OUT_OF_PCI_GART_ACCESS;	113	tmp \|= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
114	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);	114	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
115	/* Check gart size */	115	/* Check gart size */
116	switch(rdev->mc.gtt_size / (1024 * 1024)) {	116	switch(rdev->mc.gtt_size / (1024 * 1024)) {
117	case 32:	117	case 32:
118	size_reg = RS480_VA_SIZE_32MB;	118	size_reg = RS480_VA_SIZE_32MB;
119	break;	119	break;
120	case 64:	120	case 64:
121	size_reg = RS480_VA_SIZE_64MB;	121	size_reg = RS480_VA_SIZE_64MB;
122	break;	122	break;
123	case 128:	123	case 128:
124	size_reg = RS480_VA_SIZE_128MB;	124	size_reg = RS480_VA_SIZE_128MB;
125	break;	125	break;
126	case 256:	126	case 256:
127	size_reg = RS480_VA_SIZE_256MB;	127	size_reg = RS480_VA_SIZE_256MB;
128	break;	128	break;
129	case 512:	129	case 512:
130	size_reg = RS480_VA_SIZE_512MB;	130	size_reg = RS480_VA_SIZE_512MB;
131	break;	131	break;
132	case 1024:	132	case 1024:
133	size_reg = RS480_VA_SIZE_1GB;	133	size_reg = RS480_VA_SIZE_1GB;
134	break;	134	break;
135	case 2048:	135	case 2048:
136	size_reg = RS480_VA_SIZE_2GB;	136	size_reg = RS480_VA_SIZE_2GB;
137	break;	137	break;
138	default:	138	default:
139	return -EINVAL;	139	return -EINVAL;
140	}	140	}
141	/* It should be fine to program it to max value */	141	/* It should be fine to program it to max value */
142	if (rdev->family == CHIP_RS690 \|\| (rdev->family == CHIP_RS740)) {	142	if (rdev->family == CHIP_RS690 \|\| (rdev->family == CHIP_RS740)) {
143	WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);	143	WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
144	WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);	144	WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
145	} else {	145	} else {
146	WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);	146	WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
147	WREG32(RS480_AGP_BASE_2, 0);	147	WREG32(RS480_AGP_BASE_2, 0);
148	}	148	}
149	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);	149	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
150	tmp \|= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);	150	tmp \|= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
151	if ((rdev->family == CHIP_RS690) \|\| (rdev->family == CHIP_RS740)) {	151	if ((rdev->family == CHIP_RS690) \|\| (rdev->family == CHIP_RS740)) {
152	WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);	152	WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
153	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;	153	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
154	WREG32(RADEON_BUS_CNTL, tmp);	154	WREG32(RADEON_BUS_CNTL, tmp);
155	} else {	155	} else {
156	WREG32(RADEON_MC_AGP_LOCATION, tmp);	156	WREG32(RADEON_MC_AGP_LOCATION, tmp);
157	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;	157	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
158	WREG32(RADEON_BUS_CNTL, tmp);	158	WREG32(RADEON_BUS_CNTL, tmp);
159	}	159	}
160	/* Table should be in 32bits address space so ignore bits above. */	160	/* Table should be in 32bits address space so ignore bits above. */
161	tmp = (u32)rdev->gart.table_addr & 0xfffff000;	161	tmp = (u32)rdev->gart.table_addr & 0xfffff000;
162	tmp \|= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;	162	tmp \|= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
163		163
164	WREG32_MC(RS480_GART_BASE, tmp);	164	WREG32_MC(RS480_GART_BASE, tmp);
165	/* TODO: more tweaking here */	165	/* TODO: more tweaking here */
166	WREG32_MC(RS480_GART_FEATURE_ID,	166	WREG32_MC(RS480_GART_FEATURE_ID,
167	(RS480_TLB_ENABLE \|	167	(RS480_TLB_ENABLE \|
168	RS480_GTW_LAC_EN \| RS480_1LEVEL_GART));	168	RS480_GTW_LAC_EN \| RS480_1LEVEL_GART));
169	/* Disable snooping */	169	/* Disable snooping */
170	WREG32_MC(RS480_AGP_MODE_CNTL,	170	WREG32_MC(RS480_AGP_MODE_CNTL,
171	(1 << RS480_REQ_TYPE_SNOOP_SHIFT) \| RS480_REQ_TYPE_SNOOP_DIS);	171	(1 << RS480_REQ_TYPE_SNOOP_SHIFT) \| RS480_REQ_TYPE_SNOOP_DIS);
172	/* Disable AGP mode */	172	/* Disable AGP mode */
173	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,	173	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
174	* AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */	174	* AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
175	if ((rdev->family == CHIP_RS690) \|\| (rdev->family == CHIP_RS740)) {	175	if ((rdev->family == CHIP_RS690) \|\| (rdev->family == CHIP_RS740)) {
176	tmp = RREG32_MC(RS480_MC_MISC_CNTL);	176	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
177	tmp \|= RS480_GART_INDEX_REG_EN \| RS690_BLOCK_GFX_D3_EN;	177	tmp \|= RS480_GART_INDEX_REG_EN \| RS690_BLOCK_GFX_D3_EN;
178	WREG32_MC(RS480_MC_MISC_CNTL, tmp);	178	WREG32_MC(RS480_MC_MISC_CNTL, tmp);
179	} else {	179	} else {
180	tmp = RREG32_MC(RS480_MC_MISC_CNTL);	180	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
181	tmp \|= RS480_GART_INDEX_REG_EN;	181	tmp \|= RS480_GART_INDEX_REG_EN;
182	WREG32_MC(RS480_MC_MISC_CNTL, tmp);	182	WREG32_MC(RS480_MC_MISC_CNTL, tmp);
183	}	183	}
184	/* Enable gart */	184	/* Enable gart */
185	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN \| size_reg));	185	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN \| size_reg));
186	rs400_gart_tlb_flush(rdev);	186	rs400_gart_tlb_flush(rdev);
187	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",	187	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
188	(unsigned)(rdev->mc.gtt_size >> 20),	188	(unsigned)(rdev->mc.gtt_size >> 20),
189	(unsigned long long)rdev->gart.table_addr);	189	(unsigned long long)rdev->gart.table_addr);
190	rdev->gart.ready = true;	190	rdev->gart.ready = true;
191	return 0;	191	return 0;
192	}	192	}
193		193
194	void rs400_gart_disable(struct radeon_device *rdev)	194	void rs400_gart_disable(struct radeon_device *rdev)
195	{	195	{
196	uint32_t tmp;	196	uint32_t tmp;
197		197
198	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);	198	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
199	tmp \|= RS690_DIS_OUT_OF_PCI_GART_ACCESS;	199	tmp \|= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
200	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);	200	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
201	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);	201	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
202	}	202	}
203		203
204	void rs400_gart_fini(struct radeon_device *rdev)	204	void rs400_gart_fini(struct radeon_device *rdev)
205	{	205	{
206	radeon_gart_fini(rdev);	206	radeon_gart_fini(rdev);
207	rs400_gart_disable(rdev);	207	rs400_gart_disable(rdev);
208	radeon_gart_table_ram_free(rdev);	208	radeon_gart_table_ram_free(rdev);
209	}	209	}
210		210
211	#define RS400_PTE_UNSNOOPED (1 << 0)	211	#define RS400_PTE_UNSNOOPED (1 << 0)
212	#define RS400_PTE_WRITEABLE (1 << 2)	212	#define RS400_PTE_WRITEABLE (1 << 2)
213	#define RS400_PTE_READABLE (1 << 3)	213	#define RS400_PTE_READABLE (1 << 3)
214		-
215	void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,	214
216	uint64_t addr, uint32_t flags)	215	uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
217	{	216	{
218	uint32_t entry;	-
219	u32 *gtt = rdev->gart.ptr;	217	uint32_t entry;
220		218
221	entry = (lower_32_bits(addr) & PAGE_MASK) \|	219	entry = (lower_32_bits(addr) & PAGE_MASK) \|
222	((upper_32_bits(addr) & 0xff) << 4);	220	((upper_32_bits(addr) & 0xff) << 4);
223	if (flags & RADEON_GART_PAGE_READ)	221	if (flags & RADEON_GART_PAGE_READ)
224	entry \|= RS400_PTE_READABLE;	222	entry \|= RS400_PTE_READABLE;
225	if (flags & RADEON_GART_PAGE_WRITE)	223	if (flags & RADEON_GART_PAGE_WRITE)
226	entry \|= RS400_PTE_WRITEABLE;	224	entry \|= RS400_PTE_WRITEABLE;
227	if (!(flags & RADEON_GART_PAGE_SNOOP))	225	if (!(flags & RADEON_GART_PAGE_SNOOP))
228	entry \|= RS400_PTE_UNSNOOPED;	226	entry \|= RS400_PTE_UNSNOOPED;
229	entry = cpu_to_le32(entry);	227	return entry;
-		228	}
-		229
-		230	void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
230	gtt[i] = entry;	231	uint64_t entry)
-		232	{
-		233	u32 *gtt = rdev->gart.ptr;
-		234	gtt[i] = cpu_to_le32(lower_32_bits(entry));
231	}	235	}
232		236
233	int rs400_mc_wait_for_idle(struct radeon_device *rdev)	237	int rs400_mc_wait_for_idle(struct radeon_device *rdev)
234	{	238	{
235	unsigned i;	239	unsigned i;
236	uint32_t tmp;	240	uint32_t tmp;
237		241
238	for (i = 0; i < rdev->usec_timeout; i++) {	242	for (i = 0; i < rdev->usec_timeout; i++) {
239	/* read MC_STATUS */	243	/* read MC_STATUS */
240	tmp = RREG32(RADEON_MC_STATUS);	244	tmp = RREG32(RADEON_MC_STATUS);
241	if (tmp & RADEON_MC_IDLE) {	245	if (tmp & RADEON_MC_IDLE) {
242	return 0;	246	return 0;
243	}	247	}
244	DRM_UDELAY(1);	248	DRM_UDELAY(1);
245	}	249	}
246	return -1;	250	return -1;
247	}	251	}
248		252
249	static void rs400_gpu_init(struct radeon_device *rdev)	253	static void rs400_gpu_init(struct radeon_device *rdev)
250	{	254	{
251	/* FIXME: is this correct ? */	255	/* FIXME: is this correct ? */
252	r420_pipes_init(rdev);	256	r420_pipes_init(rdev);
253	if (rs400_mc_wait_for_idle(rdev)) {	257	if (rs400_mc_wait_for_idle(rdev)) {
254	printk(KERN_WARNING "rs400: Failed to wait MC idle while "	258	printk(KERN_WARNING "rs400: Failed to wait MC idle while "
255	"programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));	259	"programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
256	}	260	}
257	}	261	}
258		262
259	static void rs400_mc_init(struct radeon_device *rdev)	263	static void rs400_mc_init(struct radeon_device *rdev)
260	{	264	{
261	u64 base;	265	u64 base;
262		266
263	rs400_gart_adjust_size(rdev);	267	rs400_gart_adjust_size(rdev);
264	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);	268	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
265	/* DDR for all card after R300 & IGP */	269	/* DDR for all card after R300 & IGP */
266	rdev->mc.vram_is_ddr = true;	270	rdev->mc.vram_is_ddr = true;
267	rdev->mc.vram_width = 128;	271	rdev->mc.vram_width = 128;
268	r100_vram_init_sizes(rdev);	272	r100_vram_init_sizes(rdev);
269	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;	273	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
270	radeon_vram_location(rdev, &rdev->mc, base);	274	radeon_vram_location(rdev, &rdev->mc, base);
271	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;	275	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
272	radeon_gtt_location(rdev, &rdev->mc);	276	radeon_gtt_location(rdev, &rdev->mc);
273	radeon_update_bandwidth_info(rdev);	277	radeon_update_bandwidth_info(rdev);
274	}	278	}
275		279
276	uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)	280	uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
277	{	281	{
278	unsigned long flags;	282	unsigned long flags;
279	uint32_t r;	283	uint32_t r;
280		284
281	spin_lock_irqsave(&rdev->mc_idx_lock, flags);	285	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
282	WREG32(RS480_NB_MC_INDEX, reg & 0xff);	286	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
283	r = RREG32(RS480_NB_MC_DATA);	287	r = RREG32(RS480_NB_MC_DATA);
284	WREG32(RS480_NB_MC_INDEX, 0xff);	288	WREG32(RS480_NB_MC_INDEX, 0xff);
285	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);	289	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
286	return r;	290	return r;
287	}	291	}
288		292
289	void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)	293	void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
290	{	294	{
291	unsigned long flags;	295	unsigned long flags;
292		296
293	spin_lock_irqsave(&rdev->mc_idx_lock, flags);	297	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
294	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) \| RS480_NB_MC_IND_WR_EN);	298	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) \| RS480_NB_MC_IND_WR_EN);
295	WREG32(RS480_NB_MC_DATA, (v));	299	WREG32(RS480_NB_MC_DATA, (v));
296	WREG32(RS480_NB_MC_INDEX, 0xff);	300	WREG32(RS480_NB_MC_INDEX, 0xff);
297	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);	301	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
298	}	302	}
299		303
300	#if defined(CONFIG_DEBUG_FS)	304	#if defined(CONFIG_DEBUG_FS)
301	static int rs400_debugfs_gart_info(struct seq_file m, void data)	305	static int rs400_debugfs_gart_info(struct seq_file m, void data)
302	{	306	{
303	struct drm_info_node node = (struct drm_info_node ) m->private;	307	struct drm_info_node node = (struct drm_info_node ) m->private;
304	struct drm_device *dev = node->minor->dev;	308	struct drm_device *dev = node->minor->dev;
305	struct radeon_device *rdev = dev->dev_private;	309	struct radeon_device *rdev = dev->dev_private;
306	uint32_t tmp;	310	uint32_t tmp;
307		311
308	tmp = RREG32(RADEON_HOST_PATH_CNTL);	312	tmp = RREG32(RADEON_HOST_PATH_CNTL);
309	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);	313	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
310	tmp = RREG32(RADEON_BUS_CNTL);	314	tmp = RREG32(RADEON_BUS_CNTL);
311	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);	315	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
312	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);	316	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
313	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);	317	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
314	if (rdev->family == CHIP_RS690 \|\| (rdev->family == CHIP_RS740)) {	318	if (rdev->family == CHIP_RS690 \|\| (rdev->family == CHIP_RS740)) {
315	tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);	319	tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
316	seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);	320	seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
317	tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);	321	tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
318	seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);	322	seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
319	tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);	323	tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
320	seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);	324	seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
321	tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);	325	tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
322	seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);	326	seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
323	tmp = RREG32(RS690_HDP_FB_LOCATION);	327	tmp = RREG32(RS690_HDP_FB_LOCATION);
324	seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);	328	seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
325	} else {	329	} else {
326	tmp = RREG32(RADEON_AGP_BASE);	330	tmp = RREG32(RADEON_AGP_BASE);
327	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);	331	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
328	tmp = RREG32(RS480_AGP_BASE_2);	332	tmp = RREG32(RS480_AGP_BASE_2);
329	seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);	333	seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
330	tmp = RREG32(RADEON_MC_AGP_LOCATION);	334	tmp = RREG32(RADEON_MC_AGP_LOCATION);
331	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);	335	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
332	}	336	}
333	tmp = RREG32_MC(RS480_GART_BASE);	337	tmp = RREG32_MC(RS480_GART_BASE);
334	seq_printf(m, "GART_BASE 0x%08x\n", tmp);	338	seq_printf(m, "GART_BASE 0x%08x\n", tmp);
335	tmp = RREG32_MC(RS480_GART_FEATURE_ID);	339	tmp = RREG32_MC(RS480_GART_FEATURE_ID);
336	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);	340	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
337	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);	341	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
338	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);	342	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
339	tmp = RREG32_MC(RS480_MC_MISC_CNTL);	343	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
340	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);	344	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
341	tmp = RREG32_MC(0x5F);	345	tmp = RREG32_MC(0x5F);
342	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);	346	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
343	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);	347	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
344	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);	348	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
345	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);	349	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
346	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);	350	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
347	tmp = RREG32_MC(0x3B);	351	tmp = RREG32_MC(0x3B);
348	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);	352	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
349	tmp = RREG32_MC(0x3C);	353	tmp = RREG32_MC(0x3C);
350	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);	354	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
351	tmp = RREG32_MC(0x30);	355	tmp = RREG32_MC(0x30);
352	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);	356	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
353	tmp = RREG32_MC(0x31);	357	tmp = RREG32_MC(0x31);
354	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);	358	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
355	tmp = RREG32_MC(0x32);	359	tmp = RREG32_MC(0x32);
356	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);	360	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
357	tmp = RREG32_MC(0x33);	361	tmp = RREG32_MC(0x33);
358	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);	362	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
359	tmp = RREG32_MC(0x34);	363	tmp = RREG32_MC(0x34);
360	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);	364	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
361	tmp = RREG32_MC(0x35);	365	tmp = RREG32_MC(0x35);
362	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);	366	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
363	tmp = RREG32_MC(0x36);	367	tmp = RREG32_MC(0x36);
364	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);	368	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
365	tmp = RREG32_MC(0x37);	369	tmp = RREG32_MC(0x37);
366	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);	370	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
367	return 0;	371	return 0;
368	}	372	}
369		373
370	static struct drm_info_list rs400_gart_info_list[] = {	374	static struct drm_info_list rs400_gart_info_list[] = {
371	{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},	375	{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
372	};	376	};
373	#endif	377	#endif
374		378
375	static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)	379	static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
376	{	380	{
377	#if defined(CONFIG_DEBUG_FS)	381	#if defined(CONFIG_DEBUG_FS)
378	return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);	382	return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
379	#else	383	#else
380	return 0;	384	return 0;
381	#endif	385	#endif
382	}	386	}
383		387
384	static void rs400_mc_program(struct radeon_device *rdev)	388	static void rs400_mc_program(struct radeon_device *rdev)
385	{	389	{
386	struct r100_mc_save save;	390	struct r100_mc_save save;
387		391
388	/* Stops all mc clients */	392	/* Stops all mc clients */
389	r100_mc_stop(rdev, &save);	393	r100_mc_stop(rdev, &save);
390		394
391	/* Wait for mc idle */	395	/* Wait for mc idle */
392	if (rs400_mc_wait_for_idle(rdev))	396	if (rs400_mc_wait_for_idle(rdev))
393	dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");	397	dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
394	WREG32(R_000148_MC_FB_LOCATION,	398	WREG32(R_000148_MC_FB_LOCATION,
395	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|	399	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
396	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));	400	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
397		401
398	r100_mc_resume(rdev, &save);	402	r100_mc_resume(rdev, &save);
399	}	403	}
400		404
401	static int rs400_startup(struct radeon_device *rdev)	405	static int rs400_startup(struct radeon_device *rdev)
402	{	406	{
403	int r;	407	int r;
404		408
405	r100_set_common_regs(rdev);	409	r100_set_common_regs(rdev);
406		410
407	rs400_mc_program(rdev);	411	rs400_mc_program(rdev);
408	/* Resume clock */	412	/* Resume clock */
409	r300_clock_startup(rdev);	413	r300_clock_startup(rdev);
410	/* Initialize GPU configuration (# pipes, ...) */	414	/* Initialize GPU configuration (# pipes, ...) */
411	rs400_gpu_init(rdev);	415	rs400_gpu_init(rdev);
412	r100_enable_bm(rdev);	416	r100_enable_bm(rdev);
413	/* Initialize GART (initialize after TTM so we can allocate	417	/* Initialize GART (initialize after TTM so we can allocate
414	* memory through TTM but finalize after TTM) */	418	* memory through TTM but finalize after TTM) */
415	r = rs400_gart_enable(rdev);	419	r = rs400_gart_enable(rdev);
416	if (r)	420	if (r)
417	return r;	421	return r;
418		422
419	/* allocate wb buffer */	423	/* allocate wb buffer */
420	r = radeon_wb_init(rdev);	424	r = radeon_wb_init(rdev);
421	if (r)	425	if (r)
422	return r;	426	return r;
423		427
424	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);	428	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
425	if (r) {	429	if (r) {
426	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);	430	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
427	return r;	431	return r;
428	}	432	}
429		433
430	/* Enable IRQ */	434	/* Enable IRQ */
431	if (!rdev->irq.installed) {	435	if (!rdev->irq.installed) {
432	r = radeon_irq_kms_init(rdev);	436	r = radeon_irq_kms_init(rdev);
433	if (r)	437	if (r)
434	return r;	438	return r;
435	}	439	}
436		440
437	r100_irq_set(rdev);	441	r100_irq_set(rdev);
438	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);	442	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
439	/* 1M ring buffer */	443	/* 1M ring buffer */
440	r = r100_cp_init(rdev, 1024 * 1024);	444	r = r100_cp_init(rdev, 1024 * 1024);
441	if (r) {	445	if (r) {
442	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);	446	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
443	return r;	447	return r;
444	}	448	}
445		449
446	r = radeon_ib_pool_init(rdev);	450	r = radeon_ib_pool_init(rdev);
447	if (r) {	451	if (r) {
448	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);	452	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
449	return r;	453	return r;
450	}	454	}
451		455
452	return 0;	456	return 0;
453	}	457	}
454		458
455		459
-		460
-		461	void rs400_fini(struct radeon_device *rdev)
-		462	{
-		463	radeon_pm_fini(rdev);
-		464	r100_cp_fini(rdev);
-		465	radeon_wb_fini(rdev);
-		466	radeon_ib_pool_fini(rdev);
-		467	radeon_gem_fini(rdev);
-		468	rs400_gart_fini(rdev);
-		469	radeon_irq_kms_fini(rdev);
-		470	radeon_fence_driver_fini(rdev);
-		471	radeon_bo_fini(rdev);
-		472	radeon_atombios_fini(rdev);
-		473	kfree(rdev->bios);
-		474	rdev->bios = NULL;
456		475	}
457		476
458	int rs400_init(struct radeon_device *rdev)	477	int rs400_init(struct radeon_device *rdev)
459	{	478	{
460	int r;	479	int r;
461		480
462	/* Disable VGA */	481	/* Disable VGA */
463	r100_vga_render_disable(rdev);	482	r100_vga_render_disable(rdev);
464	/* Initialize scratch registers */	483	/* Initialize scratch registers */
465	radeon_scratch_init(rdev);	484	radeon_scratch_init(rdev);
466	/* Initialize surface registers */	485	/* Initialize surface registers */
467	radeon_surface_init(rdev);	486	radeon_surface_init(rdev);
468	/* TODO: disable VGA need to use VGA request */	487	/* TODO: disable VGA need to use VGA request */
469	/* restore some register to sane defaults */	488	/* restore some register to sane defaults */
470	r100_restore_sanity(rdev);	489	r100_restore_sanity(rdev);
471	/* BIOS*/	490	/* BIOS*/
472	if (!radeon_get_bios(rdev)) {	491	if (!radeon_get_bios(rdev)) {
473	if (ASIC_IS_AVIVO(rdev))	492	if (ASIC_IS_AVIVO(rdev))
474	return -EINVAL;	493	return -EINVAL;
475	}	494	}
476	if (rdev->is_atom_bios) {	495	if (rdev->is_atom_bios) {
477	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");	496	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
478	return -EINVAL;	497	return -EINVAL;
479	} else {	498	} else {

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/rs400.c @ 1990 – Rev 5139 → 6104