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Rev 1413 Rev 1430
Line 111... Line 111...
111 
int rs400_gart_enable(struct radeon_device *rdev)
 111 
int rs400_gart_enable(struct radeon_device *rdev)
112 
{
 112 
{
113 
	uint32_t size_reg;
 113 
	uint32_t size_reg;
114 
	uint32_t tmp;
 114 
	uint32_t tmp;
Line -... Line 115...
- 
 
 115 
 
115 
 
 116 
	radeon_gart_restore(rdev);
116 
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 117 
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
117 
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 118 
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
118 
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 119 
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
119 
	/* Check gart size */
 120 
	/* Check gart size */
Line 148... Line 149...
148 
		WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
 149 
		WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
149 
	} else {
 150 
	} else {
150 
		WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
 151 
		WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
151 
		WREG32(RS480_AGP_BASE_2, 0);
 152 
		WREG32(RS480_AGP_BASE_2, 0);
152 
	}
 153 
	}
153 
	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 - 
 
154 
	tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16);
 154 
	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
155 
	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
 155 
	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
156 
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 156 
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
157 
		WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
 157 
		WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
158 
		tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 158 
		tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
159 
		WREG32(RADEON_BUS_CNTL, tmp);
 159 
		WREG32(RADEON_BUS_CNTL, tmp);
160 
	} else {
 160 
	} else {
Line 249... Line 249...
249 
		printk(KERN_WARNING "rs400: Failed to wait MC idle while "
 249 
		printk(KERN_WARNING "rs400: Failed to wait MC idle while "
250 
		       "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
 250 
		       "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
251 
	}
 251 
	}
252 
}
 252 
}
Line 253... Line 253...
253 
 
 253 
 
254 
void rs400_vram_info(struct radeon_device *rdev)
 254 
void rs400_mc_init(struct radeon_device *rdev)
- 
 
 255 
{
- 
 
 256 
	u64 base;
255 
{
 257 
 
- 
 
 258 
	rs400_gart_adjust_size(rdev);
256 
	rs400_gart_adjust_size(rdev);
 259 
	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
257 
	/* DDR for all card after R300 & IGP */
 260 
	/* DDR for all card after R300 & IGP */
258 
	rdev->mc.vram_is_ddr = true;
 261 
	rdev->mc.vram_is_ddr = true;
259 
	rdev->mc.vram_width = 128;
 - 
 
260 
 
 262 
	rdev->mc.vram_width = 128;
- 
 
 263 
	r100_vram_init_sizes(rdev);
- 
 
 264 
	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
- 
 
 265 
	radeon_vram_location(rdev, &rdev->mc, base);
261 
	r100_vram_init_sizes(rdev);
 266 
	radeon_gtt_location(rdev, &rdev->mc);
Line 262... Line 267...
262 
}
 267 
}
263 
 
 268 
 
264 
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 269 
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
Line 360... Line 365...
360 
#else
 365 
#else
361 
	return 0;
 366 
	return 0;
362 
#endif
 367 
#endif
363 
}
 368 
}
Line 364... Line -...
364 
 
 - 
 
365 
static int rs400_mc_init(struct radeon_device *rdev)
 - 
 
366 
{
 - 
 
367 
	int r;
 - 
 
368 
	u32 tmp;
 - 
 
369 
 
 - 
 
370 
	/* Setup GPU memory space */
 - 
 
371 
	tmp = RREG32(R_00015C_NB_TOM);
 - 
 
372 
	rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
 - 
 
373 
	rdev->mc.gtt_location = 0xFFFFFFFFUL;
 - 
 
374 
	r = radeon_mc_setup(rdev);
 - 
 
375 
	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
 - 
 
376 
	if (r)
 - 
 
377 
		return r;
 - 
 
378 
	return 0;
 - 
 
379 
}
 - 
 
380 
 
 369 
 
381 
void rs400_mc_program(struct radeon_device *rdev)
 370 
void rs400_mc_program(struct radeon_device *rdev)
382 
{
 371 
{
Line 383... Line 372...
383 
	struct r100_mc_save save;
 372 
	struct r100_mc_save save;
Line 470... Line 459...
470 
 
 459 
 
471 
	/* Initialize clocks */
 460 
	/* Initialize clocks */
472 
	radeon_get_clock_info(rdev->ddev);
 461 
	radeon_get_clock_info(rdev->ddev);
473 
	/* Initialize power management */
 462 
	/* Initialize power management */
474 
	radeon_pm_init(rdev);
 - 
 
475 
	/* Get vram informations */
 - 
 
476 
	rs400_vram_info(rdev);
 463 
	radeon_pm_init(rdev);
477 
	/* Initialize memory controller (also test AGP) */
 464 
	/* initialize memory controller */
478 
	r = rs400_mc_init(rdev);
 - 
 
479 
	if (r)
 - 
 
480 
		return r;
 465 
	rs400_mc_init(rdev);
481 
	/* Fence driver */
 466 
	/* Fence driver */
482 
//	r = radeon_fence_driver_init(rdev);
 467 
//	r = radeon_fence_driver_init(rdev);
483 
//	if (r)
 468 
//	if (r)
484 
//		return r;
 469 
//		return r;