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Rev 1179 | Rev 1221 | ||
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Line 25... | Line 25... | ||
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include "radeon_reg.h" |
- | |
31 | #include "radeon.h" |
30 | #include "radeon.h" |
- | 31 | #include "rs400d.h" |
|
Line 32... | Line -... | ||
32 | - | ||
33 | /* rs400,rs480 depends on : */ |
- | |
34 | void r100_hdp_reset(struct radeon_device *rdev); |
- | |
35 | void r100_mc_disable_clients(struct radeon_device *rdev); |
- | |
36 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
- | |
37 | void r420_pipes_init(struct radeon_device *rdev); |
- | |
38 | 32 | ||
39 | /* This files gather functions specifics to : |
- | |
40 | * rs400,rs480 |
- | |
41 | * |
- | |
42 | * Some of these functions might be used by newer ASICs. |
- | |
43 | */ |
- | |
44 | void rs400_gpu_init(struct radeon_device *rdev); |
33 | /* This files gather functions specifics to : rs400,rs480 */ |
45 | int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
- | |
Line 46... | Line -... | ||
46 | - | ||
47 | - | ||
48 | /* |
- | |
49 | * GART functions. |
34 | static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
50 | */ |
35 | |
51 | void rs400_gart_adjust_size(struct radeon_device *rdev) |
36 | void rs400_gart_adjust_size(struct radeon_device *rdev) |
52 | { |
37 | { |
53 | /* Check gart size */ |
38 | /* Check gart size */ |
Line 236... | Line 221... | ||
236 | entry = cpu_to_le32(entry); |
221 | entry = cpu_to_le32(entry); |
237 | rdev->gart.table.ram.ptr[i] = entry; |
222 | rdev->gart.table.ram.ptr[i] = entry; |
238 | return 0; |
223 | return 0; |
239 | } |
224 | } |
Line 240... | Line -... | ||
240 | - | ||
241 | - | ||
242 | /* |
- | |
243 | * MC functions. |
- | |
244 | */ |
- | |
245 | int rs400_mc_init(struct radeon_device *rdev) |
- | |
246 | { |
- | |
247 | uint32_t tmp; |
- | |
248 | int r; |
- | |
249 | - | ||
250 | if (r100_debugfs_rbbm_init(rdev)) { |
- | |
251 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
- | |
252 | } |
- | |
253 | - | ||
254 | rs400_gpu_init(rdev); |
- | |
255 | rs400_gart_disable(rdev); |
- | |
256 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
- | |
257 | rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
- | |
258 | rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
- | |
259 | r = radeon_mc_setup(rdev); |
- | |
260 | if (r) { |
- | |
261 | return r; |
- | |
262 | } |
- | |
263 | - | ||
264 | r100_mc_disable_clients(rdev); |
- | |
265 | if (r300_mc_wait_for_idle(rdev)) { |
- | |
266 | printk(KERN_WARNING "Failed to wait MC idle while " |
- | |
267 | "programming pipes. Bad things might happen.\n"); |
- | |
268 | } |
- | |
269 | - | ||
270 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
- | |
271 | tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); |
- | |
272 | tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); |
- | |
273 | WREG32(RADEON_MC_FB_LOCATION, tmp); |
- | |
274 | tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS; |
- | |
275 | WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
- | |
276 | (void)RREG32(RADEON_HOST_PATH_CNTL); |
- | |
277 | WREG32(RADEON_HOST_PATH_CNTL, tmp); |
- | |
278 | (void)RREG32(RADEON_HOST_PATH_CNTL); |
- | |
279 | - | ||
280 | return 0; |
- | |
281 | } |
- | |
282 | - | ||
283 | void rs400_mc_fini(struct radeon_device *rdev) |
- | |
284 | { |
- | |
285 | } |
- | |
286 | - | ||
287 | - | ||
288 | /* |
- | |
289 | * Global GPU functions |
- | |
290 | */ |
- | |
291 | void rs400_errata(struct radeon_device *rdev) |
- | |
292 | { |
- | |
293 | rdev->pll_errata = 0; |
- | |
294 | } |
- | |
295 | 225 | ||
296 | void rs400_gpu_init(struct radeon_device *rdev) |
226 | void rs400_gpu_init(struct radeon_device *rdev) |
297 | { |
227 | { |
298 | /* FIXME: HDP same place on rs400 ? */ |
228 | /* FIXME: HDP same place on rs400 ? */ |
299 | r100_hdp_reset(rdev); |
229 | r100_hdp_reset(rdev); |
Line 303... | Line 233... | ||
303 | printk(KERN_WARNING "Failed to wait MC idle while " |
233 | printk(KERN_WARNING "Failed to wait MC idle while " |
304 | "programming pipes. Bad things might happen.\n"); |
234 | "programming pipes. Bad things might happen.\n"); |
305 | } |
235 | } |
306 | } |
236 | } |
Line 307... | Line -... | ||
307 | - | ||
308 | - | ||
309 | /* |
- | |
310 | * VRAM info. |
- | |
311 | */ |
237 | |
312 | void rs400_vram_info(struct radeon_device *rdev) |
238 | void rs400_vram_info(struct radeon_device *rdev) |
313 | { |
239 | { |
314 | rs400_gart_adjust_size(rdev); |
240 | rs400_gart_adjust_size(rdev); |
315 | /* DDR for all card after R300 & IGP */ |
241 | /* DDR for all card after R300 & IGP */ |
316 | rdev->mc.vram_is_ddr = true; |
242 | rdev->mc.vram_is_ddr = true; |
Line 317... | Line 243... | ||
317 | rdev->mc.vram_width = 128; |
243 | rdev->mc.vram_width = 128; |
318 | 244 | ||
Line 319... | Line -... | ||
319 | r100_vram_init_sizes(rdev); |
- | |
320 | } |
- | |
321 | - | ||
322 | - | ||
323 | /* |
245 | r100_vram_init_sizes(rdev); |
324 | * Indirect registers accessor |
246 | } |
325 | */ |
247 | |
Line 326... | Line 248... | ||
326 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
248 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
Line 338... | Line 260... | ||
338 | WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); |
260 | WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); |
339 | WREG32(RS480_NB_MC_DATA, (v)); |
261 | WREG32(RS480_NB_MC_DATA, (v)); |
340 | WREG32(RS480_NB_MC_INDEX, 0xff); |
262 | WREG32(RS480_NB_MC_INDEX, 0xff); |
341 | } |
263 | } |
Line 342... | Line -... | ||
342 | - | ||
343 | - | ||
344 | /* |
- | |
345 | * Debugfs info |
- | |
346 | */ |
264 | |
347 | #if defined(CONFIG_DEBUG_FS) |
265 | #if defined(CONFIG_DEBUG_FS) |
348 | static int rs400_debugfs_gart_info(struct seq_file *m, void *data) |
266 | static int rs400_debugfs_gart_info(struct seq_file *m, void *data) |
349 | { |
267 | { |
350 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
268 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
Line 417... | Line 335... | ||
417 | static struct drm_info_list rs400_gart_info_list[] = { |
335 | static struct drm_info_list rs400_gart_info_list[] = { |
418 | {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, |
336 | {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, |
419 | }; |
337 | }; |
420 | #endif |
338 | #endif |
Line 421... | Line 339... | ||
421 | 339 | ||
422 | int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
340 | static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
423 | { |
341 | { |
424 | #if defined(CONFIG_DEBUG_FS) |
342 | #if defined(CONFIG_DEBUG_FS) |
425 | return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); |
343 | return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); |
426 | #else |
344 | #else |
427 | return 0; |
345 | return 0; |
428 | #endif |
346 | #endif |
- | 347 | } |
|
- | 348 | ||
- | 349 | static int rs400_mc_init(struct radeon_device *rdev) |
|
- | 350 | { |
|
- | 351 | int r; |
|
- | 352 | u32 tmp; |
|
- | 353 | ||
- | 354 | /* Setup GPU memory space */ |
|
- | 355 | tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); |
|
- | 356 | rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16; |
|
- | 357 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
|
- | 358 | r = radeon_mc_setup(rdev); |
|
- | 359 | if (r) |
|
- | 360 | return r; |
|
- | 361 | return 0; |
|
- | 362 | } |
|
- | 363 | ||
- | 364 | void rs400_mc_program(struct radeon_device *rdev) |
|
- | 365 | { |
|
- | 366 | struct r100_mc_save save; |
|
- | 367 | ||
- | 368 | /* Stops all mc clients */ |
|
- | 369 | r100_mc_stop(rdev, &save); |
|
- | 370 | ||
- | 371 | /* Wait for mc idle */ |
|
- | 372 | if (r300_mc_wait_for_idle(rdev)) |
|
- | 373 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
|
- | 374 | WREG32(R_000148_MC_FB_LOCATION, |
|
- | 375 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
|
- | 376 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
|
- | 377 | ||
- | 378 | r100_mc_resume(rdev, &save); |
|
- | 379 | } |
|
- | 380 | ||
- | 381 | static int rs400_startup(struct radeon_device *rdev) |
|
- | 382 | { |
|
- | 383 | int r; |
|
- | 384 | ||
- | 385 | rs400_mc_program(rdev); |
|
- | 386 | /* Resume clock */ |
|
- | 387 | r300_clock_startup(rdev); |
|
- | 388 | /* Initialize GPU configuration (# pipes, ...) */ |
|
- | 389 | rs400_gpu_init(rdev); |
|
- | 390 | /* Initialize GART (initialize after TTM so we can allocate |
|
- | 391 | * memory through TTM but finalize after TTM) */ |
|
- | 392 | r = rs400_gart_enable(rdev); |
|
- | 393 | if (r) |
|
- | 394 | return r; |
|
- | 395 | /* Enable IRQ */ |
|
- | 396 | // rdev->irq.sw_int = true; |
|
- | 397 | // r100_irq_set(rdev); |
|
- | 398 | /* 1M ring buffer */ |
|
- | 399 | // r = r100_cp_init(rdev, 1024 * 1024); |
|
- | 400 | // if (r) { |
|
- | 401 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
|
- | 402 | // return r; |
|
- | 403 | // } |
|
- | 404 | // r = r100_wb_init(rdev); |
|
- | 405 | // if (r) |
|
- | 406 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
|
- | 407 | // r = r100_ib_init(rdev); |
|
- | 408 | // if (r) { |
|
- | 409 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
|
- | 410 | // return r; |
|
- | 411 | // } |
|
- | 412 | return 0; |
|
- | 413 | } |
|
- | 414 | ||
- | 415 | ||
- | 416 | ||
- | 417 | ||
- | 418 | int rs400_init(struct radeon_device *rdev) |
|
- | 419 | { |
|
- | 420 | int r; |
|
- | 421 | ||
- | 422 | /* Disable VGA */ |
|
- | 423 | r100_vga_render_disable(rdev); |
|
- | 424 | /* Initialize scratch registers */ |
|
- | 425 | radeon_scratch_init(rdev); |
|
- | 426 | /* Initialize surface registers */ |
|
- | 427 | radeon_surface_init(rdev); |
|
- | 428 | /* TODO: disable VGA need to use VGA request */ |
|
- | 429 | /* BIOS*/ |
|
- | 430 | if (!radeon_get_bios(rdev)) { |
|
- | 431 | if (ASIC_IS_AVIVO(rdev)) |
|
- | 432 | return -EINVAL; |
|
- | 433 | } |
|
- | 434 | if (rdev->is_atom_bios) { |
|
- | 435 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
|
- | 436 | return -EINVAL; |
|
- | 437 | } else { |
|
- | 438 | r = radeon_combios_init(rdev); |
|
- | 439 | if (r) |
|
- | 440 | return r; |
|
- | 441 | } |
|
- | 442 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
|
- | 443 | if (radeon_gpu_reset(rdev)) { |
|
- | 444 | dev_warn(rdev->dev, |
|
- | 445 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
|
- | 446 | RREG32(R_000E40_RBBM_STATUS), |
|
- | 447 | RREG32(R_0007C0_CP_STAT)); |
|
- | 448 | } |
|
- | 449 | /* check if cards are posted or not */ |
|
- | 450 | if (!radeon_card_posted(rdev) && rdev->bios) { |
|
- | 451 | DRM_INFO("GPU not posted. posting now...\n"); |
|
- | 452 | radeon_combios_asic_init(rdev->ddev); |
|
- | 453 | } |
|
- | 454 | /* Initialize clocks */ |
|
- | 455 | radeon_get_clock_info(rdev->ddev); |
|
- | 456 | /* Get vram informations */ |
|
- | 457 | rs400_vram_info(rdev); |
|
- | 458 | /* Initialize memory controller (also test AGP) */ |
|
- | 459 | r = rs400_mc_init(rdev); |
|
- | 460 | if (r) |
|
- | 461 | return r; |
|
- | 462 | /* Fence driver */ |
|
- | 463 | // r = radeon_fence_driver_init(rdev); |
|
- | 464 | // if (r) |
|
- | 465 | // return r; |
|
- | 466 | // r = radeon_irq_kms_init(rdev); |
|
- | 467 | // if (r) |
|
- | 468 | // return r; |
|
- | 469 | /* Memory manager */ |
|
- | 470 | r = radeon_object_init(rdev); |
|
- | 471 | if (r) |
|
- | 472 | return r; |
|
- | 473 | r = rs400_gart_init(rdev); |
|
- | 474 | if (r) |
|
- | 475 | return r; |
|
- | 476 | r300_set_reg_safe(rdev); |
|
- | 477 | rdev->accel_working = true; |
|
- | 478 | r = rs400_startup(rdev); |
|
- | 479 | if (r) { |
|
- | 480 | /* Somethings want wront with the accel init stop accel */ |
|
- | 481 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
|
- | 482 | // rs400_suspend(rdev); |
|
- | 483 | // r100_cp_fini(rdev); |
|
- | 484 | // r100_wb_fini(rdev); |
|
- | 485 | // r100_ib_fini(rdev); |
|
- | 486 | rs400_gart_fini(rdev); |
|
- | 487 | // radeon_irq_kms_fini(rdev); |
|
- | 488 | rdev->accel_working = false; |
|
- | 489 | } |
|
- | 490 | return 0; |