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Rev 6104 Rev 6321
Line 453... Line 453...
453
	uint64_t eoffset;
453
	uint64_t eoffset;
454
	int r;
454
	int r;
Line 455... Line 455...
455
 
455
 
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	if (soffset) {
456
	if (soffset) {
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		/* make sure object fit at this offset */
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		/* make sure object fit at this offset */
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		eoffset = soffset + size;
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		eoffset = soffset + size - 1;
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		if (soffset >= eoffset) {
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		if (soffset >= eoffset) {
460
			r = -EINVAL;
460
			r = -EINVAL;
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			goto error_unreserve;
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			goto error_unreserve;
Line 462... Line 462...
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		}
462
		}
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463
 
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		last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
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		last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
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		if (last_pfn > rdev->vm_manager.max_pfn) {
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		if (last_pfn >= rdev->vm_manager.max_pfn) {
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			dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
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			dev_err(rdev->dev, "va above limit (0x%08X >= 0x%08X)\n",
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				last_pfn, rdev->vm_manager.max_pfn);
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				last_pfn, rdev->vm_manager.max_pfn);
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			r = -EINVAL;
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			r = -EINVAL;
Line 476... Line 476...
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	mutex_lock(&vm->mutex);
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	mutex_lock(&vm->mutex);
477
	soffset /= RADEON_GPU_PAGE_SIZE;
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	soffset /= RADEON_GPU_PAGE_SIZE;
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	eoffset /= RADEON_GPU_PAGE_SIZE;
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	eoffset /= RADEON_GPU_PAGE_SIZE;
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	if (soffset || eoffset) {
479
	if (soffset || eoffset) {
480
		struct interval_tree_node *it;
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		struct interval_tree_node *it;
481
		it = interval_tree_iter_first(&vm->va, soffset, eoffset - 1);
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		it = interval_tree_iter_first(&vm->va, soffset, eoffset);
482
		if (it && it != &bo_va->it) {
482
		if (it && it != &bo_va->it) {
483
			struct radeon_bo_va *tmp;
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			struct radeon_bo_va *tmp;
484
			tmp = container_of(it, struct radeon_bo_va, it);
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			tmp = container_of(it, struct radeon_bo_va, it);
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			/* bo and tmp overlap, invalid offset */
485
			/* bo and tmp overlap, invalid offset */
486
			dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with "
486
			dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with "
Line 516... Line 516...
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	}
516
	}
Line 517... Line 517...
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517
 
518
	if (soffset || eoffset) {
518
	if (soffset || eoffset) {
519
		spin_lock(&vm->status_lock);
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		spin_lock(&vm->status_lock);
520
		bo_va->it.start = soffset;
520
		bo_va->it.start = soffset;
521
		bo_va->it.last = eoffset - 1;
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		bo_va->it.last = eoffset;
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		list_add(&bo_va->vm_status, &vm->cleared);
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		list_add(&bo_va->vm_status, &vm->cleared);
523
		spin_unlock(&vm->status_lock);
523
		spin_unlock(&vm->status_lock);
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		interval_tree_insert(&bo_va->it, &vm->va);
524
		interval_tree_insert(&bo_va->it, &vm->va);
Line 886... Line 886...
886
				struct radeon_fence *fence)
886
				struct radeon_fence *fence)
887
{
887
{
888
	unsigned i;
888
	unsigned i;
Line 889... Line 889...
889
 
889
 
890
	start >>= radeon_vm_block_size;
890
	start >>= radeon_vm_block_size;
Line 891... Line 891...
891
	end >>= radeon_vm_block_size;
891
	end = (end - 1) >> radeon_vm_block_size;
892
 
892
 
893
	for (i = start; i <= end; ++i)
893
	for (i = start; i <= end; ++i)