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Rev 6104 | Rev 6321 | ||
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Line 453... | Line 453... | ||
453 | uint64_t eoffset; |
453 | uint64_t eoffset; |
454 | int r; |
454 | int r; |
Line 455... | Line 455... | ||
455 | 455 | ||
456 | if (soffset) { |
456 | if (soffset) { |
457 | /* make sure object fit at this offset */ |
457 | /* make sure object fit at this offset */ |
458 | eoffset = soffset + size; |
458 | eoffset = soffset + size - 1; |
459 | if (soffset >= eoffset) { |
459 | if (soffset >= eoffset) { |
460 | r = -EINVAL; |
460 | r = -EINVAL; |
461 | goto error_unreserve; |
461 | goto error_unreserve; |
Line 462... | Line 462... | ||
462 | } |
462 | } |
463 | 463 | ||
464 | last_pfn = eoffset / RADEON_GPU_PAGE_SIZE; |
464 | last_pfn = eoffset / RADEON_GPU_PAGE_SIZE; |
465 | if (last_pfn > rdev->vm_manager.max_pfn) { |
465 | if (last_pfn >= rdev->vm_manager.max_pfn) { |
466 | dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n", |
466 | dev_err(rdev->dev, "va above limit (0x%08X >= 0x%08X)\n", |
467 | last_pfn, rdev->vm_manager.max_pfn); |
467 | last_pfn, rdev->vm_manager.max_pfn); |
468 | r = -EINVAL; |
468 | r = -EINVAL; |
Line 476... | Line 476... | ||
476 | mutex_lock(&vm->mutex); |
476 | mutex_lock(&vm->mutex); |
477 | soffset /= RADEON_GPU_PAGE_SIZE; |
477 | soffset /= RADEON_GPU_PAGE_SIZE; |
478 | eoffset /= RADEON_GPU_PAGE_SIZE; |
478 | eoffset /= RADEON_GPU_PAGE_SIZE; |
479 | if (soffset || eoffset) { |
479 | if (soffset || eoffset) { |
480 | struct interval_tree_node *it; |
480 | struct interval_tree_node *it; |
481 | it = interval_tree_iter_first(&vm->va, soffset, eoffset - 1); |
481 | it = interval_tree_iter_first(&vm->va, soffset, eoffset); |
482 | if (it && it != &bo_va->it) { |
482 | if (it && it != &bo_va->it) { |
483 | struct radeon_bo_va *tmp; |
483 | struct radeon_bo_va *tmp; |
484 | tmp = container_of(it, struct radeon_bo_va, it); |
484 | tmp = container_of(it, struct radeon_bo_va, it); |
485 | /* bo and tmp overlap, invalid offset */ |
485 | /* bo and tmp overlap, invalid offset */ |
486 | dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with " |
486 | dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with " |
Line 516... | Line 516... | ||
516 | } |
516 | } |
Line 517... | Line 517... | ||
517 | 517 | ||
518 | if (soffset || eoffset) { |
518 | if (soffset || eoffset) { |
519 | spin_lock(&vm->status_lock); |
519 | spin_lock(&vm->status_lock); |
520 | bo_va->it.start = soffset; |
520 | bo_va->it.start = soffset; |
521 | bo_va->it.last = eoffset - 1; |
521 | bo_va->it.last = eoffset; |
522 | list_add(&bo_va->vm_status, &vm->cleared); |
522 | list_add(&bo_va->vm_status, &vm->cleared); |
523 | spin_unlock(&vm->status_lock); |
523 | spin_unlock(&vm->status_lock); |
524 | interval_tree_insert(&bo_va->it, &vm->va); |
524 | interval_tree_insert(&bo_va->it, &vm->va); |
Line 886... | Line 886... | ||
886 | struct radeon_fence *fence) |
886 | struct radeon_fence *fence) |
887 | { |
887 | { |
888 | unsigned i; |
888 | unsigned i; |
Line 889... | Line 889... | ||
889 | 889 | ||
890 | start >>= radeon_vm_block_size; |
890 | start >>= radeon_vm_block_size; |
Line 891... | Line 891... | ||
891 | end >>= radeon_vm_block_size; |
891 | end = (end - 1) >> radeon_vm_block_size; |
892 | 892 | ||
893 | for (i = start; i <= end; ++i) |
893 | for (i = start; i <= end; ++i) |