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 *          Christian Konig

 * IB

 * IBs (Indirect Buffers) and areas of GPU accessible memory where

 * commands are stored.  You can put a pointer to the IB in the

 * command ring and the hw will fetch the commands from the IB

 * and execute them.  Generally userspace acceleration drivers

 * produce command buffers which are send to the kernel and

 */

static int radeon_debugfs_sa_init(struct radeon_device *rdev);

/**

 * radeon_ib_get - request an IB (Indirect Buffer)

 *

 * @rdev: radeon_device pointer

 * @ring: ring index the IB is associated with

 * @ib: IB object returned

 * @size: requested IB size

 *

 * Request an IB (all asics).  IBs are allocated using the

 * suballocator.

 * Returns 0 on success, error on failure.

int radeon_ib_get(struct radeon_device *rdev, int ring,

		  struct radeon_ib *ib, struct radeon_vm *vm,

			return r;

		}

	ib->ring = ring;

	ib->fence = NULL;

	ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);

	ib->vm = vm;

	if (vm) {

		/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address

		 * space and soffset is the offset inside the pool bo

		 */

	for (i = 0; i < RADEON_NUM_RINGS; ++i)

	return 0;

}

/**

 * radeon_ib_free - free an IB (Indirect Buffer)

 *

 * @rdev: radeon_device pointer

 * @ib: IB object to free

	radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);

	radeon_fence_unref(&ib->fence);

}

/**

 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring

 *

 * @rdev: radeon_device pointer

 * @ib: IB object to schedule

 * @const_ib: Const IB to schedule (SI only)

 *

 * Schedule an IB on the associated ring (all asics).

 * Returns 0 on success, error on failure.

 *

 * On SI, there are two parallel engines fed from the primary ring,

 * the CE (Constant Engine) and the DE (Drawing Engine).  Since

 * resource descriptors have moved to memory, the CE allows you to

 * prime the caches while the DE is updating register state so that

 * the resource descriptors will be already in cache when the draw is

 * processed.  To accomplish this, the userspace driver submits two

 * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior

 */

int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,

		dev_err(rdev->dev, "couldn't schedule ib\n");

		return -EINVAL;

	}

	/* 64 dwords should be enough for fence too */

	r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);

	if (r) {

		dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);

		return r;

	}

	for (i = 0; i < RADEON_NUM_RINGS; ++i) {

		struct radeon_fence *fence = ib->sync_to[i];

		if (radeon_fence_need_sync(fence, ib->ring)) {

			need_sync = true;

			radeon_semaphore_sync_rings(rdev, ib->semaphore,

						    fence->ring, ib->ring);

			radeon_fence_note_sync(fence, ib->ring);

		}

	}

	/* immediately free semaphore when we don't need to sync */

	if (!need_sync) {

		radeon_semaphore_free(rdev, &ib->semaphore, NULL);

	}

	/* if we can't remember our last VM flush then flush now! */

	if (ib->vm && !ib->vm->last_flush) {

		radeon_ring_vm_flush(rdev, ib->ring, ib->vm);

	}

		radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);

		dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);

	if (const_ib) {

	if (ib->vm && !ib->vm->last_flush) {

		ib->vm->last_flush = radeon_fence_ref(ib->fence);

	}

	radeon_ring_unlock_commit(rdev, ring);

	return 0;

}

/**

 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool

		return 0;

		return r;

	}

	rdev->ib_pool_ready = true;

	if (radeon_debugfs_sa_init(rdev)) {

		dev_err(rdev->dev, "failed to register debugfs file for SA\n");

	}

	return 0;

/**

 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool

 *

 * @rdev: radeon_device pointer

 *

 * Tear down the suballocator managing the pool of memory

 * for use as IBs (all asics).

 */

void radeon_ib_pool_fini(struct radeon_device *rdev)

{

	if (rdev->ib_pool_ready) {

		radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);

		radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);

		rdev->ib_pool_ready = false;

	}

}

/**

 * radeon_ib_ring_tests - test IBs on the rings

 *

 * Returns 0 on success, error if the primary GFX ring

 * IB test fails.

	unsigned i;

	int r;

	for (i = 0; i < RADEON_NUM_RINGS; ++i) {

		struct radeon_ring *ring = &rdev->ring[i];

		if (!ring->ready)

			continue;

		r = radeon_ib_test(rdev, i, ring);

			if (i == RADEON_RING_TYPE_GFX_INDEX) {

				return r;

			} else {

				/* still not good, but we can live with it */

				DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);

	}

		}

	}

	return 0;

}

/*

 * Rings

 * Most engines on the GPU are fed via ring buffers.  Ring

 * buffers are areas of GPU accessible memory that the host

 * writes commands into and the GPU reads commands out of.

 * There is a rptr (read pointer) that determines where the

 * GPU is currently reading, and a wptr (write pointer)

 * which determines where the host has written.  When the

 * pointers are equal, the ring is idle.  When the host

 * writes commands to the ring buffer, it increments the

 * wptr.  The GPU then starts fetching commands and executes

 * them until the pointers are equal again.

 */

static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);

/**

 * radeon_ring_write - write a value to the ring

 *

 * @ring: radeon_ring structure holding ring information

 * @v: dword (dw) value to write

 *

 * Write a value to the requested ring buffer (all asics).

 */

void radeon_ring_write(struct radeon_ring *ring, uint32_t v)

{

#if DRM_DEBUG_CODE

	if (ring->count_dw <= 0) {

		DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");

	}

#endif

	ring->ring[ring->wptr++] = v;

	ring->wptr &= ring->ptr_mask;

}

/**

 * radeon_ring_supports_scratch_reg - check if the ring supports

 * writing to scratch registers

 *

 * @rdev: radeon_device pointer

 * @ring: radeon_ring structure holding ring information

 *

 * Check if a specific ring supports writing to scratch registers (all asics).

 * Returns true if the ring supports writing to scratch regs, false if not.

 */

bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,

				      struct radeon_ring *ring)

{

	switch (ring->idx) {

	case RADEON_RING_TYPE_GFX_INDEX:

	case CAYMAN_RING_TYPE_CP1_INDEX:

	case CAYMAN_RING_TYPE_CP2_INDEX:

		return true;

	default:

		return false;

	}

}

 * @rdev: radeon_device pointer

	if (rdev->wb.enabled)

		rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);

	else

		rptr = RREG32(ring->rptr_reg);

	ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;

	/* This works because ring_size is a power of 2 */

	ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));

	ring->ring_free_dw -= ring->wptr;

	ring->ring_free_dw &= ring->ptr_mask;

	if (!ring->ring_free_dw) {

	while (ndw > (ring->ring_free_dw - 1)) {

		radeon_ring_free_size(rdev, ring);

		if (ndw < ring->ring_free_dw) {

			break;

		}

//        r = radeon_fence_wait_next(rdev);

//       if (r) {

//           mutex_unlock(&rdev->cp.mutex);

//           return r;

//       }

	}

 *

 * Lock the ring and allocate @ndw dwords in the ring buffer

 * (all asics).

 * Returns 0 on success, error on failure.

 */

int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)

{

	int r;

	mutex_lock(&rdev->ring_lock);

/**

 * radeon_ring_commit - tell the GPU to execute the new

 * commands on the ring buffer

 *

 * @rdev: radeon_device pointer

 * @ring: radeon_ring structure holding ring information

 *

 * Update the wptr (write pointer) to tell the GPU to

 * execute new commands on the ring buffer (all asics).

 */

void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)

{

	/* We pad to match fetch size */

	while (ring->wptr & ring->align_mask) {

	}

	DRM_MEMORYBARRIER();

	WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);

	(void)RREG32(ring->wptr_reg);

}

/**

 * radeon_ring_unlock_commit - tell the GPU to execute the new

 * commands on the ring buffer and unlock it

 *

 * @rdev: radeon_device pointer

 * @ring: radeon_ring structure holding ring information

 *

 * Call radeon_ring_commit() then unlock the ring (all asics).

 */

void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)

{

	radeon_ring_commit(rdev, ring);

	mutex_unlock(&rdev->ring_lock);

}

/**

 * radeon_ring_undo - reset the wptr

 *

 * @ring: radeon_ring structure holding ring information

 *

 * Reset the driver's copy of the wtpr (all asics).

 */

void radeon_ring_undo(struct radeon_ring *ring)

{

	ring->wptr = ring->wptr_old;

}

/**

 * radeon_ring_unlock_undo - reset the wptr and unlock the ring

 *

 * @ring: radeon_ring structure holding ring information

 *

 * Call radeon_ring_undo() then unlock the ring (all asics).

 */

void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)

{

	radeon_ring_undo(ring);

	mutex_unlock(&rdev->ring_lock);

}

/**

 * radeon_ring_force_activity - add some nop packets to the ring

 *

 * @rdev: radeon_device pointer

 * @ring: radeon_ring structure holding ring information

 *

 * Add some nop packets to the ring to force activity (all asics).

 * Used for lockup detection to see if the rptr is advancing.

 */

void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)

{

	int r;

	radeon_ring_free_size(rdev, ring);

	if (ring->rptr == ring->wptr) {

		r = radeon_ring_alloc(rdev, ring, 1);

			radeon_ring_write(ring, ring->nop);

			radeon_ring_commit(rdev, ring);

		}

	}

}

/**

 * radeon_ring_force_activity - update lockup variables

 *

 * @ring: radeon_ring structure holding ring information

 *

 * Update the last rptr value and timestamp (all asics).

 */

void radeon_ring_lockup_update(struct radeon_ring *ring)

{

	ring->last_rptr = ring->rptr;

	ring->last_activity = GetTimerTicks();

}

/**

 * @rdev:       radeon device structure

 * @ring:       radeon_ring structure holding ring information

 *

 * We don't need to initialize the lockup tracking information as we will either

 * have CP rptr to a different value of jiffies wrap around which will force

 * initialization of the lockup tracking informations.

 *

 * A possible false positivie is if we get call after while and last_cp_rptr ==

 * the current CP rptr, even if it's unlikely it might happen. To avoid this

 * if the elapsed time since last call is bigger than 2 second than we return

 * false and update the tracking information. Due to this the caller must call

 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported

 * the fencing code should be cautious about that.

 *

 * Caller should write to the ring to force CP to do something so we don't get

 * false positive when CP is just gived nothing to do.

 *

 **/

bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)

{

	unsigned long cjiffies, elapsed;

	uint32_t rptr;

	cjiffies = GetTimerTicks();

	if (!time_after(cjiffies, ring->last_activity)) {

		/* likely a wrap around */

		radeon_ring_lockup_update(ring);

		return false;

	}

	rptr = RREG32(ring->rptr_reg);

	ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;

	if (ring->rptr != ring->last_rptr) {

		/* CP is still working no lockup */

		radeon_ring_lockup_update(ring);

		return false;

	}

	if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {

		dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);

		return true;

	}

	/* give a chance to the GPU ... */

	return false;

}

/**

 * radeon_ring_backup - Back up the content of a ring

 *

 * @rdev: radeon_device pointer

 * @ring: the ring we want to back up

 *

 * Saves all unprocessed commits from a ring, returns the number of dwords saved.

 */

unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,

			    uint32_t **data)

{

	unsigned size, ptr, i;

	/* just in case lock the ring */

	mutex_lock(&rdev->ring_lock);

	*data = NULL;

	if (ring->ring_obj == NULL) {

		mutex_unlock(&rdev->ring_lock);

		return 0;

	}

	if (!radeon_fence_count_emitted(rdev, ring->idx)) {

		return 0;

	/* calculate the number of dw on the ring */

	if (ring->rptr_save_reg)

		ptr = RREG32(ring->rptr_save_reg);

	else if (rdev->wb.enabled)

		ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);

	else {

		/* no way to read back the next rptr */

		mutex_unlock(&rdev->ring_lock);

		return 0;

	}

	size = ring->wptr + (ring->ring_size / 4);

	size -= ptr;

	size &= ring->ptr_mask;

	if (size == 0) {

		mutex_unlock(&rdev->ring_lock);

		return 0;

	}

	/* and then save the content of the ring */

	*data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);

	if (!*data) {

		mutex_unlock(&rdev->ring_lock);

		return 0;

	for (i = 0; i < size; ++i) {

		ptr &= ring->ptr_mask;

	}

	mutex_unlock(&rdev->ring_lock);

	return size;

/**

 * radeon_ring_restore - append saved commands to the ring again

 *

 * @rdev: radeon_device pointer

 * @ring: ring to append commands to

 * @size: number of dwords we want to write

 * @data: saved commands

 *

 * Allocates space on the ring and restore the previously saved commands.

 */

			unsigned size, uint32_t *data)

{

	int i, r;

	if (!size || !data)

		return 0;

	/* restore the saved ring content */

	r = radeon_ring_lock(rdev, ring, size);

	if (r)

		return r;

	for (i = 0; i < size; ++i) {

		radeon_ring_write(ring, data[i]);

	}

	kfree(data);

	return 0;

 * radeon_ring_init - init driver ring struct.

 *

 * @rdev: radeon_device pointer

 * @ring: radeon_ring structure holding ring information

 * @ring_size: size of the ring

 * @rptr_offs: offset of the rptr writeback location in the WB buffer

			return r;

		}

		r = radeon_bo_reserve(ring->ring_obj, false);

		if (unlikely(r != 0))

			return r;

		r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,

					&ring->gpu_addr);

		if (r) {

			radeon_bo_unreserve(ring->ring_obj);

		}

		r = radeon_bo_kmap(ring->ring_obj,

				       (void **)&ring->ring);

		radeon_bo_unreserve(ring->ring_obj);

		if (r) {

			dev_err(rdev->dev, "(%d) ring map failed\n", r);

			return r;

		}

		ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];

#if defined(CONFIG_DEBUG_FS)

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	int ridx = *(int*)node->info_ent->data;

	radeon_ring_free_size(rdev, ring);

	count = (ring->ring_size / 4) - ring->ring_free_dw;

	seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));

	if (ring->rptr_save_reg) {

	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);

	seq_printf(m, "%u dwords in ring\n", count);

		seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);

}

static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;

static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;

static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;

static struct drm_info_list radeon_debugfs_ring_info_list[] = {

	{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},

	{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},

	{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},

	struct drm_device *dev = node->minor->dev;

	radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);

}

#endif

static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)

#if defined(CONFIG_DEBUG_FS)

	unsigned i;

	for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {

		if (&rdev->ring[ridx] != ring)

			continue;

		r = radeon_debugfs_add_files(rdev, info, 1);

		return r;

#endif