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Rev 2997 Rev 3764
Line 7... Line 7...
7 
static struct drm_mm   mm_gtt;
 7 
static struct drm_mm   mm_gtt;
8 
static struct drm_mm   mm_vram;
 8 
static struct drm_mm   mm_vram;
Line 9... Line -...
9 
 
 - 
 
10 
 
 - 
 
11 
/**
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12 
 * Initialize an already allocate GEM object of the specified size with
 - 
 
13 
 * shmfs backing store.
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14 
 */
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15 
int drm_gem_object_init(struct drm_device *dev,
 - 
 
16 
            struct drm_gem_object *obj, size_t size)
 - 
 
17 
{
 - 
 
18 
    BUG_ON((size & (PAGE_SIZE - 1)) != 0);
 - 
 
19 
 
 - 
 
20 
    obj->dev = dev;
 - 
 
21 
    obj->filp = NULL;
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22 
 
 - 
 
23 
    atomic_set(&obj->handle_count, 0);
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24 
    obj->size = size;
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25 
 
 - 
 
26 
    return 0;
 - 
 
27 
}
 - 
 
28 
 
 9 
 
29 
 
 10 
 
30 
int drm_mm_alloc(struct drm_mm *mm, size_t num_pages,
 11 
int drm_mm_alloc(struct drm_mm *mm, size_t num_pages,
31 
                 struct drm_mm_node **node)
 12 
                 struct drm_mm_node **node)
32 
{
 13 
{
Line 213... Line 194...
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    else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
 194 
    else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
214 
    {
 195 
    {
215 
        u32_t *pagelist;
 196 
        u32_t *pagelist;
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        bo->kptr  = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT );
 197 
        bo->kptr  = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT );
217 
        dbgprintf("kernel alloc %x\n", bo->kptr );
 198 
//        dbgprintf("kernel alloc %x\n", bo->kptr );
218 
 
 199 
 
Line 219... Line 200...
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        pagelist =  &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
 200 
        pagelist =  &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
220 
        dbgprintf("pagelist %x\n", pagelist);
 201 
//        dbgprintf("pagelist %x\n", pagelist);
221 
        radeon_gart_bind(bo->rdev, bo->tbo.offset,
 202 
        radeon_gart_bind(bo->rdev, bo->tbo.offset,
222 
                         bo->tbo.vm_node->size,  pagelist, NULL);
 203 
                         bo->tbo.vm_node->size,  pagelist, NULL);
223 
        bo->tbo.offset += (u64)bo->rdev->mc.gtt_start;
 204 
        bo->tbo.offset += (u64)bo->rdev->mc.gtt_start;
224 
    }
 205 
    }
225 
    else
 206 
    else
Line 243... Line 224...
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        dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 224 
        dev_err(bo->rdev->dev, "%p pin failed\n", bo);
244 
    return r;
 225 
    return r;
245 
};
 226 
};
246 
 
 227 
 
Line -... Line 228...
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 228 
int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
- 
 
 229 
                 u64 *gpu_addr)
- 
 
 230 
{
- 
 
 231 
    int r, i;
- 
 
 232 
 
- 
 
 233 
    if (bo->pin_count) {
- 
 
 234 
        bo->pin_count++;
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 235 
        if (gpu_addr)
- 
 
 236 
            *gpu_addr = radeon_bo_gpu_offset(bo);
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 237 
 
- 
 
 238 
        if (max_offset != 0) {
- 
 
 239 
            u64 domain_start;
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 240 
 
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 241 
            if (domain == RADEON_GEM_DOMAIN_VRAM)
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 242 
                domain_start = bo->rdev->mc.vram_start;
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 243 
            else
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 244 
                domain_start = bo->rdev->mc.gtt_start;
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 245 
            WARN_ON_ONCE(max_offset <
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 246 
                     (radeon_bo_gpu_offset(bo) - domain_start));
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 247 
        }
- 
 
 248 
 
- 
 
 249 
        return 0;
- 
 
 250 
    }
- 
 
 251 
 //   radeon_ttm_placement_from_domain(bo, domain);
- 
 
 252 
    if (domain == RADEON_GEM_DOMAIN_VRAM) {
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 253 
        /* force to pin into visible video ram */
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 254 
//        bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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 255 
        bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
- 
 
 256 
 
- 
 
 257 
    }
- 
 
 258 
    else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
- 
 
 259 
    {
- 
 
 260 
        u32_t *pagelist;
- 
 
 261 
        bo->kptr  = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT );
- 
 
 262 
        dbgprintf("kernel alloc %x\n", bo->kptr );
- 
 
 263 
 
- 
 
 264 
        pagelist =  &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
- 
 
 265 
        dbgprintf("pagelist %x\n", pagelist);
- 
 
 266 
        radeon_gart_bind(bo->rdev, bo->tbo.offset,
- 
 
 267 
                         bo->tbo.vm_node->size,  pagelist, NULL);
- 
 
 268 
        bo->tbo.offset += (u64)bo->rdev->mc.gtt_start;
- 
 
 269 
    }
- 
 
 270 
    else
- 
 
 271 
    {
- 
 
 272 
        DRM_ERROR("Unknown placement %x\n", bo->domain);
- 
 
 273 
        bo->tbo.offset = -1;
- 
 
 274 
        r = -1;
- 
 
 275 
    };
- 
 
 276 
 
- 
 
 277 
    if (likely(r == 0)) {
- 
 
 278 
        bo->pin_count = 1;
- 
 
 279 
        if (gpu_addr != NULL)
- 
 
 280 
            *gpu_addr = radeon_bo_gpu_offset(bo);
- 
 
 281 
    }
- 
 
 282 
 
- 
 
 283 
    if (unlikely(r != 0))
- 
 
 284 
        dev_err(bo->rdev->dev, "%p pin failed\n", bo);
- 
 
 285 
    return r;
- 
 
 286 
}
- 
 
 287 
 
- 
 
 288 
 
247 
int radeon_bo_unpin(struct radeon_bo *bo)
 289 
int radeon_bo_unpin(struct radeon_bo *bo)
248 
{
 290 
{
249 
    int r = 0;
 291 
    int r = 0;
Line 250... Line 292...
250 
 
 292 
 
Line 373... Line 415...
373 
        *pitch = bo->pitch;
 415 
        *pitch = bo->pitch;
374 
}
 416 
}
375 
 
 417 
 
Line 376... Line -...
376 
 
 - 
 
377 
/**
 - 
 
378 
 * Allocate a GEM object of the specified size with shmfs backing store
 - 
 
379 
 */
 - 
 
380 
struct drm_gem_object *
 - 
 
381 
drm_gem_object_alloc(struct drm_device *dev, size_t size)
 - 
 
382 
{
 - 
 
383 
    struct drm_gem_object *obj;
 - 
 
384 
 
 - 
 
385 
    BUG_ON((size & (PAGE_SIZE - 1)) != 0);
 - 
 
386 
 
 - 
 
387 
    obj = kzalloc(sizeof(*obj), GFP_KERNEL);
 - 
 
388 
 
 - 
 
389 
    obj->dev = dev;
 - 
 
390 
    obj->size = size;
 - 
 
391 
    return obj;
 - 
 
392 
}
 - 
 
Line 393... Line 418...
393 
 
 418 
 
394 
 
 419 
 
395 
int radeon_fb_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
 420 
int radeon_fb_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
396 
            unsigned long size, bool kernel, u32 domain,
 421 
            unsigned long size, bool kernel, u32 domain,