WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_object.c

 	return false;
+}
 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
 {
-    u32 c = 0, i;
+	u32 c = 0, i;
-    rbo->placement.placement = rbo->placements;
+	rbo->placement.placement = rbo->placements;
-    rbo->placement.busy_placement = rbo->placements;
+	rbo->placement.busy_placement = rbo->placements;
 	if (domain & RADEON_GEM_DOMAIN_VRAM) {
 		/* Try placing BOs which don't need CPU access outside of the
 		 * CPU accessible part of VRAM
 		 */
 		if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 		    rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
 			rbo->placements[c].fpfn =
 				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 						     TTM_PL_FLAG_UNCACHED |
-                    TTM_PL_FLAG_VRAM;
+						     TTM_PL_FLAG_VRAM;
+		}
 		rbo->placements[c].fpfn = 0;
 		rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 					     TTM_PL_FLAG_UNCACHED |
 					     TTM_PL_FLAG_VRAM;
+	}
-    if (domain & RADEON_GEM_DOMAIN_GTT) {
+	if (domain & RADEON_GEM_DOMAIN_GTT) {
 			   (rbo->rdev->flags & RADEON_IS_AGP)) {
 			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 				TTM_PL_FLAG_UNCACHED |
 				TTM_PL_FLAG_TT;
-        } else {
+		} else {
 			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 						     TTM_PL_FLAG_TT;
-        }
+		}
-    }
+	}
-    if (domain & RADEON_GEM_DOMAIN_CPU) {
+	if (domain & RADEON_GEM_DOMAIN_CPU) {
 		if (rbo->flags & RADEON_GEM_GTT_UC) {
 			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 		    rbo->rdev->flags & RADEON_IS_AGP) {
 			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 				TTM_PL_FLAG_UNCACHED |
 				TTM_PL_FLAG_SYSTEM;
-        } else {
+		} else {
 			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 						     TTM_PL_FLAG_SYSTEM;
-        }
+		}
-    }
+	}
 	if (!c) {
 		rbo->placements[c].fpfn = 0;
 		rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
 					     TTM_PL_FLAG_SYSTEM;
+	}
-    rbo->placement.num_placement = c;
+	rbo->placement.num_placement = c;
-    rbo->placement.num_busy_placement = c;
+	rbo->placement.num_busy_placement = c;
 	for (i = 0; i < c; ++i) {
 		if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 		    (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 		    !rbo->placements[i].fpfn)
 			rbo->placements[i].lpfn =
 				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 		else
-			rbo->placements[i].lpfn = 0;
-	}
-    /*
-     * Use two-ended allocation depending on the buffer size to
-     * improve fragmentation quality.
-     * 512kb was measured as the most optimal number.
-     */
-	if (rbo->tbo.mem.size > 512 * 1024) {
-        for (i = 0; i < c; i++) {
-			rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
 			rbo->placements[i].lpfn = 0;
+	}
+}
 int radeon_bo_create(struct radeon_device *rdev,
 		     unsigned long size, int byte_align, bool kernel,
 		     u32 domain, u32 flags, struct sg_table *sg,
 		     struct reservation_object *resv,
 		     struct radeon_bo **bo_ptr)
 {
-    struct radeon_bo *bo;
+	struct radeon_bo *bo;
 	enum ttm_bo_type type;
-    unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
+	unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
-    size_t acc_size;
+	size_t acc_size;
-    int r;
+	int r;
 	*bo_ptr = NULL;
 	acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 				       sizeof(struct radeon_bo));
-    bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
+	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
-    if (bo == NULL)
+	if (bo == NULL)
-            return -ENOMEM;
+		return -ENOMEM;
-    r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
+	r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
-    if (unlikely(r)) {
+	if (unlikely(r)) {
-            kfree(bo);
+		kfree(bo);
-            return r;
+		return r;
-    }
+	}
-    bo->rdev = rdev;
+	bo->rdev = rdev;
-    bo->surface_reg = -1;
+	bo->surface_reg = -1;
-    INIT_LIST_HEAD(&bo->list);
+	INIT_LIST_HEAD(&bo->list);
-    INIT_LIST_HEAD(&bo->va);
+	INIT_LIST_HEAD(&bo->va);
-    bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
+	bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
-                                   RADEON_GEM_DOMAIN_GTT |
+	                               RADEON_GEM_DOMAIN_GTT |
-                                   RADEON_GEM_DOMAIN_CPU);
+	                               RADEON_GEM_DOMAIN_CPU);
 	bo->flags = flags;
+	/* PCI GART is always snooped */
+	if (!(rdev->flags & RADEON_IS_PCIE))
+		bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
+	/* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
+	 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
-	/* PCI GART is always snooped */
+	 */
-	if (!(rdev->flags & RADEON_IS_PCIE))
+	if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
 		bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
+#ifdef CONFIG_X86_32
+	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
+	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
+	 */
+	bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
+#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
+	/* Don't try to enable write-combining when it can't work, or things
+	 * may be slow
+	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
+	 */
-#ifdef CONFIG_X86_32
+#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
+	 thanks to write-combining
-	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
+	if (bo->flags & RADEON_GEM_GTT_WC)
-	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
+		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
-	 */
+			      "better performance thanks to write-combining\n");
-	bo->flags &= ~RADEON_GEM_GTT_WC;
+	bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 #endif
-    radeon_ttm_placement_from_domain(bo, domain);
+	radeon_ttm_placement_from_domain(bo, domain);
 	if (tbo == NULL)
 		*bo = NULL;
+}
 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
-                 u64 *gpu_addr)
+			     u64 *gpu_addr)
 {
+	int r, i;
+	if (bo->pin_count) {
+		bo->pin_count++;
+		if (gpu_addr)
+			*gpu_addr = radeon_bo_gpu_offset(bo);
+		if (max_offset != 0) {
+			u64 domain_start;
+			if (domain == RADEON_GEM_DOMAIN_VRAM)
+				domain_start = bo->rdev->mc.vram_start;
+			else
+				domain_start = bo->rdev->mc.gtt_start;
+			WARN_ON_ONCE(max_offset <
+				     (radeon_bo_gpu_offset(bo) - domain_start));
-    int r, i;
-    if (bo->pin_count) {
-        bo->pin_count++;
-        if (gpu_addr)
-            *gpu_addr = radeon_bo_gpu_offset(bo);
-        if (max_offset != 0) {
-            u64 domain_start;
-            if (domain == RADEON_GEM_DOMAIN_VRAM)
-                domain_start = bo->rdev->mc.vram_start;
-            else
-                domain_start = bo->rdev->mc.gtt_start;
-            WARN_ON_ONCE(max_offset <
-                     (radeon_bo_gpu_offset(bo) - domain_start));
-        }
+		}
-        return 0;
+		return 0;
+	}
-    radeon_ttm_placement_from_domain(bo, domain);
+	radeon_ttm_placement_from_domain(bo, domain);
 	for (i = 0; i < bo->placement.num_placement; i++) {
-        /* force to pin into visible video ram */
+		/* force to pin into visible video ram */
 		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 		    !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 		    (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 			bo->placements[i].lpfn =
 				bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 		else
 			bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 		bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
-    }
+	}
 	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
-    if (likely(r == 0)) {
+	if (likely(r == 0)) {
-        bo->pin_count = 1;
+		bo->pin_count = 1;
-        if (gpu_addr != NULL)
+		if (gpu_addr != NULL)
-            *gpu_addr = radeon_bo_gpu_offset(bo);
+			*gpu_addr = radeon_bo_gpu_offset(bo);
 		if (domain == RADEON_GEM_DOMAIN_VRAM)
 			bo->rdev->vram_pin_size += radeon_bo_size(bo);
 		else
 			bo->rdev->gart_pin_size += radeon_bo_size(bo);
 	} else {
 		dev_err(bo->rdev->dev, "%p pin failed\n", bo);
+	}
-    return r;
+	return r;
+}
 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 {
-    return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
+	return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 }
 int radeon_bo_unpin(struct radeon_bo *bo)
 {
-    int r, i;
+	int r, i;
-    if (!bo->pin_count) {
+	if (!bo->pin_count) {
-            dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
+		dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
-            return 0;
+		return 0;
+	}
-    bo->pin_count--;
+	bo->pin_count--;
 	if (unlikely(r != 0))
 		return r;
 	if (mem_type)
 		*mem_type = bo->tbo.mem.mem_type;
-		r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
+	r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 	ttm_bo_unreserve(&bo->tbo);
 	return r;
+}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_object.c – Rev 5346 → 6104