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Rev 5346 Rev 6104
Line 170... Line 170...
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			rbo->placements[i].lpfn =
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			rbo->placements[i].lpfn =
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				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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		else
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		else
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			rbo->placements[i].lpfn = 0;
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			rbo->placements[i].lpfn = 0;
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	}
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	}
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-
 
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    /*
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     * Use two-ended allocation depending on the buffer size to
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     * improve fragmentation quality.
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     * 512kb was measured as the most optimal number.
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     */
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	if (rbo->tbo.mem.size > 512 * 1024) {
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        for (i = 0; i < c; i++) {
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			rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
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        }
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    }
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}
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}
Line 187... Line 176...
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176
 
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int radeon_bo_create(struct radeon_device *rdev,
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int radeon_bo_create(struct radeon_device *rdev,
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		     unsigned long size, int byte_align, bool kernel,
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		     unsigned long size, int byte_align, bool kernel,
Line 230... Line 219...
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	bo->flags = flags;
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	bo->flags = flags;
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	/* PCI GART is always snooped */
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	/* PCI GART is always snooped */
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	if (!(rdev->flags & RADEON_IS_PCIE))
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	if (!(rdev->flags & RADEON_IS_PCIE))
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		bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
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		bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
Line -... Line 223...
-
 
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	/* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
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	 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
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	 */
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	if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
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		bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
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229
 
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#ifdef CONFIG_X86_32
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#ifdef CONFIG_X86_32
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	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
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	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
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	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
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	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
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	 */
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	bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
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#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
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	/* Don't try to enable write-combining when it can't work, or things
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	 * may be slow
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	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
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	 */
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#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
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	 thanks to write-combining
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	 */
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	if (bo->flags & RADEON_GEM_GTT_WC)
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		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
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			      "better performance thanks to write-combining\n");
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	bo->flags &= ~RADEON_GEM_GTT_WC;
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	bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
Line 240... Line 248...
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#endif
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#endif
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249
 
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    radeon_ttm_placement_from_domain(bo, domain);
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	radeon_ttm_placement_from_domain(bo, domain);