Subversion Repositories Kolibri OS

Rev

Rev 1321 | Rev 1430 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 1321 Rev 1403
Line 44... Line 44...
44 
	struct drm_device *dev = encoder->dev;
 44 
	struct drm_device *dev = encoder->dev;
45 
	struct radeon_device *rdev = dev->dev_private;
 45 
	struct radeon_device *rdev = dev->dev_private;
46 
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 46 
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
47 
	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
 47 
	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
48 
	int panel_pwr_delay = 2000;
 48 
	int panel_pwr_delay = 2000;
- 
 
 49 
	bool is_mac = false;
49 
	DRM_DEBUG("\n");
 50 
	DRM_DEBUG("\n");
Line 50... Line 51...
50 
 
 51 
 
51 
	if (radeon_encoder->enc_priv) {
 52 
	if (radeon_encoder->enc_priv) {
52 
		if (rdev->is_atom_bios) {
 53 
		if (rdev->is_atom_bios) {
Line 56... Line 57...
56 
			struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 57 
			struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
57 
			panel_pwr_delay = lvds->panel_pwr_delay;
 58 
			panel_pwr_delay = lvds->panel_pwr_delay;
58 
		}
 59 
		}
59 
	}
 60 
	}
Line -... Line 61...
- 
 
 61 
 
- 
 
 62 
	/* macs (and possibly some x86 oem systems?) wire up LVDS strangely
- 
 
 63 
	 * Taken from radeonfb.
- 
 
 64 
	 */
- 
 
 65 
	if ((rdev->mode_info.connector_table == CT_IBOOK) ||
- 
 
 66 
	    (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
- 
 
 67 
	    (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
- 
 
 68 
	    (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
- 
 
 69 
		is_mac = true;
60 
 
 70 
 
61 
	switch (mode) {
 71 
	switch (mode) {
62 
	case DRM_MODE_DPMS_ON:
 72 
	case DRM_MODE_DPMS_ON:
63 
		disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
 73 
		disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
64 
		disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
 74 
		disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
Line 72... Line 82...
72 
		lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
 82 
		lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
73 
		WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 83 
		WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
Line 74... Line 84...
74 
 
 84 
 
75 
		lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 85 
		lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
- 
 
 86 
		lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
- 
 
 87 
		if (is_mac)
76 
		lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
 88 
			lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
77 
		lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
 89 
		lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
78 
		udelay(panel_pwr_delay * 1000);
 90 
		udelay(panel_pwr_delay * 1000);
79 
		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 91 
		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
80 
		break;
 92 
		break;
Line 83... Line 95...
83 
	case DRM_MODE_DPMS_OFF:
 95 
	case DRM_MODE_DPMS_OFF:
84 
		pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 96 
		pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
85 
		WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 97 
		WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
86 
		lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 98 
		lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
87 
		lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 99 
		lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- 
 
 100 
		if (is_mac) {
- 
 
 101 
			lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
- 
 
 102 
			WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
- 
 
 103 
			lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
- 
 
 104 
		} else {
- 
 
 105 
			WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
88 
		lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 106 
		lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
- 
 
 107 
		}
89 
		udelay(panel_pwr_delay * 1000);
 108 
		udelay(panel_pwr_delay * 1000);
90 
		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 109 
		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
91 
		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 110 
		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
92 
		break;
 111 
		break;
93 
	}
 112 
	}
Line 205... Line 224...
205 
		struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 224 
		struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
206 
		int mode_id = adjusted_mode->base.id;
 225 
		int mode_id = adjusted_mode->base.id;
207 
		*adjusted_mode = *native_mode;
 226 
		*adjusted_mode = *native_mode;
208 
		adjusted_mode->hdisplay = mode->hdisplay;
 227 
		adjusted_mode->hdisplay = mode->hdisplay;
209 
		adjusted_mode->vdisplay = mode->vdisplay;
 228 
		adjusted_mode->vdisplay = mode->vdisplay;
- 
 
 229 
		adjusted_mode->crtc_hdisplay = mode->hdisplay;
- 
 
 230 
		adjusted_mode->crtc_vdisplay = mode->vdisplay;
210 
		adjusted_mode->base.id = mode_id;
 231 
		adjusted_mode->base.id = mode_id;
211 
	}
 232 
	}
Line 212... Line 233...
212 
 
 233 
 
213 
	return true;
 234 
	return true;