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| Rev 3764 | Rev 5078 | ||
|---|---|---|---|
| Line 383... | Line 383... | ||
| 383 | uint32_t gen_cntl_reg, gen_cntl_val; |
383 | uint32_t gen_cntl_reg, gen_cntl_val; |
| 384 | int r; |
384 | int r; |
| Line 385... | Line 385... | ||
| 385 | 385 | ||
| 386 | DRM_DEBUG_KMS("\n"); |
386 | DRM_DEBUG_KMS("\n"); |
| 387 | /* no fb bound */ |
387 | /* no fb bound */ |
| 388 | if (!atomic && !crtc->fb) { |
388 | if (!atomic && !crtc->primary->fb) { |
| 389 | DRM_DEBUG_KMS("No FB bound\n"); |
389 | DRM_DEBUG_KMS("No FB bound\n"); |
| 390 | return 0; |
390 | return 0; |
| Line 391... | Line 391... | ||
| 391 | } |
391 | } |
| 392 | 392 | ||
| 393 | if (atomic) { |
393 | if (atomic) { |
| 394 | radeon_fb = to_radeon_framebuffer(fb); |
394 | radeon_fb = to_radeon_framebuffer(fb); |
| 395 | target_fb = fb; |
395 | target_fb = fb; |
| 396 | } |
396 | } |
| 397 | else { |
397 | else { |
| 398 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
398 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
| Line 399... | Line 399... | ||
| 399 | target_fb = crtc->fb; |
399 | target_fb = crtc->primary->fb; |
| 400 | } |
400 | } |
| 401 | 401 | ||
| Line 420... | Line 420... | ||
| 420 | } |
420 | } |
| Line 421... | Line 421... | ||
| 421 | 421 | ||
| 422 | /* Pin framebuffer & get tilling informations */ |
422 | /* Pin framebuffer & get tilling informations */ |
| 423 | obj = radeon_fb->obj; |
423 | obj = radeon_fb->obj; |
| - | 424 | rbo = gem_to_radeon_bo(obj); |
|
| 424 | rbo = gem_to_radeon_bo(obj); |
425 | retry: |
| 425 | r = radeon_bo_reserve(rbo, false); |
426 | r = radeon_bo_reserve(rbo, false); |
| 426 | if (unlikely(r != 0)) |
427 | if (unlikely(r != 0)) |
| 427 | return r; |
428 | return r; |
| 428 | /* Only 27 bit offset for legacy CRTC */ |
429 | /* Only 27 bit offset for legacy CRTC */ |
| 429 | r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, |
430 | r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, |
| 430 | &base); |
431 | &base); |
| 431 | if (unlikely(r != 0)) { |
432 | if (unlikely(r != 0)) { |
| - | 433 | radeon_bo_unreserve(rbo); |
|
| - | 434 | ||
| - | 435 | /* On old GPU like RN50 with little vram pining can fails because |
|
| - | 436 | * current fb is taking all space needed. So instead of unpining |
|
| - | 437 | * the old buffer after pining the new one, first unpin old one |
|
| - | 438 | * and then retry pining new one. |
|
| - | 439 | * |
|
| - | 440 | * As only master can set mode only master can pin and it is |
|
| - | 441 | * unlikely the master client will race with itself especialy |
|
| - | 442 | * on those old gpu with single crtc. |
|
| - | 443 | * |
|
| - | 444 | * We don't shutdown the display controller because new buffer |
|
| - | 445 | * will end up in same spot. |
|
| - | 446 | */ |
|
| - | 447 | if (!atomic && fb && fb != crtc->primary->fb) { |
|
| - | 448 | struct radeon_bo *old_rbo; |
|
| - | 449 | unsigned long nsize, osize; |
|
| - | 450 | ||
| - | 451 | old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj); |
|
| - | 452 | osize = radeon_bo_size(old_rbo); |
|
| - | 453 | nsize = radeon_bo_size(rbo); |
|
| - | 454 | if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) { |
|
| - | 455 | radeon_bo_unpin(old_rbo); |
|
| - | 456 | radeon_bo_unreserve(old_rbo); |
|
| - | 457 | fb = NULL; |
|
| - | 458 | goto retry; |
|
| - | 459 | } |
|
| 432 | radeon_bo_unreserve(rbo); |
460 | } |
| 433 | return -EINVAL; |
461 | return -EINVAL; |
| 434 | } |
462 | } |
| 435 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
463 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 436 | radeon_bo_unreserve(rbo); |
464 | radeon_bo_unreserve(rbo); |
| Line 525... | Line 553... | ||
| 525 | } |
553 | } |
| 526 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
554 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
| 527 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
555 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
| 528 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
556 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
| Line 529... | Line 557... | ||
| 529 | 557 | ||
| 530 | if (!atomic && fb && fb != crtc->fb) { |
558 | if (!atomic && fb && fb != crtc->primary->fb) { |
| 531 | radeon_fb = to_radeon_framebuffer(fb); |
559 | radeon_fb = to_radeon_framebuffer(fb); |
| 532 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
560 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
| 533 | r = radeon_bo_reserve(rbo, false); |
561 | r = radeon_bo_reserve(rbo, false); |
| 534 | if (unlikely(r != 0)) |
562 | if (unlikely(r != 0)) |
| Line 569... | Line 597... | ||
| 569 | break; |
597 | break; |
| 570 | } |
598 | } |
| 571 | } |
599 | } |
| 572 | } |
600 | } |
| Line 573... | Line 601... | ||
| 573 | 601 | ||
| 574 | switch (crtc->fb->bits_per_pixel) { |
602 | switch (crtc->primary->fb->bits_per_pixel) { |
| 575 | case 8: |
603 | case 8: |
| 576 | format = 2; |
604 | format = 2; |
| 577 | break; |
605 | break; |
| 578 | case 15: /* 555 */ |
606 | case 15: /* 555 */ |
| Line 1054... | Line 1082... | ||
| 1054 | if (crtci->enabled) |
1082 | if (crtci->enabled) |
| 1055 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); |
1083 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); |
| 1056 | } |
1084 | } |
| 1057 | } |
1085 | } |
| Line -... | Line 1086... | ||
| - | 1086 | ||
| - | 1087 | static void radeon_crtc_disable(struct drm_crtc *crtc) |
|
| - | 1088 | { |
|
| - | 1089 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
|
| - | 1090 | if (crtc->primary->fb) { |
|
| - | 1091 | int r; |
|
| - | 1092 | struct radeon_framebuffer *radeon_fb; |
|
| - | 1093 | struct radeon_bo *rbo; |
|
| - | 1094 | ||
| - | 1095 | radeon_fb = to_radeon_framebuffer(crtc->primary->fb); |
|
| - | 1096 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
|
| - | 1097 | r = radeon_bo_reserve(rbo, false); |
|
| - | 1098 | if (unlikely(r)) |
|
| - | 1099 | DRM_ERROR("failed to reserve rbo before unpin\n"); |
|
| - | 1100 | else { |
|
| - | 1101 | radeon_bo_unpin(rbo); |
|
| - | 1102 | radeon_bo_unreserve(rbo); |
|
| - | 1103 | } |
|
| - | 1104 | } |
|
| - | 1105 | } |
|
| 1058 | 1106 | ||
| 1059 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
1107 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
| 1060 | .dpms = radeon_crtc_dpms, |
1108 | .dpms = radeon_crtc_dpms, |
| 1061 | .mode_fixup = radeon_crtc_mode_fixup, |
1109 | .mode_fixup = radeon_crtc_mode_fixup, |
| 1062 | .mode_set = radeon_crtc_mode_set, |
1110 | .mode_set = radeon_crtc_mode_set, |
| 1063 | .mode_set_base = radeon_crtc_set_base, |
1111 | .mode_set_base = radeon_crtc_set_base, |
| 1064 | .mode_set_base_atomic = radeon_crtc_set_base_atomic, |
1112 | .mode_set_base_atomic = radeon_crtc_set_base_atomic, |
| 1065 | .prepare = radeon_crtc_prepare, |
1113 | .prepare = radeon_crtc_prepare, |
| 1066 | .commit = radeon_crtc_commit, |
1114 | .commit = radeon_crtc_commit, |
| - | 1115 | .load_lut = radeon_crtc_load_lut, |
|
| 1067 | .load_lut = radeon_crtc_load_lut, |
1116 | .disable = radeon_crtc_disable |
| Line 1068... | Line 1117... | ||
| 1068 | }; |
1117 | }; |
| 1069 | 1118 | ||