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Rev 2997 Rev 3120
Line 293... Line 293...
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static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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{
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	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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	struct drm_device *dev = crtc->dev;
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	struct drm_device *dev = crtc->dev;
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	struct radeon_device *rdev = dev->dev_private;
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	struct radeon_device *rdev = dev->dev_private;
-
 
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	uint32_t crtc_ext_cntl = 0;
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	uint32_t mask;
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	uint32_t mask;
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	if (radeon_crtc->crtc_id)
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	if (radeon_crtc->crtc_id)
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		mask = (RADEON_CRTC2_DISP_DIS |
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		mask = (RADEON_CRTC2_DISP_DIS |
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	else
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	else
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		mask = (RADEON_CRTC_DISPLAY_DIS |
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		mask = (RADEON_CRTC_DISPLAY_DIS |
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			RADEON_CRTC_VSYNC_DIS |
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			RADEON_CRTC_VSYNC_DIS |
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			RADEON_CRTC_HSYNC_DIS);
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			RADEON_CRTC_HSYNC_DIS);
Line -... Line 310...
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	/*
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	 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
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	 * Therefore it is set in the DAC DMPS function.
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	 * This is different for GPU's with a single CRTC but a primary and a
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	 * TV DAC: here it controls the single CRTC no matter where it is
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	 * routed. Therefore we set it here.
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	 */
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	if (rdev->flags & RADEON_SINGLE_CRTC)
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		crtc_ext_cntl = RADEON_CRTC_CRT_ON;
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	switch (mode) {
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	switch (mode) {
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	case DRM_MODE_DPMS_ON:
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	case DRM_MODE_DPMS_ON:
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		radeon_crtc->enabled = true;
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		radeon_crtc->enabled = true;
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		/* adjust pm to dpms changes BEFORE enabling crtcs */
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		/* adjust pm to dpms changes BEFORE enabling crtcs */
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		radeon_pm_compute_clocks(rdev);
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		radeon_pm_compute_clocks(rdev);
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		if (radeon_crtc->crtc_id)
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		if (radeon_crtc->crtc_id)
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			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
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			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
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		else {
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		else {
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			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
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			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
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									 RADEON_CRTC_DISP_REQ_EN_B));
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									 RADEON_CRTC_DISP_REQ_EN_B));
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			WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
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			WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
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		}
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		}
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		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
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		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
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		radeon_crtc_load_lut(crtc);
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		radeon_crtc_load_lut(crtc);
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		break;
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		break;
Line 329... Line 340...
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		if (radeon_crtc->crtc_id)
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		if (radeon_crtc->crtc_id)
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			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
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			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
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		else {
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		else {
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			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
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			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
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										    RADEON_CRTC_DISP_REQ_EN_B));
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										    RADEON_CRTC_DISP_REQ_EN_B));
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			WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
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			WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
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		}
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		}
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		radeon_crtc->enabled = false;
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		radeon_crtc->enabled = false;
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		/* adjust pm to dpms changes AFTER disabling crtcs */
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		/* adjust pm to dpms changes AFTER disabling crtcs */
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		radeon_pm_compute_clocks(rdev);
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		radeon_pm_compute_clocks(rdev);
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		break;
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		break;