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Rev 2997 | Rev 3120 | ||
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Line 293... | Line 293... | ||
293 | static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
293 | static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
294 | { |
294 | { |
295 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
295 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
296 | struct drm_device *dev = crtc->dev; |
296 | struct drm_device *dev = crtc->dev; |
297 | struct radeon_device *rdev = dev->dev_private; |
297 | struct radeon_device *rdev = dev->dev_private; |
- | 298 | uint32_t crtc_ext_cntl = 0; |
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298 | uint32_t mask; |
299 | uint32_t mask; |
Line 299... | Line 300... | ||
299 | 300 | ||
300 | if (radeon_crtc->crtc_id) |
301 | if (radeon_crtc->crtc_id) |
301 | mask = (RADEON_CRTC2_DISP_DIS | |
302 | mask = (RADEON_CRTC2_DISP_DIS | |
Line 305... | Line 306... | ||
305 | else |
306 | else |
306 | mask = (RADEON_CRTC_DISPLAY_DIS | |
307 | mask = (RADEON_CRTC_DISPLAY_DIS | |
307 | RADEON_CRTC_VSYNC_DIS | |
308 | RADEON_CRTC_VSYNC_DIS | |
308 | RADEON_CRTC_HSYNC_DIS); |
309 | RADEON_CRTC_HSYNC_DIS); |
Line -... | Line 310... | ||
- | 310 | ||
- | 311 | /* |
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- | 312 | * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. |
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- | 313 | * Therefore it is set in the DAC DMPS function. |
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- | 314 | * This is different for GPU's with a single CRTC but a primary and a |
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- | 315 | * TV DAC: here it controls the single CRTC no matter where it is |
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- | 316 | * routed. Therefore we set it here. |
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- | 317 | */ |
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- | 318 | if (rdev->flags & RADEON_SINGLE_CRTC) |
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- | 319 | crtc_ext_cntl = RADEON_CRTC_CRT_ON; |
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309 | 320 | ||
310 | switch (mode) { |
321 | switch (mode) { |
311 | case DRM_MODE_DPMS_ON: |
322 | case DRM_MODE_DPMS_ON: |
312 | radeon_crtc->enabled = true; |
323 | radeon_crtc->enabled = true; |
313 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
324 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
314 | radeon_pm_compute_clocks(rdev); |
325 | radeon_pm_compute_clocks(rdev); |
315 | if (radeon_crtc->crtc_id) |
326 | if (radeon_crtc->crtc_id) |
316 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); |
327 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); |
317 | else { |
328 | else { |
318 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
329 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
319 | RADEON_CRTC_DISP_REQ_EN_B)); |
330 | RADEON_CRTC_DISP_REQ_EN_B)); |
320 | WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); |
331 | WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); |
321 | } |
332 | } |
322 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
333 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
323 | radeon_crtc_load_lut(crtc); |
334 | radeon_crtc_load_lut(crtc); |
324 | break; |
335 | break; |
Line 329... | Line 340... | ||
329 | if (radeon_crtc->crtc_id) |
340 | if (radeon_crtc->crtc_id) |
330 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); |
341 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); |
331 | else { |
342 | else { |
332 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
343 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
333 | RADEON_CRTC_DISP_REQ_EN_B)); |
344 | RADEON_CRTC_DISP_REQ_EN_B)); |
334 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); |
345 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); |
335 | } |
346 | } |
336 | radeon_crtc->enabled = false; |
347 | radeon_crtc->enabled = false; |
337 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
348 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
338 | radeon_pm_compute_clocks(rdev); |
349 | radeon_pm_compute_clocks(rdev); |
339 | break; |
350 | break; |