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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include |
26 | #include |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include "radeon_fixed.h" |
29 | #include "radeon_fixed.h" |
30 | #include "radeon.h" |
30 | #include "radeon.h" |
31 | #include "atom.h" |
31 | #include "atom.h" |
32 | 32 | ||
33 | static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, |
33 | static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, |
34 | struct drm_display_mode *mode, |
34 | struct drm_display_mode *mode, |
35 | struct drm_display_mode *adjusted_mode) |
35 | struct drm_display_mode *adjusted_mode) |
36 | { |
36 | { |
37 | struct drm_device *dev = crtc->dev; |
37 | struct drm_device *dev = crtc->dev; |
38 | struct radeon_device *rdev = dev->dev_private; |
38 | struct radeon_device *rdev = dev->dev_private; |
39 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
39 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
40 | int xres = mode->hdisplay; |
40 | int xres = mode->hdisplay; |
41 | int yres = mode->vdisplay; |
41 | int yres = mode->vdisplay; |
42 | bool hscale = true, vscale = true; |
42 | bool hscale = true, vscale = true; |
43 | int hsync_wid; |
43 | int hsync_wid; |
44 | int vsync_wid; |
44 | int vsync_wid; |
45 | int hsync_start; |
45 | int hsync_start; |
46 | int blank_width; |
46 | int blank_width; |
47 | u32 scale, inc, crtc_more_cntl; |
47 | u32 scale, inc, crtc_more_cntl; |
48 | u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; |
48 | u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; |
49 | u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; |
49 | u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; |
50 | u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; |
50 | u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; |
51 | struct drm_display_mode *native_mode = &radeon_crtc->native_mode; |
51 | struct drm_display_mode *native_mode = &radeon_crtc->native_mode; |
52 | 52 | ||
53 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & |
53 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & |
54 | (RADEON_VERT_STRETCH_RESERVED | |
54 | (RADEON_VERT_STRETCH_RESERVED | |
55 | RADEON_VERT_AUTO_RATIO_INC); |
55 | RADEON_VERT_AUTO_RATIO_INC); |
56 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & |
56 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & |
57 | (RADEON_HORZ_FP_LOOP_STRETCH | |
57 | (RADEON_HORZ_FP_LOOP_STRETCH | |
58 | RADEON_HORZ_AUTO_RATIO_INC); |
58 | RADEON_HORZ_AUTO_RATIO_INC); |
59 | 59 | ||
60 | crtc_more_cntl = 0; |
60 | crtc_more_cntl = 0; |
61 | if ((rdev->family == CHIP_RS100) || |
61 | if ((rdev->family == CHIP_RS100) || |
62 | (rdev->family == CHIP_RS200)) { |
62 | (rdev->family == CHIP_RS200)) { |
63 | /* This is to workaround the asic bug for RMX, some versions |
63 | /* This is to workaround the asic bug for RMX, some versions |
64 | of BIOS dosen't have this register initialized correctly. */ |
64 | of BIOS dosen't have this register initialized correctly. */ |
65 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; |
65 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; |
66 | } |
66 | } |
67 | 67 | ||
68 | 68 | ||
69 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
69 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
70 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
70 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
71 | 71 | ||
72 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
72 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
73 | if (!hsync_wid) |
73 | if (!hsync_wid) |
74 | hsync_wid = 1; |
74 | hsync_wid = 1; |
75 | hsync_start = mode->crtc_hsync_start - 8; |
75 | hsync_start = mode->crtc_hsync_start - 8; |
76 | 76 | ||
77 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) |
77 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) |
78 | | ((hsync_wid & 0x3f) << 16) |
78 | | ((hsync_wid & 0x3f) << 16) |
79 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
79 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
80 | ? RADEON_CRTC_H_SYNC_POL |
80 | ? RADEON_CRTC_H_SYNC_POL |
81 | : 0)); |
81 | : 0)); |
82 | 82 | ||
83 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
83 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
84 | | ((mode->crtc_vdisplay - 1) << 16)); |
84 | | ((mode->crtc_vdisplay - 1) << 16)); |
85 | 85 | ||
86 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
86 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
87 | if (!vsync_wid) |
87 | if (!vsync_wid) |
88 | vsync_wid = 1; |
88 | vsync_wid = 1; |
89 | 89 | ||
90 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
90 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
91 | | ((vsync_wid & 0x1f) << 16) |
91 | | ((vsync_wid & 0x1f) << 16) |
92 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
92 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
93 | ? RADEON_CRTC_V_SYNC_POL |
93 | ? RADEON_CRTC_V_SYNC_POL |
94 | : 0)); |
94 | : 0)); |
95 | 95 | ||
96 | fp_horz_vert_active = 0; |
96 | fp_horz_vert_active = 0; |
97 | 97 | ||
98 | if (native_mode->hdisplay == 0 || |
98 | if (native_mode->hdisplay == 0 || |
99 | native_mode->vdisplay == 0) { |
99 | native_mode->vdisplay == 0) { |
100 | hscale = false; |
100 | hscale = false; |
101 | vscale = false; |
101 | vscale = false; |
102 | } else { |
102 | } else { |
103 | if (xres > native_mode->hdisplay) |
103 | if (xres > native_mode->hdisplay) |
104 | xres = native_mode->hdisplay; |
104 | xres = native_mode->hdisplay; |
105 | if (yres > native_mode->vdisplay) |
105 | if (yres > native_mode->vdisplay) |
106 | yres = native_mode->vdisplay; |
106 | yres = native_mode->vdisplay; |
107 | 107 | ||
108 | if (xres == native_mode->hdisplay) |
108 | if (xres == native_mode->hdisplay) |
109 | hscale = false; |
109 | hscale = false; |
110 | if (yres == native_mode->vdisplay) |
110 | if (yres == native_mode->vdisplay) |
111 | vscale = false; |
111 | vscale = false; |
112 | } |
112 | } |
113 | 113 | ||
114 | switch (radeon_crtc->rmx_type) { |
114 | switch (radeon_crtc->rmx_type) { |
115 | case RMX_FULL: |
115 | case RMX_FULL: |
116 | case RMX_ASPECT: |
116 | case RMX_ASPECT: |
117 | if (!hscale) |
117 | if (!hscale) |
118 | fp_horz_stretch |= ((xres/8-1) << 16); |
118 | fp_horz_stretch |= ((xres/8-1) << 16); |
119 | else { |
119 | else { |
120 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; |
120 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; |
121 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) |
121 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) |
122 | / native_mode->hdisplay + 1; |
122 | / native_mode->hdisplay + 1; |
123 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | |
123 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | |
124 | RADEON_HORZ_STRETCH_BLEND | |
124 | RADEON_HORZ_STRETCH_BLEND | |
125 | RADEON_HORZ_STRETCH_ENABLE | |
125 | RADEON_HORZ_STRETCH_ENABLE | |
126 | ((native_mode->hdisplay/8-1) << 16)); |
126 | ((native_mode->hdisplay/8-1) << 16)); |
127 | } |
127 | } |
128 | 128 | ||
129 | if (!vscale) |
129 | if (!vscale) |
130 | fp_vert_stretch |= ((yres-1) << 12); |
130 | fp_vert_stretch |= ((yres-1) << 12); |
131 | else { |
131 | else { |
132 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; |
132 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; |
133 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) |
133 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) |
134 | / native_mode->vdisplay + 1; |
134 | / native_mode->vdisplay + 1; |
135 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | |
135 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | |
136 | RADEON_VERT_STRETCH_ENABLE | |
136 | RADEON_VERT_STRETCH_ENABLE | |
137 | RADEON_VERT_STRETCH_BLEND | |
137 | RADEON_VERT_STRETCH_BLEND | |
138 | ((native_mode->vdisplay-1) << 12)); |
138 | ((native_mode->vdisplay-1) << 12)); |
139 | } |
139 | } |
140 | break; |
140 | break; |
141 | case RMX_CENTER: |
141 | case RMX_CENTER: |
142 | fp_horz_stretch |= ((xres/8-1) << 16); |
142 | fp_horz_stretch |= ((xres/8-1) << 16); |
143 | fp_vert_stretch |= ((yres-1) << 12); |
143 | fp_vert_stretch |= ((yres-1) << 12); |
144 | 144 | ||
145 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | |
145 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | |
146 | RADEON_CRTC_AUTO_VERT_CENTER_EN); |
146 | RADEON_CRTC_AUTO_VERT_CENTER_EN); |
147 | 147 | ||
148 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; |
148 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; |
149 | if (blank_width > 110) |
149 | if (blank_width > 110) |
150 | blank_width = 110; |
150 | blank_width = 110; |
151 | 151 | ||
152 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) |
152 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) |
153 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
153 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
154 | 154 | ||
155 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
155 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
156 | if (!hsync_wid) |
156 | if (!hsync_wid) |
157 | hsync_wid = 1; |
157 | hsync_wid = 1; |
158 | 158 | ||
159 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) |
159 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) |
160 | | ((hsync_wid & 0x3f) << 16) |
160 | | ((hsync_wid & 0x3f) << 16) |
161 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
161 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
162 | ? RADEON_CRTC_H_SYNC_POL |
162 | ? RADEON_CRTC_H_SYNC_POL |
163 | : 0)); |
163 | : 0)); |
164 | 164 | ||
165 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) |
165 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) |
166 | | ((mode->crtc_vdisplay - 1) << 16)); |
166 | | ((mode->crtc_vdisplay - 1) << 16)); |
167 | 167 | ||
168 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
168 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
169 | if (!vsync_wid) |
169 | if (!vsync_wid) |
170 | vsync_wid = 1; |
170 | vsync_wid = 1; |
171 | 171 | ||
172 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) |
172 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) |
173 | | ((vsync_wid & 0x1f) << 16) |
173 | | ((vsync_wid & 0x1f) << 16) |
174 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
174 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
175 | ? RADEON_CRTC_V_SYNC_POL |
175 | ? RADEON_CRTC_V_SYNC_POL |
176 | : 0))); |
176 | : 0))); |
177 | 177 | ||
178 | fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | |
178 | fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | |
179 | (((native_mode->hdisplay / 8) & 0x1ff) << 16)); |
179 | (((native_mode->hdisplay / 8) & 0x1ff) << 16)); |
180 | break; |
180 | break; |
181 | case RMX_OFF: |
181 | case RMX_OFF: |
182 | default: |
182 | default: |
183 | fp_horz_stretch |= ((xres/8-1) << 16); |
183 | fp_horz_stretch |= ((xres/8-1) << 16); |
184 | fp_vert_stretch |= ((yres-1) << 12); |
184 | fp_vert_stretch |= ((yres-1) << 12); |
185 | break; |
185 | break; |
186 | } |
186 | } |
187 | 187 | ||
188 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); |
188 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); |
189 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); |
189 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); |
190 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); |
190 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); |
191 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); |
191 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); |
192 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); |
192 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); |
193 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); |
193 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); |
194 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); |
194 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); |
195 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); |
195 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); |
196 | } |
196 | } |
197 | 197 | ||
198 | void radeon_restore_common_regs(struct drm_device *dev) |
198 | void radeon_restore_common_regs(struct drm_device *dev) |
199 | { |
199 | { |
200 | /* don't need this yet */ |
200 | /* don't need this yet */ |
201 | } |
201 | } |
202 | 202 | ||
203 | static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) |
203 | static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) |
204 | { |
204 | { |
205 | struct radeon_device *rdev = dev->dev_private; |
205 | struct radeon_device *rdev = dev->dev_private; |
206 | int i = 0; |
206 | int i = 0; |
207 | 207 | ||
208 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
208 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
209 | the cause yet, but this workaround will mask the problem for now. |
209 | the cause yet, but this workaround will mask the problem for now. |
210 | Other chips usually will pass at the very first test, so the |
210 | Other chips usually will pass at the very first test, so the |
211 | workaround shouldn't have any effect on them. */ |
211 | workaround shouldn't have any effect on them. */ |
212 | for (i = 0; |
212 | for (i = 0; |
213 | (i < 10000 && |
213 | (i < 10000 && |
214 | RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
214 | RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
215 | i++); |
215 | i++); |
216 | } |
216 | } |
217 | 217 | ||
218 | static void radeon_pll_write_update(struct drm_device *dev) |
218 | static void radeon_pll_write_update(struct drm_device *dev) |
219 | { |
219 | { |
220 | struct radeon_device *rdev = dev->dev_private; |
220 | struct radeon_device *rdev = dev->dev_private; |
221 | 221 | ||
222 | while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
222 | while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
223 | 223 | ||
224 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
224 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
225 | RADEON_PPLL_ATOMIC_UPDATE_W, |
225 | RADEON_PPLL_ATOMIC_UPDATE_W, |
226 | ~(RADEON_PPLL_ATOMIC_UPDATE_W)); |
226 | ~(RADEON_PPLL_ATOMIC_UPDATE_W)); |
227 | } |
227 | } |
228 | 228 | ||
229 | static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) |
229 | static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) |
230 | { |
230 | { |
231 | struct radeon_device *rdev = dev->dev_private; |
231 | struct radeon_device *rdev = dev->dev_private; |
232 | int i = 0; |
232 | int i = 0; |
233 | 233 | ||
234 | 234 | ||
235 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
235 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
236 | the cause yet, but this workaround will mask the problem for now. |
236 | the cause yet, but this workaround will mask the problem for now. |
237 | Other chips usually will pass at the very first test, so the |
237 | Other chips usually will pass at the very first test, so the |
238 | workaround shouldn't have any effect on them. */ |
238 | workaround shouldn't have any effect on them. */ |
239 | for (i = 0; |
239 | for (i = 0; |
240 | (i < 10000 && |
240 | (i < 10000 && |
241 | RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
241 | RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
242 | i++); |
242 | i++); |
243 | } |
243 | } |
244 | 244 | ||
245 | static void radeon_pll2_write_update(struct drm_device *dev) |
245 | static void radeon_pll2_write_update(struct drm_device *dev) |
246 | { |
246 | { |
247 | struct radeon_device *rdev = dev->dev_private; |
247 | struct radeon_device *rdev = dev->dev_private; |
248 | 248 | ||
249 | while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
249 | while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
250 | 250 | ||
251 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
251 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
252 | RADEON_P2PLL_ATOMIC_UPDATE_W, |
252 | RADEON_P2PLL_ATOMIC_UPDATE_W, |
253 | ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); |
253 | ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); |
254 | } |
254 | } |
255 | 255 | ||
256 | static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, |
256 | static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, |
257 | uint16_t fb_div) |
257 | uint16_t fb_div) |
258 | { |
258 | { |
259 | unsigned int vcoFreq; |
259 | unsigned int vcoFreq; |
260 | 260 | ||
261 | if (!ref_div) |
261 | if (!ref_div) |
262 | return 1; |
262 | return 1; |
263 | 263 | ||
264 | vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div; |
264 | vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div; |
265 | 265 | ||
266 | /* |
266 | /* |
267 | * This is horribly crude: the VCO frequency range is divided into |
267 | * This is horribly crude: the VCO frequency range is divided into |
268 | * 3 parts, each part having a fixed PLL gain value. |
268 | * 3 parts, each part having a fixed PLL gain value. |
269 | */ |
269 | */ |
270 | if (vcoFreq >= 30000) |
270 | if (vcoFreq >= 30000) |
271 | /* |
271 | /* |
272 | * [300..max] MHz : 7 |
272 | * [300..max] MHz : 7 |
273 | */ |
273 | */ |
274 | return 7; |
274 | return 7; |
275 | else if (vcoFreq >= 18000) |
275 | else if (vcoFreq >= 18000) |
276 | /* |
276 | /* |
277 | * [180..300) MHz : 4 |
277 | * [180..300) MHz : 4 |
278 | */ |
278 | */ |
279 | return 4; |
279 | return 4; |
280 | else |
280 | else |
281 | /* |
281 | /* |
282 | * [0..180) MHz : 1 |
282 | * [0..180) MHz : 1 |
283 | */ |
283 | */ |
284 | return 1; |
284 | return 1; |
285 | } |
285 | } |
286 | 286 | ||
287 | void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
287 | void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
288 | { |
288 | { |
289 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
289 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
290 | struct drm_device *dev = crtc->dev; |
290 | struct drm_device *dev = crtc->dev; |
291 | struct radeon_device *rdev = dev->dev_private; |
291 | struct radeon_device *rdev = dev->dev_private; |
292 | uint32_t mask; |
292 | uint32_t mask; |
293 | 293 | ||
294 | if (radeon_crtc->crtc_id) |
294 | if (radeon_crtc->crtc_id) |
295 | mask = (RADEON_CRTC2_EN | |
295 | mask = (RADEON_CRTC2_EN | |
296 | RADEON_CRTC2_DISP_DIS | |
296 | RADEON_CRTC2_DISP_DIS | |
297 | RADEON_CRTC2_VSYNC_DIS | |
297 | RADEON_CRTC2_VSYNC_DIS | |
298 | RADEON_CRTC2_HSYNC_DIS | |
298 | RADEON_CRTC2_HSYNC_DIS | |
299 | RADEON_CRTC2_DISP_REQ_EN_B); |
299 | RADEON_CRTC2_DISP_REQ_EN_B); |
300 | else |
300 | else |
301 | mask = (RADEON_CRTC_DISPLAY_DIS | |
301 | mask = (RADEON_CRTC_DISPLAY_DIS | |
302 | RADEON_CRTC_VSYNC_DIS | |
302 | RADEON_CRTC_VSYNC_DIS | |
303 | RADEON_CRTC_HSYNC_DIS); |
303 | RADEON_CRTC_HSYNC_DIS); |
304 | 304 | ||
305 | switch (mode) { |
305 | switch (mode) { |
306 | case DRM_MODE_DPMS_ON: |
306 | case DRM_MODE_DPMS_ON: |
307 | if (radeon_crtc->crtc_id) |
307 | if (radeon_crtc->crtc_id) |
308 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask); |
308 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask); |
309 | else { |
309 | else { |
310 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
310 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
311 | RADEON_CRTC_DISP_REQ_EN_B)); |
311 | RADEON_CRTC_DISP_REQ_EN_B)); |
312 | WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); |
312 | WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); |
313 | } |
313 | } |
314 | // drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
314 | // drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
315 | radeon_crtc_load_lut(crtc); |
315 | radeon_crtc_load_lut(crtc); |
316 | break; |
316 | break; |
317 | case DRM_MODE_DPMS_STANDBY: |
317 | case DRM_MODE_DPMS_STANDBY: |
318 | case DRM_MODE_DPMS_SUSPEND: |
318 | case DRM_MODE_DPMS_SUSPEND: |
319 | case DRM_MODE_DPMS_OFF: |
319 | case DRM_MODE_DPMS_OFF: |
320 | // drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
320 | // drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
321 | if (radeon_crtc->crtc_id) |
321 | if (radeon_crtc->crtc_id) |
322 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask); |
322 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask); |
323 | else { |
323 | else { |
324 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
324 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
325 | RADEON_CRTC_DISP_REQ_EN_B)); |
325 | RADEON_CRTC_DISP_REQ_EN_B)); |
326 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); |
326 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); |
327 | } |
327 | } |
328 | break; |
328 | break; |
329 | } |
329 | } |
330 | } |
330 | } |
331 | 331 | ||
332 | /* properly set crtc bpp when using atombios */ |
332 | /* properly set crtc bpp when using atombios */ |
333 | void radeon_legacy_atom_set_surface(struct drm_crtc *crtc) |
333 | void radeon_legacy_atom_set_surface(struct drm_crtc *crtc) |
334 | { |
334 | { |
335 | struct drm_device *dev = crtc->dev; |
335 | struct drm_device *dev = crtc->dev; |
336 | struct radeon_device *rdev = dev->dev_private; |
336 | struct radeon_device *rdev = dev->dev_private; |
337 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
337 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
338 | int format; |
338 | int format; |
339 | uint32_t crtc_gen_cntl; |
339 | uint32_t crtc_gen_cntl; |
340 | uint32_t disp_merge_cntl; |
340 | uint32_t disp_merge_cntl; |
341 | uint32_t crtc_pitch; |
341 | uint32_t crtc_pitch; |
342 | 342 | ||
343 | switch (crtc->fb->bits_per_pixel) { |
343 | switch (crtc->fb->bits_per_pixel) { |
344 | case 8: |
344 | case 8: |
345 | format = 2; |
345 | format = 2; |
346 | break; |
346 | break; |
347 | case 15: /* 555 */ |
347 | case 15: /* 555 */ |
348 | format = 3; |
348 | format = 3; |
349 | break; |
349 | break; |
350 | case 16: /* 565 */ |
350 | case 16: /* 565 */ |
351 | format = 4; |
351 | format = 4; |
352 | break; |
352 | break; |
353 | case 24: /* RGB */ |
353 | case 24: /* RGB */ |
354 | format = 5; |
354 | format = 5; |
355 | break; |
355 | break; |
356 | case 32: /* xRGB */ |
356 | case 32: /* xRGB */ |
357 | format = 6; |
357 | format = 6; |
358 | break; |
358 | break; |
359 | default: |
359 | default: |
360 | return; |
360 | return; |
361 | } |
361 | } |
362 | 362 | ||
363 | crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) + |
363 | crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) + |
364 | ((crtc->fb->bits_per_pixel * 8) - 1)) / |
364 | ((crtc->fb->bits_per_pixel * 8) - 1)) / |
365 | (crtc->fb->bits_per_pixel * 8)); |
365 | (crtc->fb->bits_per_pixel * 8)); |
366 | crtc_pitch |= crtc_pitch << 16; |
366 | crtc_pitch |= crtc_pitch << 16; |
367 | 367 | ||
368 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
368 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
369 | 369 | ||
370 | switch (radeon_crtc->crtc_id) { |
370 | switch (radeon_crtc->crtc_id) { |
371 | case 0: |
371 | case 0: |
372 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
372 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
373 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
373 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
374 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
374 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
375 | 375 | ||
376 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff; |
376 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff; |
377 | crtc_gen_cntl |= (format << 8); |
377 | crtc_gen_cntl |= (format << 8); |
378 | crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN; |
378 | crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN; |
379 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
379 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
380 | break; |
380 | break; |
381 | case 1: |
381 | case 1: |
382 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
382 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
383 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
383 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
384 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
384 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
385 | 385 | ||
386 | crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff; |
386 | crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff; |
387 | crtc_gen_cntl |= (format << 8); |
387 | crtc_gen_cntl |= (format << 8); |
388 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl); |
388 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl); |
389 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
389 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
390 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
390 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
391 | break; |
391 | break; |
392 | } |
392 | } |
393 | } |
393 | } |
394 | 394 | ||
395 | int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
395 | int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
396 | struct drm_framebuffer *old_fb) |
396 | struct drm_framebuffer *old_fb) |
397 | { |
397 | { |
398 | struct drm_device *dev = crtc->dev; |
398 | struct drm_device *dev = crtc->dev; |
399 | struct radeon_device *rdev = dev->dev_private; |
399 | struct radeon_device *rdev = dev->dev_private; |
400 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
400 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
401 | struct radeon_framebuffer *radeon_fb; |
401 | struct radeon_framebuffer *radeon_fb; |
402 | struct drm_gem_object *obj; |
402 | struct drm_gem_object *obj; |
403 | uint64_t base; |
403 | uint64_t base; |
404 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
404 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
405 | uint32_t crtc_pitch, pitch_pixels; |
405 | uint32_t crtc_pitch, pitch_pixels; |
406 | uint32_t tiling_flags; |
406 | uint32_t tiling_flags; |
407 | int format; |
407 | int format; |
408 | uint32_t gen_cntl_reg, gen_cntl_val; |
408 | uint32_t gen_cntl_reg, gen_cntl_val; |
409 | 409 | ||
410 | DRM_DEBUG("\n"); |
410 | DRM_DEBUG("\n"); |
411 | 411 | ||
412 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
412 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
413 | 413 | ||
414 | switch (crtc->fb->bits_per_pixel) { |
414 | switch (crtc->fb->bits_per_pixel) { |
415 | case 8: |
415 | case 8: |
416 | format = 2; |
416 | format = 2; |
417 | break; |
417 | break; |
418 | case 15: /* 555 */ |
418 | case 15: /* 555 */ |
419 | format = 3; |
419 | format = 3; |
420 | break; |
420 | break; |
421 | case 16: /* 565 */ |
421 | case 16: /* 565 */ |
422 | format = 4; |
422 | format = 4; |
423 | break; |
423 | break; |
424 | case 24: /* RGB */ |
424 | case 24: /* RGB */ |
425 | format = 5; |
425 | format = 5; |
426 | break; |
426 | break; |
427 | case 32: /* xRGB */ |
427 | case 32: /* xRGB */ |
428 | format = 6; |
428 | format = 6; |
429 | break; |
429 | break; |
430 | default: |
430 | default: |
431 | return false; |
431 | return false; |
432 | } |
432 | } |
433 | 433 | ||
434 | obj = radeon_fb->obj; |
434 | obj = radeon_fb->obj; |
435 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { |
435 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { |
436 | // return -EINVAL; |
436 | // return -EINVAL; |
437 | // } |
437 | // } |
438 | base = rdev->mc.vram_location; |
438 | base = rdev->mc.vram_location; |
439 | 439 | ||
440 | /* if scanout was in GTT this really wouldn't work */ |
440 | /* if scanout was in GTT this really wouldn't work */ |
441 | /* crtc offset is from display base addr not FB location */ |
441 | /* crtc offset is from display base addr not FB location */ |
442 | radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location; |
442 | radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location; |
443 | 443 | ||
444 | base -= radeon_crtc->legacy_display_base_addr; |
444 | base -= radeon_crtc->legacy_display_base_addr; |
445 | 445 | ||
446 | crtc_offset_cntl = 0; |
446 | crtc_offset_cntl = 0; |
447 | 447 | ||
448 | pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
448 | pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
449 | crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) + |
449 | crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) + |
450 | ((crtc->fb->bits_per_pixel * 8) - 1)) / |
450 | ((crtc->fb->bits_per_pixel * 8) - 1)) / |
451 | (crtc->fb->bits_per_pixel * 8)); |
451 | (crtc->fb->bits_per_pixel * 8)); |
452 | crtc_pitch |= crtc_pitch << 16; |
452 | crtc_pitch |= crtc_pitch << 16; |
453 | 453 | ||
454 | // radeon_object_get_tiling_flags(obj->driver_private, |
454 | // radeon_object_get_tiling_flags(obj->driver_private, |
455 | // &tiling_flags, NULL); |
455 | // &tiling_flags, NULL); |
- | 456 | tiling_flags = 0; |
|
- | 457 | ||
456 | if (tiling_flags & RADEON_TILING_MICRO) |
458 | if (tiling_flags & RADEON_TILING_MICRO) |
457 | DRM_ERROR("trying to scanout microtiled buffer\n"); |
459 | DRM_ERROR("trying to scanout microtiled buffer\n"); |
458 | 460 | ||
459 | if (tiling_flags & RADEON_TILING_MACRO) { |
461 | if (tiling_flags & RADEON_TILING_MACRO) { |
460 | if (ASIC_IS_R300(rdev)) |
462 | if (ASIC_IS_R300(rdev)) |
461 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
463 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
462 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
464 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
463 | R300_CRTC_MACRO_TILE_EN); |
465 | R300_CRTC_MACRO_TILE_EN); |
464 | else |
466 | else |
465 | crtc_offset_cntl |= RADEON_CRTC_TILE_EN; |
467 | crtc_offset_cntl |= RADEON_CRTC_TILE_EN; |
466 | } else { |
468 | } else { |
467 | if (ASIC_IS_R300(rdev)) |
469 | if (ASIC_IS_R300(rdev)) |
468 | crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | |
470 | crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | |
469 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
471 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
470 | R300_CRTC_MACRO_TILE_EN); |
472 | R300_CRTC_MACRO_TILE_EN); |
471 | else |
473 | else |
472 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
474 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
473 | } |
475 | } |
474 | 476 | ||
475 | if (tiling_flags & RADEON_TILING_MACRO) { |
477 | if (tiling_flags & RADEON_TILING_MACRO) { |
476 | if (ASIC_IS_R300(rdev)) { |
478 | if (ASIC_IS_R300(rdev)) { |
477 | crtc_tile_x0_y0 = x | (y << 16); |
479 | crtc_tile_x0_y0 = x | (y << 16); |
478 | base &= ~0x7ff; |
480 | base &= ~0x7ff; |
479 | } else { |
481 | } else { |
480 | int byteshift = crtc->fb->bits_per_pixel >> 4; |
482 | int byteshift = crtc->fb->bits_per_pixel >> 4; |
481 | int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; |
483 | int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; |
482 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
484 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
483 | crtc_offset_cntl |= (y % 16); |
485 | crtc_offset_cntl |= (y % 16); |
484 | } |
486 | } |
485 | } else { |
487 | } else { |
486 | int offset = y * pitch_pixels + x; |
488 | int offset = y * pitch_pixels + x; |
487 | switch (crtc->fb->bits_per_pixel) { |
489 | switch (crtc->fb->bits_per_pixel) { |
488 | case 8: |
490 | case 8: |
489 | offset *= 1; |
491 | offset *= 1; |
490 | break; |
492 | break; |
491 | case 15: |
493 | case 15: |
492 | case 16: |
494 | case 16: |
493 | offset *= 2; |
495 | offset *= 2; |
494 | break; |
496 | break; |
495 | case 24: |
497 | case 24: |
496 | offset *= 3; |
498 | offset *= 3; |
497 | break; |
499 | break; |
498 | case 32: |
500 | case 32: |
499 | offset *= 4; |
501 | offset *= 4; |
500 | break; |
502 | break; |
501 | default: |
503 | default: |
502 | return false; |
504 | return false; |
503 | } |
505 | } |
504 | base += offset; |
506 | base += offset; |
505 | } |
507 | } |
506 | 508 | ||
507 | base &= ~7; |
509 | base &= ~7; |
508 | 510 | ||
509 | if (radeon_crtc->crtc_id == 1) |
511 | if (radeon_crtc->crtc_id == 1) |
510 | gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; |
512 | gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; |
511 | else |
513 | else |
512 | gen_cntl_reg = RADEON_CRTC_GEN_CNTL; |
514 | gen_cntl_reg = RADEON_CRTC_GEN_CNTL; |
513 | 515 | ||
514 | gen_cntl_val = RREG32(gen_cntl_reg); |
516 | gen_cntl_val = RREG32(gen_cntl_reg); |
515 | gen_cntl_val &= ~(0xf << 8); |
517 | gen_cntl_val &= ~(0xf << 8); |
516 | gen_cntl_val |= (format << 8); |
518 | gen_cntl_val |= (format << 8); |
517 | WREG32(gen_cntl_reg, gen_cntl_val); |
519 | WREG32(gen_cntl_reg, gen_cntl_val); |
518 | 520 | ||
519 | crtc_offset = (u32)base; |
521 | crtc_offset = (u32)base; |
520 | 522 | ||
521 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); |
523 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); |
522 | 524 | ||
523 | if (ASIC_IS_R300(rdev)) { |
525 | if (ASIC_IS_R300(rdev)) { |
524 | if (radeon_crtc->crtc_id) |
526 | if (radeon_crtc->crtc_id) |
525 | WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); |
527 | WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); |
526 | else |
528 | else |
527 | WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); |
529 | WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); |
528 | } |
530 | } |
529 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
531 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
530 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
532 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
531 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
533 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
532 | 534 | ||
533 | if (old_fb && old_fb != crtc->fb) { |
535 | // if (old_fb && old_fb != crtc->fb) { |
534 | radeon_fb = to_radeon_framebuffer(old_fb); |
536 | // radeon_fb = to_radeon_framebuffer(old_fb); |
535 | // radeon_gem_object_unpin(radeon_fb->obj); |
537 | // radeon_gem_object_unpin(radeon_fb->obj); |
536 | } |
538 | // } |
537 | 539 | ||
538 | /* Bytes per pixel may have changed */ |
540 | /* Bytes per pixel may have changed */ |
539 | radeon_bandwidth_update(rdev); |
541 | radeon_bandwidth_update(rdev); |
540 | 542 | ||
541 | return 0; |
543 | return 0; |
542 | } |
544 | } |
543 | 545 | ||
544 | static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) |
546 | static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) |
545 | { |
547 | { |
546 | struct drm_device *dev = crtc->dev; |
548 | struct drm_device *dev = crtc->dev; |
547 | struct radeon_device *rdev = dev->dev_private; |
549 | struct radeon_device *rdev = dev->dev_private; |
548 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
550 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
549 | struct drm_encoder *encoder; |
551 | struct drm_encoder *encoder; |
550 | int format; |
552 | int format; |
551 | int hsync_start; |
553 | int hsync_start; |
552 | int hsync_wid; |
554 | int hsync_wid; |
553 | int vsync_wid; |
555 | int vsync_wid; |
554 | uint32_t crtc_h_total_disp; |
556 | uint32_t crtc_h_total_disp; |
555 | uint32_t crtc_h_sync_strt_wid; |
557 | uint32_t crtc_h_sync_strt_wid; |
556 | uint32_t crtc_v_total_disp; |
558 | uint32_t crtc_v_total_disp; |
557 | uint32_t crtc_v_sync_strt_wid; |
559 | uint32_t crtc_v_sync_strt_wid; |
558 | bool is_tv = false; |
560 | bool is_tv = false; |
559 | 561 | ||
560 | DRM_DEBUG("\n"); |
562 | DRM_DEBUG("\n"); |
561 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
563 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
562 | if (encoder->crtc == crtc) { |
564 | if (encoder->crtc == crtc) { |
563 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
565 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
564 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
566 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
565 | is_tv = true; |
567 | is_tv = true; |
566 | DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); |
568 | DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); |
567 | break; |
569 | break; |
568 | } |
570 | } |
569 | } |
571 | } |
570 | } |
572 | } |
571 | 573 | ||
572 | switch (crtc->fb->bits_per_pixel) { |
574 | switch (crtc->fb->bits_per_pixel) { |
573 | case 8: |
575 | case 8: |
574 | format = 2; |
576 | format = 2; |
575 | break; |
577 | break; |
576 | case 15: /* 555 */ |
578 | case 15: /* 555 */ |
577 | format = 3; |
579 | format = 3; |
578 | break; |
580 | break; |
579 | case 16: /* 565 */ |
581 | case 16: /* 565 */ |
580 | format = 4; |
582 | format = 4; |
581 | break; |
583 | break; |
582 | case 24: /* RGB */ |
584 | case 24: /* RGB */ |
583 | format = 5; |
585 | format = 5; |
584 | break; |
586 | break; |
585 | case 32: /* xRGB */ |
587 | case 32: /* xRGB */ |
586 | format = 6; |
588 | format = 6; |
587 | break; |
589 | break; |
588 | default: |
590 | default: |
589 | return false; |
591 | return false; |
590 | } |
592 | } |
591 | 593 | ||
592 | crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
594 | crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
593 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
595 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
594 | 596 | ||
595 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
597 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
596 | if (!hsync_wid) |
598 | if (!hsync_wid) |
597 | hsync_wid = 1; |
599 | hsync_wid = 1; |
598 | hsync_start = mode->crtc_hsync_start - 8; |
600 | hsync_start = mode->crtc_hsync_start - 8; |
599 | 601 | ||
600 | crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
602 | crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
601 | | ((hsync_wid & 0x3f) << 16) |
603 | | ((hsync_wid & 0x3f) << 16) |
602 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
604 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
603 | ? RADEON_CRTC_H_SYNC_POL |
605 | ? RADEON_CRTC_H_SYNC_POL |
604 | : 0)); |
606 | : 0)); |
605 | 607 | ||
606 | /* This works for double scan mode. */ |
608 | /* This works for double scan mode. */ |
607 | crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
609 | crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
608 | | ((mode->crtc_vdisplay - 1) << 16)); |
610 | | ((mode->crtc_vdisplay - 1) << 16)); |
609 | 611 | ||
610 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
612 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
611 | if (!vsync_wid) |
613 | if (!vsync_wid) |
612 | vsync_wid = 1; |
614 | vsync_wid = 1; |
613 | 615 | ||
614 | crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
616 | crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
615 | | ((vsync_wid & 0x1f) << 16) |
617 | | ((vsync_wid & 0x1f) << 16) |
616 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
618 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
617 | ? RADEON_CRTC_V_SYNC_POL |
619 | ? RADEON_CRTC_V_SYNC_POL |
618 | : 0)); |
620 | : 0)); |
619 | 621 | ||
620 | /* TODO -> Dell Server */ |
622 | /* TODO -> Dell Server */ |
621 | if (0) { |
623 | if (0) { |
622 | uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
624 | uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
623 | uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
625 | uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
624 | uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
626 | uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
625 | uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
627 | uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
626 | 628 | ||
627 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
629 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
628 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
630 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
629 | 631 | ||
630 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
632 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
631 | enable it, even it's detected. |
633 | enable it, even it's detected. |
632 | */ |
634 | */ |
633 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
635 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
634 | tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); |
636 | tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); |
635 | tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); |
637 | tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); |
636 | 638 | ||
637 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
639 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
638 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
640 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
639 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
641 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
640 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
642 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
641 | } |
643 | } |
642 | 644 | ||
643 | if (radeon_crtc->crtc_id) { |
645 | if (radeon_crtc->crtc_id) { |
644 | uint32_t crtc2_gen_cntl; |
646 | uint32_t crtc2_gen_cntl; |
645 | uint32_t disp2_merge_cntl; |
647 | uint32_t disp2_merge_cntl; |
646 | 648 | ||
647 | /* check to see if TV DAC is enabled for another crtc and keep it enabled */ |
649 | /* check to see if TV DAC is enabled for another crtc and keep it enabled */ |
648 | if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON) |
650 | if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON) |
649 | crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; |
651 | crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; |
650 | else |
652 | else |
651 | crtc2_gen_cntl = 0; |
653 | crtc2_gen_cntl = 0; |
652 | 654 | ||
653 | crtc2_gen_cntl |= ((format << 8) |
655 | crtc2_gen_cntl |= ((format << 8) |
654 | | RADEON_CRTC2_VSYNC_DIS |
656 | | RADEON_CRTC2_VSYNC_DIS |
655 | | RADEON_CRTC2_HSYNC_DIS |
657 | | RADEON_CRTC2_HSYNC_DIS |
656 | | RADEON_CRTC2_DISP_DIS |
658 | | RADEON_CRTC2_DISP_DIS |
657 | | RADEON_CRTC2_DISP_REQ_EN_B |
659 | | RADEON_CRTC2_DISP_REQ_EN_B |
658 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
660 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
659 | ? RADEON_CRTC2_DBL_SCAN_EN |
661 | ? RADEON_CRTC2_DBL_SCAN_EN |
660 | : 0) |
662 | : 0) |
661 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
663 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
662 | ? RADEON_CRTC2_CSYNC_EN |
664 | ? RADEON_CRTC2_CSYNC_EN |
663 | : 0) |
665 | : 0) |
664 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
666 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
665 | ? RADEON_CRTC2_INTERLACE_EN |
667 | ? RADEON_CRTC2_INTERLACE_EN |
666 | : 0)); |
668 | : 0)); |
667 | 669 | ||
668 | disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
670 | disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
669 | disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
671 | disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
670 | 672 | ||
671 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
673 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
672 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
674 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
673 | 675 | ||
674 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); |
676 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); |
675 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); |
677 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); |
676 | } else { |
678 | } else { |
677 | uint32_t crtc_gen_cntl; |
679 | uint32_t crtc_gen_cntl; |
678 | uint32_t crtc_ext_cntl; |
680 | uint32_t crtc_ext_cntl; |
679 | uint32_t disp_merge_cntl; |
681 | uint32_t disp_merge_cntl; |
680 | 682 | ||
681 | crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN |
683 | crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN |
682 | | (format << 8) |
684 | | (format << 8) |
683 | | RADEON_CRTC_DISP_REQ_EN_B |
685 | | RADEON_CRTC_DISP_REQ_EN_B |
684 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
686 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
685 | ? RADEON_CRTC_DBL_SCAN_EN |
687 | ? RADEON_CRTC_DBL_SCAN_EN |
686 | : 0) |
688 | : 0) |
687 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
689 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
688 | ? RADEON_CRTC_CSYNC_EN |
690 | ? RADEON_CRTC_CSYNC_EN |
689 | : 0) |
691 | : 0) |
690 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
692 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
691 | ? RADEON_CRTC_INTERLACE_EN |
693 | ? RADEON_CRTC_INTERLACE_EN |
692 | : 0)); |
694 | : 0)); |
693 | 695 | ||
694 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
696 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
695 | crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | |
697 | crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | |
696 | RADEON_CRTC_VSYNC_DIS | |
698 | RADEON_CRTC_VSYNC_DIS | |
697 | RADEON_CRTC_HSYNC_DIS | |
699 | RADEON_CRTC_HSYNC_DIS | |
698 | RADEON_CRTC_DISPLAY_DIS); |
700 | RADEON_CRTC_DISPLAY_DIS); |
699 | 701 | ||
700 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
702 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
701 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
703 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
702 | 704 | ||
703 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
705 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
704 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
706 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
705 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
707 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
706 | } |
708 | } |
707 | 709 | ||
708 | if (is_tv) |
710 | if (is_tv) |
709 | radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, |
711 | radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, |
710 | &crtc_h_sync_strt_wid, &crtc_v_total_disp, |
712 | &crtc_h_sync_strt_wid, &crtc_v_total_disp, |
711 | &crtc_v_sync_strt_wid); |
713 | &crtc_v_sync_strt_wid); |
712 | 714 | ||
713 | WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); |
715 | WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); |
714 | WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); |
716 | WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); |
715 | WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); |
717 | WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); |
716 | WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); |
718 | WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); |
717 | 719 | ||
718 | return true; |
720 | return true; |
719 | } |
721 | } |
720 | 722 | ||
721 | static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
723 | static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
722 | { |
724 | { |
723 | struct drm_device *dev = crtc->dev; |
725 | struct drm_device *dev = crtc->dev; |
724 | struct radeon_device *rdev = dev->dev_private; |
726 | struct radeon_device *rdev = dev->dev_private; |
725 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
727 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
726 | struct drm_encoder *encoder; |
728 | struct drm_encoder *encoder; |
727 | uint32_t feedback_div = 0; |
729 | uint32_t feedback_div = 0; |
728 | uint32_t frac_fb_div = 0; |
730 | uint32_t frac_fb_div = 0; |
729 | uint32_t reference_div = 0; |
731 | uint32_t reference_div = 0; |
730 | uint32_t post_divider = 0; |
732 | uint32_t post_divider = 0; |
731 | uint32_t freq = 0; |
733 | uint32_t freq = 0; |
732 | uint8_t pll_gain; |
734 | uint8_t pll_gain; |
733 | int pll_flags = RADEON_PLL_LEGACY; |
735 | int pll_flags = RADEON_PLL_LEGACY; |
734 | bool use_bios_divs = false; |
736 | bool use_bios_divs = false; |
735 | /* PLL registers */ |
737 | /* PLL registers */ |
736 | uint32_t pll_ref_div = 0; |
738 | uint32_t pll_ref_div = 0; |
737 | uint32_t pll_fb_post_div = 0; |
739 | uint32_t pll_fb_post_div = 0; |
738 | uint32_t htotal_cntl = 0; |
740 | uint32_t htotal_cntl = 0; |
739 | bool is_tv = false; |
741 | bool is_tv = false; |
740 | struct radeon_pll *pll; |
742 | struct radeon_pll *pll; |
741 | 743 | ||
742 | struct { |
744 | struct { |
743 | int divider; |
745 | int divider; |
744 | int bitvalue; |
746 | int bitvalue; |
745 | } *post_div, post_divs[] = { |
747 | } *post_div, post_divs[] = { |
746 | /* From RAGE 128 VR/RAGE 128 GL Register |
748 | /* From RAGE 128 VR/RAGE 128 GL Register |
747 | * Reference Manual (Technical Reference |
749 | * Reference Manual (Technical Reference |
748 | * Manual P/N RRG-G04100-C Rev. 0.04), page |
750 | * Manual P/N RRG-G04100-C Rev. 0.04), page |
749 | * 3-17 (PLL_DIV_[3:0]). |
751 | * 3-17 (PLL_DIV_[3:0]). |
750 | */ |
752 | */ |
751 | { 1, 0 }, /* VCLK_SRC */ |
753 | { 1, 0 }, /* VCLK_SRC */ |
752 | { 2, 1 }, /* VCLK_SRC/2 */ |
754 | { 2, 1 }, /* VCLK_SRC/2 */ |
753 | { 4, 2 }, /* VCLK_SRC/4 */ |
755 | { 4, 2 }, /* VCLK_SRC/4 */ |
754 | { 8, 3 }, /* VCLK_SRC/8 */ |
756 | { 8, 3 }, /* VCLK_SRC/8 */ |
755 | { 3, 4 }, /* VCLK_SRC/3 */ |
757 | { 3, 4 }, /* VCLK_SRC/3 */ |
756 | { 16, 5 }, /* VCLK_SRC/16 */ |
758 | { 16, 5 }, /* VCLK_SRC/16 */ |
757 | { 6, 6 }, /* VCLK_SRC/6 */ |
759 | { 6, 6 }, /* VCLK_SRC/6 */ |
758 | { 12, 7 }, /* VCLK_SRC/12 */ |
760 | { 12, 7 }, /* VCLK_SRC/12 */ |
759 | { 0, 0 } |
761 | { 0, 0 } |
760 | }; |
762 | }; |
761 | 763 | ||
762 | if (radeon_crtc->crtc_id) |
764 | if (radeon_crtc->crtc_id) |
763 | pll = &rdev->clock.p2pll; |
765 | pll = &rdev->clock.p2pll; |
764 | else |
766 | else |
765 | pll = &rdev->clock.p1pll; |
767 | pll = &rdev->clock.p1pll; |
766 | 768 | ||
767 | if (mode->clock > 200000) /* range limits??? */ |
769 | if (mode->clock > 200000) /* range limits??? */ |
768 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
770 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
769 | else |
771 | else |
770 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
772 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
771 | 773 | ||
772 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
774 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
773 | if (encoder->crtc == crtc) { |
775 | if (encoder->crtc == crtc) { |
774 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
776 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
775 | 777 | ||
776 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
778 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
777 | is_tv = true; |
779 | is_tv = true; |
778 | break; |
780 | break; |
779 | } |
781 | } |
780 | 782 | ||
781 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
783 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
782 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
784 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
783 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
785 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
784 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
786 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
785 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
787 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
786 | if (lvds) { |
788 | if (lvds) { |
787 | if (lvds->use_bios_dividers) { |
789 | if (lvds->use_bios_dividers) { |
788 | pll_ref_div = lvds->panel_ref_divider; |
790 | pll_ref_div = lvds->panel_ref_divider; |
789 | pll_fb_post_div = (lvds->panel_fb_divider | |
791 | pll_fb_post_div = (lvds->panel_fb_divider | |
790 | (lvds->panel_post_divider << 16)); |
792 | (lvds->panel_post_divider << 16)); |
791 | htotal_cntl = 0; |
793 | htotal_cntl = 0; |
792 | use_bios_divs = true; |
794 | use_bios_divs = true; |
793 | } |
795 | } |
794 | } |
796 | } |
795 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
797 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
796 | } |
798 | } |
797 | } |
799 | } |
798 | } |
800 | } |
799 | 801 | ||
800 | DRM_DEBUG("\n"); |
802 | DRM_DEBUG("\n"); |
801 | 803 | ||
802 | if (!use_bios_divs) { |
804 | if (!use_bios_divs) { |
803 | radeon_compute_pll(pll, mode->clock, |
805 | radeon_compute_pll(pll, mode->clock, |
804 | &freq, &feedback_div, &frac_fb_div, |
806 | &freq, &feedback_div, &frac_fb_div, |
805 | &reference_div, &post_divider, |
807 | &reference_div, &post_divider, |
806 | pll_flags); |
808 | pll_flags); |
807 | 809 | ||
808 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { |
810 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { |
809 | if (post_div->divider == post_divider) |
811 | if (post_div->divider == post_divider) |
810 | break; |
812 | break; |
811 | } |
813 | } |
812 | 814 | ||
813 | if (!post_div->divider) |
815 | if (!post_div->divider) |
814 | post_div = &post_divs[0]; |
816 | post_div = &post_divs[0]; |
815 | 817 | ||
816 | DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n", |
818 | DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n", |
817 | (unsigned)freq, |
819 | (unsigned)freq, |
818 | feedback_div, |
820 | feedback_div, |
819 | reference_div, |
821 | reference_div, |
820 | post_divider); |
822 | post_divider); |
821 | 823 | ||
822 | pll_ref_div = reference_div; |
824 | pll_ref_div = reference_div; |
823 | #if defined(__powerpc__) && (0) /* TODO */ |
825 | #if defined(__powerpc__) && (0) /* TODO */ |
824 | /* apparently programming this otherwise causes a hang??? */ |
826 | /* apparently programming this otherwise causes a hang??? */ |
825 | if (info->MacModel == RADEON_MAC_IBOOK) |
827 | if (info->MacModel == RADEON_MAC_IBOOK) |
826 | pll_fb_post_div = 0x000600ad; |
828 | pll_fb_post_div = 0x000600ad; |
827 | else |
829 | else |
828 | #endif |
830 | #endif |
829 | pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); |
831 | pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); |
830 | 832 | ||
831 | htotal_cntl = mode->htotal & 0x7; |
833 | htotal_cntl = mode->htotal & 0x7; |
832 | 834 | ||
833 | } |
835 | } |
834 | 836 | ||
835 | pll_gain = radeon_compute_pll_gain(pll->reference_freq, |
837 | pll_gain = radeon_compute_pll_gain(pll->reference_freq, |
836 | pll_ref_div & 0x3ff, |
838 | pll_ref_div & 0x3ff, |
837 | pll_fb_post_div & 0x7ff); |
839 | pll_fb_post_div & 0x7ff); |
838 | 840 | ||
839 | if (radeon_crtc->crtc_id) { |
841 | if (radeon_crtc->crtc_id) { |
840 | uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & |
842 | uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & |
841 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | |
843 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | |
842 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); |
844 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); |
843 | 845 | ||
844 | if (is_tv) { |
846 | if (is_tv) { |
845 | radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, |
847 | radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, |
846 | &pll_ref_div, &pll_fb_post_div, |
848 | &pll_ref_div, &pll_fb_post_div, |
847 | &pixclks_cntl); |
849 | &pixclks_cntl); |
848 | } |
850 | } |
849 | 851 | ||
850 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
852 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
851 | RADEON_PIX2CLK_SRC_SEL_CPUCLK, |
853 | RADEON_PIX2CLK_SRC_SEL_CPUCLK, |
852 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
854 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
853 | 855 | ||
854 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
856 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
855 | RADEON_P2PLL_RESET |
857 | RADEON_P2PLL_RESET |
856 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
858 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
857 | | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), |
859 | | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), |
858 | ~(RADEON_P2PLL_RESET |
860 | ~(RADEON_P2PLL_RESET |
859 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
861 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
860 | | RADEON_P2PLL_PVG_MASK)); |
862 | | RADEON_P2PLL_PVG_MASK)); |
861 | 863 | ||
862 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
864 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
863 | pll_ref_div, |
865 | pll_ref_div, |
864 | ~RADEON_P2PLL_REF_DIV_MASK); |
866 | ~RADEON_P2PLL_REF_DIV_MASK); |
865 | 867 | ||
866 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
868 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
867 | pll_fb_post_div, |
869 | pll_fb_post_div, |
868 | ~RADEON_P2PLL_FB0_DIV_MASK); |
870 | ~RADEON_P2PLL_FB0_DIV_MASK); |
869 | 871 | ||
870 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
872 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
871 | pll_fb_post_div, |
873 | pll_fb_post_div, |
872 | ~RADEON_P2PLL_POST0_DIV_MASK); |
874 | ~RADEON_P2PLL_POST0_DIV_MASK); |
873 | 875 | ||
874 | radeon_pll2_write_update(dev); |
876 | radeon_pll2_write_update(dev); |
875 | radeon_pll2_wait_for_read_update_complete(dev); |
877 | radeon_pll2_wait_for_read_update_complete(dev); |
876 | 878 | ||
877 | WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); |
879 | WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); |
878 | 880 | ||
879 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
881 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
880 | 0, |
882 | 0, |
881 | ~(RADEON_P2PLL_RESET |
883 | ~(RADEON_P2PLL_RESET |
882 | | RADEON_P2PLL_SLEEP |
884 | | RADEON_P2PLL_SLEEP |
883 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
885 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
884 | 886 | ||
885 | DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
887 | DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
886 | (unsigned)pll_ref_div, |
888 | (unsigned)pll_ref_div, |
887 | (unsigned)pll_fb_post_div, |
889 | (unsigned)pll_fb_post_div, |
888 | (unsigned)htotal_cntl, |
890 | (unsigned)htotal_cntl, |
889 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
891 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
890 | DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n", |
892 | DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n", |
891 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
893 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
892 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
894 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
893 | (unsigned)((pll_fb_post_div & |
895 | (unsigned)((pll_fb_post_div & |
894 | RADEON_P2PLL_POST0_DIV_MASK) >> 16)); |
896 | RADEON_P2PLL_POST0_DIV_MASK) >> 16)); |
895 | 897 | ||
896 | mdelay(50); /* Let the clock to lock */ |
898 | mdelay(50); /* Let the clock to lock */ |
897 | 899 | ||
898 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
900 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
899 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, |
901 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, |
900 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
902 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
901 | 903 | ||
902 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
904 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
903 | } else { |
905 | } else { |
904 | uint32_t pixclks_cntl; |
906 | uint32_t pixclks_cntl; |
905 | 907 | ||
906 | 908 | ||
907 | if (is_tv) { |
909 | if (is_tv) { |
908 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
910 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
909 | radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, |
911 | radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, |
910 | &pll_fb_post_div, &pixclks_cntl); |
912 | &pll_fb_post_div, &pixclks_cntl); |
911 | } |
913 | } |
912 | 914 | ||
913 | if (rdev->flags & RADEON_IS_MOBILITY) { |
915 | if (rdev->flags & RADEON_IS_MOBILITY) { |
914 | /* A temporal workaround for the occational blanking on certain laptop panels. |
916 | /* A temporal workaround for the occational blanking on certain laptop panels. |
915 | This appears to related to the PLL divider registers (fail to lock?). |
917 | This appears to related to the PLL divider registers (fail to lock?). |
916 | It occurs even when all dividers are the same with their old settings. |
918 | It occurs even when all dividers are the same with their old settings. |
917 | In this case we really don't need to fiddle with PLL registers. |
919 | In this case we really don't need to fiddle with PLL registers. |
918 | By doing this we can avoid the blanking problem with some panels. |
920 | By doing this we can avoid the blanking problem with some panels. |
919 | */ |
921 | */ |
920 | if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && |
922 | if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && |
921 | (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & |
923 | (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & |
922 | (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { |
924 | (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { |
923 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
925 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
924 | RADEON_PLL_DIV_SEL, |
926 | RADEON_PLL_DIV_SEL, |
925 | ~(RADEON_PLL_DIV_SEL)); |
927 | ~(RADEON_PLL_DIV_SEL)); |
926 | r100_pll_errata_after_index(rdev); |
928 | r100_pll_errata_after_index(rdev); |
927 | return; |
929 | return; |
928 | } |
930 | } |
929 | } |
931 | } |
930 | 932 | ||
931 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
933 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
932 | RADEON_VCLK_SRC_SEL_CPUCLK, |
934 | RADEON_VCLK_SRC_SEL_CPUCLK, |
933 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
935 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
934 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
936 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
935 | RADEON_PPLL_RESET |
937 | RADEON_PPLL_RESET |
936 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
938 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
937 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
939 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
938 | | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), |
940 | | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), |
939 | ~(RADEON_PPLL_RESET |
941 | ~(RADEON_PPLL_RESET |
940 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
942 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
941 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
943 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
942 | | RADEON_PPLL_PVG_MASK)); |
944 | | RADEON_PPLL_PVG_MASK)); |
943 | 945 | ||
944 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
946 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
945 | RADEON_PLL_DIV_SEL, |
947 | RADEON_PLL_DIV_SEL, |
946 | ~(RADEON_PLL_DIV_SEL)); |
948 | ~(RADEON_PLL_DIV_SEL)); |
947 | r100_pll_errata_after_index(rdev); |
949 | r100_pll_errata_after_index(rdev); |
948 | 950 | ||
949 | if (ASIC_IS_R300(rdev) || |
951 | if (ASIC_IS_R300(rdev) || |
950 | (rdev->family == CHIP_RS300) || |
952 | (rdev->family == CHIP_RS300) || |
951 | (rdev->family == CHIP_RS400) || |
953 | (rdev->family == CHIP_RS400) || |
952 | (rdev->family == CHIP_RS480)) { |
954 | (rdev->family == CHIP_RS480)) { |
953 | if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
955 | if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
954 | /* When restoring console mode, use saved PPLL_REF_DIV |
956 | /* When restoring console mode, use saved PPLL_REF_DIV |
955 | * setting. |
957 | * setting. |
956 | */ |
958 | */ |
957 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
959 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
958 | pll_ref_div, |
960 | pll_ref_div, |
959 | 0); |
961 | 0); |
960 | } else { |
962 | } else { |
961 | /* R300 uses ref_div_acc field as real ref divider */ |
963 | /* R300 uses ref_div_acc field as real ref divider */ |
962 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
964 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
963 | (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), |
965 | (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), |
964 | ~R300_PPLL_REF_DIV_ACC_MASK); |
966 | ~R300_PPLL_REF_DIV_ACC_MASK); |
965 | } |
967 | } |
966 | } else |
968 | } else |
967 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
969 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
968 | pll_ref_div, |
970 | pll_ref_div, |
969 | ~RADEON_PPLL_REF_DIV_MASK); |
971 | ~RADEON_PPLL_REF_DIV_MASK); |
970 | 972 | ||
971 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
973 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
972 | pll_fb_post_div, |
974 | pll_fb_post_div, |
973 | ~RADEON_PPLL_FB3_DIV_MASK); |
975 | ~RADEON_PPLL_FB3_DIV_MASK); |
974 | 976 | ||
975 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
977 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
976 | pll_fb_post_div, |
978 | pll_fb_post_div, |
977 | ~RADEON_PPLL_POST3_DIV_MASK); |
979 | ~RADEON_PPLL_POST3_DIV_MASK); |
978 | 980 | ||
979 | radeon_pll_write_update(dev); |
981 | radeon_pll_write_update(dev); |
980 | radeon_pll_wait_for_read_update_complete(dev); |
982 | radeon_pll_wait_for_read_update_complete(dev); |
981 | 983 | ||
982 | WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); |
984 | WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); |
983 | 985 | ||
984 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
986 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
985 | 0, |
987 | 0, |
986 | ~(RADEON_PPLL_RESET |
988 | ~(RADEON_PPLL_RESET |
987 | | RADEON_PPLL_SLEEP |
989 | | RADEON_PPLL_SLEEP |
988 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
990 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
989 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
991 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
990 | 992 | ||
991 | DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
993 | DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
992 | pll_ref_div, |
994 | pll_ref_div, |
993 | pll_fb_post_div, |
995 | pll_fb_post_div, |
994 | (unsigned)htotal_cntl, |
996 | (unsigned)htotal_cntl, |
995 | RREG32_PLL(RADEON_PPLL_CNTL)); |
997 | RREG32_PLL(RADEON_PPLL_CNTL)); |
996 | DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n", |
998 | DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n", |
997 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
999 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
998 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
1000 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
999 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
1001 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
1000 | 1002 | ||
1001 | mdelay(50); /* Let the clock to lock */ |
1003 | mdelay(50); /* Let the clock to lock */ |
1002 | 1004 | ||
1003 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
1005 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
1004 | RADEON_VCLK_SRC_SEL_PPLLCLK, |
1006 | RADEON_VCLK_SRC_SEL_PPLLCLK, |
1005 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
1007 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
1006 | 1008 | ||
1007 | if (is_tv) |
1009 | if (is_tv) |
1008 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
1010 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
1009 | } |
1011 | } |
1010 | } |
1012 | } |
1011 | 1013 | ||
1012 | static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, |
1014 | static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, |
1013 | struct drm_display_mode *mode, |
1015 | struct drm_display_mode *mode, |
1014 | struct drm_display_mode *adjusted_mode) |
1016 | struct drm_display_mode *adjusted_mode) |
1015 | { |
1017 | { |
1016 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1018 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1017 | return false; |
1019 | return false; |
1018 | return true; |
1020 | return true; |
1019 | } |
1021 | } |
1020 | 1022 | ||
1021 | static int radeon_crtc_mode_set(struct drm_crtc *crtc, |
1023 | static int radeon_crtc_mode_set(struct drm_crtc *crtc, |
1022 | struct drm_display_mode *mode, |
1024 | struct drm_display_mode *mode, |
1023 | struct drm_display_mode *adjusted_mode, |
1025 | struct drm_display_mode *adjusted_mode, |
1024 | int x, int y, struct drm_framebuffer *old_fb) |
1026 | int x, int y, struct drm_framebuffer *old_fb) |
1025 | { |
1027 | { |
1026 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1028 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1027 | 1029 | ||
1028 | /* TODO TV */ |
1030 | /* TODO TV */ |
1029 | radeon_crtc_set_base(crtc, x, y, old_fb); |
1031 | radeon_crtc_set_base(crtc, x, y, old_fb); |
1030 | radeon_set_crtc_timing(crtc, adjusted_mode); |
1032 | radeon_set_crtc_timing(crtc, adjusted_mode); |
1031 | radeon_set_pll(crtc, adjusted_mode); |
1033 | radeon_set_pll(crtc, adjusted_mode); |
1032 | if (radeon_crtc->crtc_id == 0) { |
1034 | if (radeon_crtc->crtc_id == 0) { |
1033 | radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); |
1035 | radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); |
1034 | } else { |
1036 | } else { |
1035 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1037 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1036 | /* FIXME: only first crtc has rmx what should we |
1038 | /* FIXME: only first crtc has rmx what should we |
1037 | * do ? |
1039 | * do ? |
1038 | */ |
1040 | */ |
1039 | DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); |
1041 | DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); |
1040 | } |
1042 | } |
1041 | } |
1043 | } |
1042 | return 0; |
1044 | return 0; |
1043 | } |
1045 | } |
1044 | 1046 | ||
1045 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
1047 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
1046 | { |
1048 | { |
1047 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1049 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1048 | } |
1050 | } |
1049 | 1051 | ||
1050 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
1052 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
1051 | { |
1053 | { |
1052 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
1054 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
1053 | } |
1055 | } |
1054 | 1056 | ||
1055 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
1057 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
1056 | .dpms = radeon_crtc_dpms, |
1058 | .dpms = radeon_crtc_dpms, |
1057 | .mode_fixup = radeon_crtc_mode_fixup, |
1059 | .mode_fixup = radeon_crtc_mode_fixup, |
1058 | .mode_set = radeon_crtc_mode_set, |
1060 | .mode_set = radeon_crtc_mode_set, |
1059 | .mode_set_base = radeon_crtc_set_base, |
1061 | .mode_set_base = radeon_crtc_set_base, |
1060 | .prepare = radeon_crtc_prepare, |
1062 | .prepare = radeon_crtc_prepare, |
1061 | .commit = radeon_crtc_commit, |
1063 | .commit = radeon_crtc_commit, |
1062 | .load_lut = radeon_crtc_load_lut, |
1064 | .load_lut = radeon_crtc_load_lut, |
1063 | }; |
1065 | }; |
1064 | 1066 | ||
1065 | 1067 | ||
1066 | void radeon_legacy_init_crtc(struct drm_device *dev, |
1068 | void radeon_legacy_init_crtc(struct drm_device *dev, |
1067 | struct radeon_crtc *radeon_crtc) |
1069 | struct radeon_crtc *radeon_crtc) |
1068 | { |
1070 | { |
1069 | if (radeon_crtc->crtc_id == 1) |
1071 | if (radeon_crtc->crtc_id == 1) |
1070 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
1072 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
1071 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); |
1073 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); |
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1073 | 1075 | ||
1074 | ><16)); |
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