WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_legacy_crtc.c


/*
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include 
#include 
#include 
#include "radeon_fixed.h"
#include "radeon.h"
#include "atom.h"
 
static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
				       struct drm_display_mode *mode,
				       struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	int xres = mode->hdisplay;
	int yres = mode->vdisplay;
	bool hscale = true, vscale = true;
	int hsync_wid;
	int vsync_wid;
	int hsync_start;
	int blank_width;
	u32 scale, inc, crtc_more_cntl;
	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
	struct radeon_native_mode *native_mode = &radeon_crtc->native_mode;
 
	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
		(RADEON_VERT_STRETCH_RESERVED |
		 RADEON_VERT_AUTO_RATIO_INC);
	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
		(RADEON_HORZ_FP_LOOP_STRETCH |
		 RADEON_HORZ_AUTO_RATIO_INC);
 
	crtc_more_cntl = 0;
	if ((rdev->family == CHIP_RS100) ||
	    (rdev->family == CHIP_RS200)) {
		/* This is to workaround the asic bug for RMX, some versions
		   of BIOS dosen't have this register initialized correctly. */
		crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
	}
 
 
	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
				| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
	if (!hsync_wid)
		hsync_wid = 1;
	hsync_start = mode->crtc_hsync_start - 8;
 
	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
			      | ((hsync_wid & 0x3f) << 16)
			      | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
				 ? RADEON_CRTC_H_SYNC_POL
				 : 0));
 
	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
				| ((mode->crtc_vdisplay - 1) << 16));
 
	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
	if (!vsync_wid)
		vsync_wid = 1;
 
	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
			      | ((vsync_wid & 0x1f) << 16)
			      | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
				 ? RADEON_CRTC_V_SYNC_POL
				 : 0));
 
	fp_horz_vert_active = 0;
 
	if (native_mode->panel_xres == 0 ||
	    native_mode->panel_yres == 0) {
		hscale = false;
		vscale = false;
	} else {
		if (xres > native_mode->panel_xres)
			xres = native_mode->panel_xres;
		if (yres > native_mode->panel_yres)
			yres = native_mode->panel_yres;
 
		if (xres == native_mode->panel_xres)
			hscale = false;
		if (yres == native_mode->panel_yres)
			vscale = false;
	}
 
	switch (radeon_crtc->rmx_type) {
	case RMX_FULL:
	case RMX_ASPECT:
		if (!hscale)
			fp_horz_stretch |= ((xres/8-1) << 16);
		else {
			inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
			scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
				/ native_mode->panel_xres + 1;
			fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
					RADEON_HORZ_STRETCH_BLEND |
					RADEON_HORZ_STRETCH_ENABLE |
					((native_mode->panel_xres/8-1) << 16));
		}
 
		if (!vscale)
			fp_vert_stretch |= ((yres-1) << 12);
		else {
			inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
			scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
				/ native_mode->panel_yres + 1;
			fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
					RADEON_VERT_STRETCH_ENABLE |
					RADEON_VERT_STRETCH_BLEND |
					((native_mode->panel_yres-1) << 12));
		}
		break;
	case RMX_CENTER:
		fp_horz_stretch |= ((xres/8-1) << 16);
		fp_vert_stretch |= ((yres-1) << 12);
 
		crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
				RADEON_CRTC_AUTO_VERT_CENTER_EN);
 
		blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
		if (blank_width > 110)
			blank_width = 110;
 
		fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
				| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
		hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
		if (!hsync_wid)
			hsync_wid = 1;
 
		fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
				| ((hsync_wid & 0x3f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
					? RADEON_CRTC_H_SYNC_POL
					: 0));
 
		fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
				| ((mode->crtc_vdisplay - 1) << 16));
 
		vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
		if (!vsync_wid)
			vsync_wid = 1;
 
		fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
					| ((vsync_wid & 0x1f) << 16)
					| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
						? RADEON_CRTC_V_SYNC_POL
						: 0)));
 
		fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) |
				(((native_mode->panel_xres / 8) & 0x1ff) << 16));
		break;
	case RMX_OFF:
	default:
		fp_horz_stretch |= ((xres/8-1) << 16);
		fp_vert_stretch |= ((yres-1) << 12);
		break;
	}
 
	WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
	WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
	WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
	WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
	WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
	WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
}
 
void radeon_restore_common_regs(struct drm_device *dev)
{
	/* don't need this yet */
}
 
static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int i = 0;
 
	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
	   the cause yet, but this workaround will mask the problem for now.
	   Other chips usually will pass at the very first test, so the
	   workaround shouldn't have any effect on them. */
	for (i = 0;
	     (i < 10000 &&
	      RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
	     i++);
}
 
static void radeon_pll_write_update(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
 
	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 
	WREG32_PLL_P(RADEON_PPLL_REF_DIV,
			   RADEON_PPLL_ATOMIC_UPDATE_W,
			   ~(RADEON_PPLL_ATOMIC_UPDATE_W));
}
 
static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int i = 0;
 
 
	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
	   the cause yet, but this workaround will mask the problem for now.
	   Other chips usually will pass at the very first test, so the
	   workaround shouldn't have any effect on them. */
	for (i = 0;
	     (i < 10000 &&
	      RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
	     i++);
}
 
static void radeon_pll2_write_update(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
 
	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 
	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
			   RADEON_P2PLL_ATOMIC_UPDATE_W,
			   ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
}
 
static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
				       uint16_t fb_div)
{
	unsigned int vcoFreq;
 
	if (!ref_div)
		return 1;
 
	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
 
	/*
	 * This is horribly crude: the VCO frequency range is divided into
	 * 3 parts, each part having a fixed PLL gain value.
	 */
	if (vcoFreq >= 30000)
		/*
		 * [300..max] MHz : 7
		 */
		return 7;
	else if (vcoFreq >= 18000)
		/*
		 * [180..300) MHz : 4
		 */
		return 4;
	else
		/*
		 * [0..180) MHz : 1
		 */
		return 1;
}
 
void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t mask;
 
	if (radeon_crtc->crtc_id)
		mask = (RADEON_CRTC2_EN |
			RADEON_CRTC2_DISP_DIS |
			RADEON_CRTC2_VSYNC_DIS |
			RADEON_CRTC2_HSYNC_DIS |
			RADEON_CRTC2_DISP_REQ_EN_B);
	else
		mask = (RADEON_CRTC_DISPLAY_DIS |
			RADEON_CRTC_VSYNC_DIS |
			RADEON_CRTC_HSYNC_DIS);
 
	switch (mode) {
	case DRM_MODE_DPMS_ON:
		if (radeon_crtc->crtc_id)
			WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
		else {
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
									 RADEON_CRTC_DISP_REQ_EN_B));
			WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
		}
//       drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
		radeon_crtc_load_lut(crtc);
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
//       drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
		if (radeon_crtc->crtc_id)
			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
		else {
			WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
										    RADEON_CRTC_DISP_REQ_EN_B));
			WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
		}
		break;
	}
}
 
/* properly set crtc bpp when using atombios */
void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	int format;
	uint32_t crtc_gen_cntl;
	uint32_t disp_merge_cntl;
	uint32_t crtc_pitch;
 
	switch (crtc->fb->bits_per_pixel) {
	case 8:
		format = 2;
		break;
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return;
	}
 
	crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
			((crtc->fb->bits_per_pixel * 8) - 1)) /
		       (crtc->fb->bits_per_pixel * 8));
	crtc_pitch |= crtc_pitch << 16;
 
	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 
	switch (radeon_crtc->crtc_id) {
	case 0:
		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 
		crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
		crtc_gen_cntl |= (format << 8);
		crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
		WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
		break;
	case 1:
		disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
		WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
 
		crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
		crtc_gen_cntl |= (format << 8);
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
		WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
		WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
		break;
	}
}
 
int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
			 struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct radeon_framebuffer *radeon_fb;
	struct drm_gem_object *obj;
	uint64_t base;
	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
	uint32_t crtc_pitch, pitch_pixels;
	uint32_t tiling_flags;
	int format;
	uint32_t gen_cntl_reg, gen_cntl_val;
 
	DRM_DEBUG("\n");
 
	radeon_fb = to_radeon_framebuffer(crtc->fb);
 
	switch (crtc->fb->bits_per_pixel) {
	case 8:
		format = 2;
		break;
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return false;
	}
 
	obj = radeon_fb->obj;
//   if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
//       return -EINVAL;
//   }
    base = rdev->mc.vram_location;
 
	/* if scanout was in GTT this really wouldn't work */
	/* crtc offset is from display base addr not FB location */
	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
 
	base -= radeon_crtc->legacy_display_base_addr;
 
	crtc_offset_cntl = 0;
 
	pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
	crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
			((crtc->fb->bits_per_pixel * 8) - 1)) /
		       (crtc->fb->bits_per_pixel * 8));
	crtc_pitch |= crtc_pitch << 16;
 
//	radeon_object_get_tiling_flags(obj->driver_private,
//				       &tiling_flags, NULL);
	if (tiling_flags & RADEON_TILING_MICRO)
		DRM_ERROR("trying to scanout microtiled buffer\n");
 
	if (tiling_flags & RADEON_TILING_MACRO) {
		if (ASIC_IS_R300(rdev))
			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
					     R300_CRTC_MICRO_TILE_BUFFER_DIS |
					     R300_CRTC_MACRO_TILE_EN);
		else
			crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
	} else {
		if (ASIC_IS_R300(rdev))
			crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
					      R300_CRTC_MICRO_TILE_BUFFER_DIS |
					      R300_CRTC_MACRO_TILE_EN);
		else
			crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
	}
 
	if (tiling_flags & RADEON_TILING_MACRO) {
		if (ASIC_IS_R300(rdev)) {
			crtc_tile_x0_y0 = x | (y << 16);
			base &= ~0x7ff;
		} else {
			int byteshift = crtc->fb->bits_per_pixel >> 4;
			int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
			base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
			crtc_offset_cntl |= (y % 16);
		}
	} else {
		int offset = y * pitch_pixels + x;
		switch (crtc->fb->bits_per_pixel) {
		case 8:
			offset *= 1;
			break;
		case 15:
		case 16:
			offset *= 2;
			break;
		case 24:
			offset *= 3;
			break;
		case 32:
			offset *= 4;
			break;
		default:
			return false;
		}
		base += offset;
	}
 
	base &= ~7;
 
	if (radeon_crtc->crtc_id == 1)
		gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
	else
		gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 
	gen_cntl_val = RREG32(gen_cntl_reg);
	gen_cntl_val &= ~(0xf << 8);
	gen_cntl_val |= (format << 8);
	WREG32(gen_cntl_reg, gen_cntl_val);
 
	crtc_offset = (u32)base;
 
	WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 
	if (ASIC_IS_R300(rdev)) {
		if (radeon_crtc->crtc_id)
			WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
		else
			WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
	}
	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 
	if (old_fb && old_fb != crtc->fb) {
		radeon_fb = to_radeon_framebuffer(old_fb);
//       radeon_gem_object_unpin(radeon_fb->obj);
	}
	return 0;
}
 
static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_encoder *encoder;
	int format;
	int hsync_start;
	int hsync_wid;
	int vsync_wid;
	uint32_t crtc_h_total_disp;
	uint32_t crtc_h_sync_strt_wid;
	uint32_t crtc_v_total_disp;
	uint32_t crtc_v_sync_strt_wid;
	bool is_tv = false;
 
	DRM_DEBUG("\n");
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
				is_tv = true;
				DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
				break;
			}
		}
	}
 
	switch (crtc->fb->bits_per_pixel) {
	case 8:
		format = 2;
		break;
	case 15:      /*  555 */
		format = 3;
		break;
	case 16:      /*  565 */
		format = 4;
		break;
	case 24:      /*  RGB */
		format = 5;
		break;
	case 32:      /* xRGB */
		format = 6;
		break;
	default:
		return false;
	}
 
	crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
			     | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 
	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
	if (!hsync_wid)
		hsync_wid = 1;
	hsync_start = mode->crtc_hsync_start - 8;
 
	crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
				| ((hsync_wid & 0x3f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
				   ? RADEON_CRTC_H_SYNC_POL
				   : 0));
 
	/* This works for double scan mode. */
	crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
			     | ((mode->crtc_vdisplay - 1) << 16));
 
	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
	if (!vsync_wid)
		vsync_wid = 1;
 
	crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
				| ((vsync_wid & 0x1f) << 16)
				| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
				   ? RADEON_CRTC_V_SYNC_POL
				   : 0));
 
	/* TODO -> Dell Server */
	if (0) {
		uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 
		dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 
		/* For CRT on DAC2, don't turn it on if BIOS didn't
		   enable it, even it's detected.
		*/
		disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
		tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
		tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 
		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
	}
 
	if (radeon_crtc->crtc_id) {
		uint32_t crtc2_gen_cntl;
		uint32_t disp2_merge_cntl;
 
		/* check to see if TV DAC is enabled for another crtc and keep it enabled */
		if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
			crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
		else
			crtc2_gen_cntl = 0;
 
		crtc2_gen_cntl |= ((format << 8)
				   | RADEON_CRTC2_VSYNC_DIS
				   | RADEON_CRTC2_HSYNC_DIS
				   | RADEON_CRTC2_DISP_DIS
				   | RADEON_CRTC2_DISP_REQ_EN_B
				   | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
				      ? RADEON_CRTC2_DBL_SCAN_EN
				      : 0)
				   | ((mode->flags & DRM_MODE_FLAG_CSYNC)
				      ? RADEON_CRTC2_CSYNC_EN
				      : 0)
				   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
				      ? RADEON_CRTC2_INTERLACE_EN
				      : 0));
 
		disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 
		WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
	} else {
		uint32_t crtc_gen_cntl;
		uint32_t crtc_ext_cntl;
		uint32_t disp_merge_cntl;
 
		crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
				 | (format << 8)
				 | RADEON_CRTC_DISP_REQ_EN_B
				 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
				    ? RADEON_CRTC_DBL_SCAN_EN
				    : 0)
				 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
				    ? RADEON_CRTC_CSYNC_EN
				    : 0)
				 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
				    ? RADEON_CRTC_INTERLACE_EN
				    : 0));
 
		crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
				  RADEON_CRTC_VSYNC_DIS |
				  RADEON_CRTC_HSYNC_DIS |
				  RADEON_CRTC_DISPLAY_DIS);
 
		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 
		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
		WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
		WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
	}
 
	if (is_tv)
		radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
						 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
						 &crtc_v_sync_strt_wid);
 
	WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
	WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
	WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
	WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 
	return true;
}
 
static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_encoder *encoder;
	uint32_t feedback_div = 0;
	uint32_t frac_fb_div = 0;
	uint32_t reference_div = 0;
	uint32_t post_divider = 0;
	uint32_t freq = 0;
	uint8_t pll_gain;
	int pll_flags = RADEON_PLL_LEGACY;
	bool use_bios_divs = false;
	/* PLL registers */
	uint32_t pll_ref_div = 0;
	uint32_t pll_fb_post_div = 0;
	uint32_t htotal_cntl = 0;
	bool is_tv = false;
	struct radeon_pll *pll;
 
	struct {
		int divider;
		int bitvalue;
	} *post_div, post_divs[]   = {
		/* From RAGE 128 VR/RAGE 128 GL Register
		 * Reference Manual (Technical Reference
		 * Manual P/N RRG-G04100-C Rev. 0.04), page
		 * 3-17 (PLL_DIV_[3:0]).
		 */
		{  1, 0 },              /* VCLK_SRC                 */
		{  2, 1 },              /* VCLK_SRC/2               */
		{  4, 2 },              /* VCLK_SRC/4               */
		{  8, 3 },              /* VCLK_SRC/8               */
		{  3, 4 },              /* VCLK_SRC/3               */
		{ 16, 5 },              /* VCLK_SRC/16              */
		{  6, 6 },              /* VCLK_SRC/6               */
		{ 12, 7 },              /* VCLK_SRC/12              */
		{  0, 0 }
	};
 
	if (radeon_crtc->crtc_id)
		pll = &rdev->clock.p2pll;
	else
		pll = &rdev->clock.p1pll;
 
	if (mode->clock > 200000) /* range limits??? */
		pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
	else
		pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
				is_tv = true;
				break;
			}
 
			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
				pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
			if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
				struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
				struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
				if (lvds) {
					if (lvds->use_bios_dividers) {
						pll_ref_div = lvds->panel_ref_divider;
						pll_fb_post_div   = (lvds->panel_fb_divider |
								     (lvds->panel_post_divider << 16));
						htotal_cntl  = 0;
						use_bios_divs = true;
					}
				}
				pll_flags |= RADEON_PLL_USE_REF_DIV;
			}
		}
	}
 
	DRM_DEBUG("\n");
 
	if (!use_bios_divs) {
		radeon_compute_pll(pll, mode->clock,
				   &freq, &feedback_div, &frac_fb_div,
				   &reference_div, &post_divider,
				   pll_flags);
 
		for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
			if (post_div->divider == post_divider)
				break;
		}
 
		if (!post_div->divider)
			post_div = &post_divs[0];
 
		DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
			  (unsigned)freq,
			  feedback_div,
			  reference_div,
			  post_divider);
 
		pll_ref_div   = reference_div;
#if defined(__powerpc__) && (0) /* TODO */
		/* apparently programming this otherwise causes a hang??? */
		if (info->MacModel == RADEON_MAC_IBOOK)
			pll_fb_post_div = 0x000600ad;
		else
#endif
			pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 
		htotal_cntl    = mode->htotal & 0x7;
 
	}
 
	pll_gain = radeon_compute_pll_gain(pll->reference_freq,
					   pll_ref_div & 0x3ff,
					   pll_fb_post_div & 0x7ff);
 
	if (radeon_crtc->crtc_id) {
		uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
					  ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
					 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 
		if (is_tv) {
			radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
						     &pll_ref_div, &pll_fb_post_div,
						     &pixclks_cntl);
		}
 
		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
			     RADEON_PIX2CLK_SRC_SEL_CPUCLK,
			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 
		WREG32_PLL_P(RADEON_P2PLL_CNTL,
			     RADEON_P2PLL_RESET
			     | RADEON_P2PLL_ATOMIC_UPDATE_EN
			     | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
			     ~(RADEON_P2PLL_RESET
			       | RADEON_P2PLL_ATOMIC_UPDATE_EN
			       | RADEON_P2PLL_PVG_MASK));
 
		WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
			     pll_ref_div,
			     ~RADEON_P2PLL_REF_DIV_MASK);
 
		WREG32_PLL_P(RADEON_P2PLL_DIV_0,
			     pll_fb_post_div,
			     ~RADEON_P2PLL_FB0_DIV_MASK);
 
		WREG32_PLL_P(RADEON_P2PLL_DIV_0,
			     pll_fb_post_div,
			     ~RADEON_P2PLL_POST0_DIV_MASK);
 
		radeon_pll2_write_update(dev);
		radeon_pll2_wait_for_read_update_complete(dev);
 
		WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 
		WREG32_PLL_P(RADEON_P2PLL_CNTL,
			     0,
			     ~(RADEON_P2PLL_RESET
			       | RADEON_P2PLL_SLEEP
			       | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 
		DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
			  (unsigned)pll_ref_div,
			  (unsigned)pll_fb_post_div,
			  (unsigned)htotal_cntl,
			  RREG32_PLL(RADEON_P2PLL_CNTL));
		DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
			  (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
			  (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
			  (unsigned)((pll_fb_post_div &
				      RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 
		mdelay(50); /* Let the clock to lock */
 
		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
			     RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 
		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
	} else {
		uint32_t pixclks_cntl;
 
 
		if (is_tv) {
			pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
			radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
						     &pll_fb_post_div, &pixclks_cntl);
		}
 
		if (rdev->flags & RADEON_IS_MOBILITY) {
			/* A temporal workaround for the occational blanking on certain laptop panels.
			   This appears to related to the PLL divider registers (fail to lock?).
			   It occurs even when all dividers are the same with their old settings.
			   In this case we really don't need to fiddle with PLL registers.
			   By doing this we can avoid the blanking problem with some panels.
			*/
			if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
			    (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
						 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
				WREG32_P(RADEON_CLOCK_CNTL_INDEX,
					 RADEON_PLL_DIV_SEL,
					 ~(RADEON_PLL_DIV_SEL));
				r100_pll_errata_after_index(rdev);
				return;
			}
		}
 
		WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
			     RADEON_VCLK_SRC_SEL_CPUCLK,
			     ~(RADEON_VCLK_SRC_SEL_MASK));
		WREG32_PLL_P(RADEON_PPLL_CNTL,
			     RADEON_PPLL_RESET
			     | RADEON_PPLL_ATOMIC_UPDATE_EN
			     | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
			     | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
			     ~(RADEON_PPLL_RESET
			       | RADEON_PPLL_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_PVG_MASK));
 
		WREG32_P(RADEON_CLOCK_CNTL_INDEX,
			 RADEON_PLL_DIV_SEL,
			 ~(RADEON_PLL_DIV_SEL));
		r100_pll_errata_after_index(rdev);
 
		if (ASIC_IS_R300(rdev) ||
		    (rdev->family == CHIP_RS300) ||
		    (rdev->family == CHIP_RS400) ||
		    (rdev->family == CHIP_RS480)) {
			if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
				/* When restoring console mode, use saved PPLL_REF_DIV
				 * setting.
				 */
				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
					     pll_ref_div,
					     0);
			} else {
				/* R300 uses ref_div_acc field as real ref divider */
				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
					     (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
					     ~R300_PPLL_REF_DIV_ACC_MASK);
			}
		} else
			WREG32_PLL_P(RADEON_PPLL_REF_DIV,
				     pll_ref_div,
				     ~RADEON_PPLL_REF_DIV_MASK);
 
		WREG32_PLL_P(RADEON_PPLL_DIV_3,
			     pll_fb_post_div,
			     ~RADEON_PPLL_FB3_DIV_MASK);
 
		WREG32_PLL_P(RADEON_PPLL_DIV_3,
			     pll_fb_post_div,
			     ~RADEON_PPLL_POST3_DIV_MASK);
 
		radeon_pll_write_update(dev);
		radeon_pll_wait_for_read_update_complete(dev);
 
		WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 
		WREG32_PLL_P(RADEON_PPLL_CNTL,
			     0,
			     ~(RADEON_PPLL_RESET
			       | RADEON_PPLL_SLEEP
			       | RADEON_PPLL_ATOMIC_UPDATE_EN
			       | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 
		DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
			  pll_ref_div,
			  pll_fb_post_div,
			  (unsigned)htotal_cntl,
			  RREG32_PLL(RADEON_PPLL_CNTL));
		DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
			  pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
			  pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
			  (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 
		mdelay(50); /* Let the clock to lock */
 
		WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
			     RADEON_VCLK_SRC_SEL_PPLLCLK,
			     ~(RADEON_VCLK_SRC_SEL_MASK));
 
		if (is_tv)
			WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
	}
}
 
static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
		return false;
	return true;
}
 
static int radeon_crtc_mode_set(struct drm_crtc *crtc,
				 struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode,
				 int x, int y, struct drm_framebuffer *old_fb)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
 
	/* TODO TV */
	radeon_crtc_set_base(crtc, x, y, old_fb);
	radeon_set_crtc_timing(crtc, adjusted_mode);
	radeon_set_pll(crtc, adjusted_mode);
	radeon_bandwidth_update(rdev);
	if (radeon_crtc->crtc_id == 0) {
		radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
	} else {
		if (radeon_crtc->rmx_type != RMX_OFF) {
			/* FIXME: only first crtc has rmx what should we
			 * do ?
			 */
			DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
		}
	}
	return 0;
}
 
static void radeon_crtc_prepare(struct drm_crtc *crtc)
{
	radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
}
 
static void radeon_crtc_commit(struct drm_crtc *crtc)
{
	radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
}
 
static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
	.dpms = radeon_crtc_dpms,
	.mode_fixup = radeon_crtc_mode_fixup,
	.mode_set = radeon_crtc_mode_set,
	.mode_set_base = radeon_crtc_set_base,
	.prepare = radeon_crtc_prepare,
	.commit = radeon_crtc_commit,
	.load_lut = radeon_crtc_load_lut,
};
 
 
void radeon_legacy_init_crtc(struct drm_device *dev,
			       struct radeon_crtc *radeon_crtc)
{
	if (radeon_crtc->crtc_id == 1)
		radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
	drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
}
 
>
 
>
>
>

Rev 1221	Rev 1246
1	/*	1	/*
2	* Copyright 2007-8 Advanced Micro Devices, Inc.	2	* Copyright 2007-8 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),	6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation	7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the	9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:	10	* Software is furnished to do so, subject to the following conditions:
11	*	11	*
12	* The above copyright notice and this permission notice shall be included in	12	* The above copyright notice and this permission notice shall be included in
13	* all copies or substantial portions of the Software.	13	* all copies or substantial portions of the Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21	* OTHER DEALINGS IN THE SOFTWARE.	21	* OTHER DEALINGS IN THE SOFTWARE.
22	*	22	*
23	* Authors: Dave Airlie	23	* Authors: Dave Airlie
24	* Alex Deucher	24	* Alex Deucher
25	*/	25	*/
26	#include	26	#include
27	#include	27	#include
28	#include	28	#include
29	#include "radeon_fixed.h"	29	#include "radeon_fixed.h"
30	#include "radeon.h"	30	#include "radeon.h"
31	#include "atom.h"	31	#include "atom.h"
32		32
33	static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,	33	static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
34	struct drm_display_mode *mode,	34	struct drm_display_mode *mode,
35	struct drm_display_mode *adjusted_mode)	35	struct drm_display_mode *adjusted_mode)
36	{	36	{
37	struct drm_device *dev = crtc->dev;	37	struct drm_device *dev = crtc->dev;
38	struct radeon_device *rdev = dev->dev_private;	38	struct radeon_device *rdev = dev->dev_private;
39	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	39	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40	int xres = mode->hdisplay;	40	int xres = mode->hdisplay;
41	int yres = mode->vdisplay;	41	int yres = mode->vdisplay;
42	bool hscale = true, vscale = true;	42	bool hscale = true, vscale = true;
43	int hsync_wid;	43	int hsync_wid;
44	int vsync_wid;	44	int vsync_wid;
45	int hsync_start;	45	int hsync_start;
46	int blank_width;	46	int blank_width;
47	u32 scale, inc, crtc_more_cntl;	47	u32 scale, inc, crtc_more_cntl;
48	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;	48	u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
49	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;	49	u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
50	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;	50	u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
51	struct radeon_native_mode *native_mode = &radeon_crtc->native_mode;	51	struct radeon_native_mode *native_mode = &radeon_crtc->native_mode;
52		52
53	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &	53	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
54	(RADEON_VERT_STRETCH_RESERVED \|	54	(RADEON_VERT_STRETCH_RESERVED \|
55	RADEON_VERT_AUTO_RATIO_INC);	55	RADEON_VERT_AUTO_RATIO_INC);
56	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &	56	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
57	(RADEON_HORZ_FP_LOOP_STRETCH \|	57	(RADEON_HORZ_FP_LOOP_STRETCH \|
58	RADEON_HORZ_AUTO_RATIO_INC);	58	RADEON_HORZ_AUTO_RATIO_INC);
59		59
60	crtc_more_cntl = 0;	60	crtc_more_cntl = 0;
61	if ((rdev->family == CHIP_RS100) \|\|	61	if ((rdev->family == CHIP_RS100) \|\|
62	(rdev->family == CHIP_RS200)) {	62	(rdev->family == CHIP_RS200)) {
63	/* This is to workaround the asic bug for RMX, some versions	63	/* This is to workaround the asic bug for RMX, some versions
64	of BIOS dosen't have this register initialized correctly. */	64	of BIOS dosen't have this register initialized correctly. */
65	crtc_more_cntl \|= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;	65	crtc_more_cntl \|= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
66	}	66	}
67		67
68		68
69	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)	69	fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
70	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));	70	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
71		71
72	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;	72	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
73	if (!hsync_wid)	73	if (!hsync_wid)
74	hsync_wid = 1;	74	hsync_wid = 1;
75	hsync_start = mode->crtc_hsync_start - 8;	75	hsync_start = mode->crtc_hsync_start - 8;
76		76
77	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)	77	fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
78	\| ((hsync_wid & 0x3f) << 16)	78	\| ((hsync_wid & 0x3f) << 16)
79	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)	79	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
80	? RADEON_CRTC_H_SYNC_POL	80	? RADEON_CRTC_H_SYNC_POL
81	: 0));	81	: 0));
82		82
83	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)	83	fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
84	\| ((mode->crtc_vdisplay - 1) << 16));	84	\| ((mode->crtc_vdisplay - 1) << 16));
85		85
86	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;	86	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
87	if (!vsync_wid)	87	if (!vsync_wid)
88	vsync_wid = 1;	88	vsync_wid = 1;
89		89
90	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)	90	fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
91	\| ((vsync_wid & 0x1f) << 16)	91	\| ((vsync_wid & 0x1f) << 16)
92	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)	92	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
93	? RADEON_CRTC_V_SYNC_POL	93	? RADEON_CRTC_V_SYNC_POL
94	: 0));	94	: 0));
95		95
96	fp_horz_vert_active = 0;	96	fp_horz_vert_active = 0;
97		97
98	if (native_mode->panel_xres == 0 \|\|	98	if (native_mode->panel_xres == 0 \|\|
99	native_mode->panel_yres == 0) {	99	native_mode->panel_yres == 0) {
100	hscale = false;	100	hscale = false;
101	vscale = false;	101	vscale = false;
102	} else {	102	} else {
103	if (xres > native_mode->panel_xres)	103	if (xres > native_mode->panel_xres)
104	xres = native_mode->panel_xres;	104	xres = native_mode->panel_xres;
105	if (yres > native_mode->panel_yres)	105	if (yres > native_mode->panel_yres)
106	yres = native_mode->panel_yres;	106	yres = native_mode->panel_yres;
107		107
108	if (xres == native_mode->panel_xres)	108	if (xres == native_mode->panel_xres)
109	hscale = false;	109	hscale = false;
110	if (yres == native_mode->panel_yres)	110	if (yres == native_mode->panel_yres)
111	vscale = false;	111	vscale = false;
112	}	112	}
113		113
114	switch (radeon_crtc->rmx_type) {	114	switch (radeon_crtc->rmx_type) {
115	case RMX_FULL:	115	case RMX_FULL:
116	case RMX_ASPECT:	116	case RMX_ASPECT:
117	if (!hscale)	117	if (!hscale)
118	fp_horz_stretch \|= ((xres/8-1) << 16);	118	fp_horz_stretch \|= ((xres/8-1) << 16);
119	else {	119	else {
120	inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;	120	inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
121	scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)	121	scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
122	/ native_mode->panel_xres + 1;	122	/ native_mode->panel_xres + 1;
123	fp_horz_stretch \|= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) \|	123	fp_horz_stretch \|= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) \|
124	RADEON_HORZ_STRETCH_BLEND \|	124	RADEON_HORZ_STRETCH_BLEND \|
125	RADEON_HORZ_STRETCH_ENABLE \|	125	RADEON_HORZ_STRETCH_ENABLE \|
126	((native_mode->panel_xres/8-1) << 16));	126	((native_mode->panel_xres/8-1) << 16));
127	}	127	}
128		128
129	if (!vscale)	129	if (!vscale)
130	fp_vert_stretch \|= ((yres-1) << 12);	130	fp_vert_stretch \|= ((yres-1) << 12);
131	else {	131	else {
132	inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;	132	inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
133	scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)	133	scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
134	/ native_mode->panel_yres + 1;	134	/ native_mode->panel_yres + 1;
135	fp_vert_stretch \|= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) \|	135	fp_vert_stretch \|= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) \|
136	RADEON_VERT_STRETCH_ENABLE \|	136	RADEON_VERT_STRETCH_ENABLE \|
137	RADEON_VERT_STRETCH_BLEND \|	137	RADEON_VERT_STRETCH_BLEND \|
138	((native_mode->panel_yres-1) << 12));	138	((native_mode->panel_yres-1) << 12));
139	}	139	}
140	break;	140	break;
141	case RMX_CENTER:	141	case RMX_CENTER:
142	fp_horz_stretch \|= ((xres/8-1) << 16);	142	fp_horz_stretch \|= ((xres/8-1) << 16);
143	fp_vert_stretch \|= ((yres-1) << 12);	143	fp_vert_stretch \|= ((yres-1) << 12);
144		144
145	crtc_more_cntl \|= (RADEON_CRTC_AUTO_HORZ_CENTER_EN \|	145	crtc_more_cntl \|= (RADEON_CRTC_AUTO_HORZ_CENTER_EN \|
146	RADEON_CRTC_AUTO_VERT_CENTER_EN);	146	RADEON_CRTC_AUTO_VERT_CENTER_EN);
147		147
148	blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;	148	blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
149	if (blank_width > 110)	149	if (blank_width > 110)
150	blank_width = 110;	150	blank_width = 110;
151		151
152	fp_crtc_h_total_disp = (((blank_width) & 0x3ff)	152	fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
153	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));	153	\| ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
154		154
155	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;	155	hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
156	if (!hsync_wid)	156	if (!hsync_wid)
157	hsync_wid = 1;	157	hsync_wid = 1;
158		158
159	fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)	159	fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
160	\| ((hsync_wid & 0x3f) << 16)	160	\| ((hsync_wid & 0x3f) << 16)
161	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)	161	\| ((mode->flags & DRM_MODE_FLAG_NHSYNC)
162	? RADEON_CRTC_H_SYNC_POL	162	? RADEON_CRTC_H_SYNC_POL
163	: 0));	163	: 0));
164		164
165	fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)	165	fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
166	\| ((mode->crtc_vdisplay - 1) << 16));	166	\| ((mode->crtc_vdisplay - 1) << 16));
167		167
168	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;	168	vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
169	if (!vsync_wid)	169	if (!vsync_wid)
170	vsync_wid = 1;	170	vsync_wid = 1;
171		171
172	fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)	172	fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
173	\| ((vsync_wid & 0x1f) << 16)	173	\| ((vsync_wid & 0x1f) << 16)
174	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)	174	\| ((mode->flags & DRM_MODE_FLAG_NVSYNC)
175	? RADEON_CRTC_V_SYNC_POL	175	? RADEON_CRTC_V_SYNC_POL
176	: 0)));	176	: 0)));
177		177
178	fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) \|	178	fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) \|
179	(((native_mode->panel_xres / 8) & 0x1ff) << 16));	179	(((native_mode->panel_xres / 8) & 0x1ff) << 16));
180	break;	180	break;
181	case RMX_OFF:	181	case RMX_OFF:
182	default:	182	default:
183	fp_horz_stretch \|= ((xres/8-1) << 16);	183	fp_horz_stretch \|= ((xres/8-1) << 16);
184	fp_vert_stretch \|= ((yres-1) << 12);	184	fp_vert_stretch \|= ((yres-1) << 12);
185	break;	185	break;
186	}	186	}
187		187
188	WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);	188	WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
189	WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);	189	WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
190	WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);	190	WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
191	WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);	191	WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
192	WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);	192	WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
193	WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);	193	WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
194	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);	194	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
195	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);	195	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
196	}	196	}
197		197
198	void radeon_restore_common_regs(struct drm_device *dev)	198	void radeon_restore_common_regs(struct drm_device *dev)
199	{	199	{
200	/* don't need this yet */	200	/* don't need this yet */
201	}	201	}
202		202
203	static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)	203	static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
204	{	204	{
205	struct radeon_device *rdev = dev->dev_private;	205	struct radeon_device *rdev = dev->dev_private;
206	int i = 0;	206	int i = 0;
207		207
208	/* FIXME: Certain revisions of R300 can't recover here. Not sure of	208	/* FIXME: Certain revisions of R300 can't recover here. Not sure of
209	the cause yet, but this workaround will mask the problem for now.	209	the cause yet, but this workaround will mask the problem for now.
210	Other chips usually will pass at the very first test, so the	210	Other chips usually will pass at the very first test, so the
211	workaround shouldn't have any effect on them. */	211	workaround shouldn't have any effect on them. */
212	for (i = 0;	212	for (i = 0;
213	(i < 10000 &&	213	(i < 10000 &&
214	RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);	214	RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
215	i++);	215	i++);
216	}	216	}
217		217
218	static void radeon_pll_write_update(struct drm_device *dev)	218	static void radeon_pll_write_update(struct drm_device *dev)
219	{	219	{
220	struct radeon_device *rdev = dev->dev_private;	220	struct radeon_device *rdev = dev->dev_private;
221		221
222	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);	222	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
223		223
224	WREG32_PLL_P(RADEON_PPLL_REF_DIV,	224	WREG32_PLL_P(RADEON_PPLL_REF_DIV,
225	RADEON_PPLL_ATOMIC_UPDATE_W,	225	RADEON_PPLL_ATOMIC_UPDATE_W,
226	~(RADEON_PPLL_ATOMIC_UPDATE_W));	226	~(RADEON_PPLL_ATOMIC_UPDATE_W));
227	}	227	}
228		228
229	static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)	229	static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
230	{	230	{
231	struct radeon_device *rdev = dev->dev_private;	231	struct radeon_device *rdev = dev->dev_private;
232	int i = 0;	232	int i = 0;
233		233
234		234
235	/* FIXME: Certain revisions of R300 can't recover here. Not sure of	235	/* FIXME: Certain revisions of R300 can't recover here. Not sure of
236	the cause yet, but this workaround will mask the problem for now.	236	the cause yet, but this workaround will mask the problem for now.
237	Other chips usually will pass at the very first test, so the	237	Other chips usually will pass at the very first test, so the
238	workaround shouldn't have any effect on them. */	238	workaround shouldn't have any effect on them. */
239	for (i = 0;	239	for (i = 0;
240	(i < 10000 &&	240	(i < 10000 &&
241	RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);	241	RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
242	i++);	242	i++);
243	}	243	}
244		244
245	static void radeon_pll2_write_update(struct drm_device *dev)	245	static void radeon_pll2_write_update(struct drm_device *dev)
246	{	246	{
247	struct radeon_device *rdev = dev->dev_private;	247	struct radeon_device *rdev = dev->dev_private;
248		248
249	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);	249	while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
250		250
251	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,	251	WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
252	RADEON_P2PLL_ATOMIC_UPDATE_W,	252	RADEON_P2PLL_ATOMIC_UPDATE_W,
253	~(RADEON_P2PLL_ATOMIC_UPDATE_W));	253	~(RADEON_P2PLL_ATOMIC_UPDATE_W));
254	}	254	}
255		255
256	static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,	256	static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
257	uint16_t fb_div)	257	uint16_t fb_div)
258	{	258	{
259	unsigned int vcoFreq;	259	unsigned int vcoFreq;
260		260
261	if (!ref_div)	261	if (!ref_div)
262	return 1;	262	return 1;
263		263
264	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;	264	vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
265		265
266	/*	266	/*
267	* This is horribly crude: the VCO frequency range is divided into	267	* This is horribly crude: the VCO frequency range is divided into
268	* 3 parts, each part having a fixed PLL gain value.	268	* 3 parts, each part having a fixed PLL gain value.
269	*/	269	*/
270	if (vcoFreq >= 30000)	270	if (vcoFreq >= 30000)
271	/*	271	/*
272	* [300..max] MHz : 7	272	* [300..max] MHz : 7
273	*/	273	*/
274	return 7;	274	return 7;
275	else if (vcoFreq >= 18000)	275	else if (vcoFreq >= 18000)
276	/*	276	/*
277	* [180..300) MHz : 4	277	* [180..300) MHz : 4
278	*/	278	*/
279	return 4;	279	return 4;
280	else	280	else
281	/*	281	/*
282	* [0..180) MHz : 1	282	* [0..180) MHz : 1
283	*/	283	*/
284	return 1;	284	return 1;
285	}	285	}
286		286
287	void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)	287	void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
288	{	288	{
289	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	289	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
290	struct drm_device *dev = crtc->dev;	290	struct drm_device *dev = crtc->dev;
291	struct radeon_device *rdev = dev->dev_private;	291	struct radeon_device *rdev = dev->dev_private;
292	uint32_t mask;	292	uint32_t mask;
293		293
294	if (radeon_crtc->crtc_id)	294	if (radeon_crtc->crtc_id)
295	mask = (RADEON_CRTC2_EN \|	295	mask = (RADEON_CRTC2_EN \|
296	RADEON_CRTC2_DISP_DIS \|	296	RADEON_CRTC2_DISP_DIS \|
297	RADEON_CRTC2_VSYNC_DIS \|	297	RADEON_CRTC2_VSYNC_DIS \|
298	RADEON_CRTC2_HSYNC_DIS \|	298	RADEON_CRTC2_HSYNC_DIS \|
299	RADEON_CRTC2_DISP_REQ_EN_B);	299	RADEON_CRTC2_DISP_REQ_EN_B);
300	else	300	else
301	mask = (RADEON_CRTC_DISPLAY_DIS \|	301	mask = (RADEON_CRTC_DISPLAY_DIS \|
302	RADEON_CRTC_VSYNC_DIS \|	302	RADEON_CRTC_VSYNC_DIS \|
303	RADEON_CRTC_HSYNC_DIS);	303	RADEON_CRTC_HSYNC_DIS);
304		304
305	switch (mode) {	305	switch (mode) {
306	case DRM_MODE_DPMS_ON:	306	case DRM_MODE_DPMS_ON:
307	if (radeon_crtc->crtc_id)	307	if (radeon_crtc->crtc_id)
308	WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);	308	WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
309	else {	309	else {
310	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN \|	310	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN \|
311	RADEON_CRTC_DISP_REQ_EN_B));	311	RADEON_CRTC_DISP_REQ_EN_B));
312	WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);	312	WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
313	}	313	}
314	// drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);	314	// drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
315	radeon_crtc_load_lut(crtc);	315	radeon_crtc_load_lut(crtc);
316	break;	316	break;
317	case DRM_MODE_DPMS_STANDBY:	317	case DRM_MODE_DPMS_STANDBY:
318	case DRM_MODE_DPMS_SUSPEND:	318	case DRM_MODE_DPMS_SUSPEND:
319	case DRM_MODE_DPMS_OFF:	319	case DRM_MODE_DPMS_OFF:
320	// drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);	320	// drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
321	if (radeon_crtc->crtc_id)	321	if (radeon_crtc->crtc_id)
322	WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);	322	WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
323	else {	323	else {
324	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN \|	324	WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN \|
325	RADEON_CRTC_DISP_REQ_EN_B));	325	RADEON_CRTC_DISP_REQ_EN_B));
326	WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);	326	WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
327	}	327	}
328	break;	328	break;
329	}	329	}
330	}	330	}
331		331
332	/* properly set crtc bpp when using atombios */	332	/* properly set crtc bpp when using atombios */
333	void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)	333	void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
334	{	334	{
335	struct drm_device *dev = crtc->dev;	335	struct drm_device *dev = crtc->dev;
336	struct radeon_device *rdev = dev->dev_private;	336	struct radeon_device *rdev = dev->dev_private;
337	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	337	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
338	int format;	338	int format;
339	uint32_t crtc_gen_cntl;	339	uint32_t crtc_gen_cntl;
340	uint32_t disp_merge_cntl;	340	uint32_t disp_merge_cntl;
341	uint32_t crtc_pitch;	341	uint32_t crtc_pitch;
342		342
343	switch (crtc->fb->bits_per_pixel) {	343	switch (crtc->fb->bits_per_pixel) {
344	case 8:	344	case 8:
345	format = 2;	345	format = 2;
346	break;	346	break;
347	case 15: /* 555 */	347	case 15: /* 555 */
348	format = 3;	348	format = 3;
349	break;	349	break;
350	case 16: /* 565 */	350	case 16: /* 565 */
351	format = 4;	351	format = 4;
352	break;	352	break;
353	case 24: /* RGB */	353	case 24: /* RGB */
354	format = 5;	354	format = 5;
355	break;	355	break;
356	case 32: /* xRGB */	356	case 32: /* xRGB */
357	format = 6;	357	format = 6;
358	break;	358	break;
359	default:	359	default:
360	return;	360	return;
361	}	361	}
362		362
363	crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +	363	crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
364	((crtc->fb->bits_per_pixel * 8) - 1)) /	364	((crtc->fb->bits_per_pixel * 8) - 1)) /
365	(crtc->fb->bits_per_pixel * 8));	365	(crtc->fb->bits_per_pixel * 8));
366	crtc_pitch \|= crtc_pitch << 16;	366	crtc_pitch \|= crtc_pitch << 16;
367		367
368	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);	368	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
369		369
370	switch (radeon_crtc->crtc_id) {	370	switch (radeon_crtc->crtc_id) {
371	case 0:	371	case 0:
372	disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);	372	disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
373	disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;	373	disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
374	WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);	374	WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
375		375
376	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;	376	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
377	crtc_gen_cntl \|= (format << 8);	377	crtc_gen_cntl \|= (format << 8);
378	crtc_gen_cntl \|= RADEON_CRTC_EXT_DISP_EN;	378	crtc_gen_cntl \|= RADEON_CRTC_EXT_DISP_EN;
379	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);	379	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
380	break;	380	break;
381	case 1:	381	case 1:
382	disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);	382	disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
383	disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;	383	disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
384	WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);	384	WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
385		385
386	crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;	386	crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
387	crtc_gen_cntl \|= (format << 8);	387	crtc_gen_cntl \|= (format << 8);
388	WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);	388	WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
389	WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));	389	WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
390	WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));	390	WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
391	break;	391	break;
392	}	392	}
393	}	393	}
394		394
395	int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,	395	int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
396	struct drm_framebuffer *old_fb)	396	struct drm_framebuffer *old_fb)
397	{	397	{
398	struct drm_device *dev = crtc->dev;	398	struct drm_device *dev = crtc->dev;
399	struct radeon_device *rdev = dev->dev_private;	399	struct radeon_device *rdev = dev->dev_private;
400	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);	400	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
401	struct radeon_framebuffer *radeon_fb;	401	struct radeon_framebuffer *radeon_fb;
402	struct drm_gem_object *obj;	402	struct drm_gem_object *obj;
403	uint64_t base;	403	uint64_t base;
404	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;	404	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
405	uint32_t crtc_pitch, pitch_pixels;	405	uint32_t crtc_pitch, pitch_pixels;
406	uint32_t tiling_flags;	406	uint32_t tiling_flags;
407	int format;	407	int format;
408	uint32_t gen_cntl_reg, gen_cntl_val;	408	uint32_t gen_cntl_reg, gen_cntl_val;
409		409
410	DRM_DEBUG("\n");	410	DRM_DEBUG("\n");
411		411
412	radeon_fb = to_radeon_framebuffer(crtc->fb);	412	radeon_fb = to_radeon_framebuffer(crtc->fb);
413		413
414	switch (crtc->fb->bits_per_pixel) {	414	switch (crtc->fb->bits_per_pixel) {
415	case 8:	415	case 8:
416	format = 2;	416	format = 2;
417	break;	417	break;
418	case 15: /* 555 */	418	case 15: /* 555 */
419	format = 3;	419	format = 3;
420	break;	420	break;
421	case 16: /* 565 */	421	case 16: /* 565 */
422	format = 4;	422	format = 4;
423	break;	423	break;
424	case 24: /* RGB */	424	case 24: /* RGB */
425	format = 5;	425	format = 5;
426	break;	426	break;
427	case 32: /* xRGB */	427	case 32: /* xRGB */
428	format = 6;	428	format = 6;
429	break;	429	break;
430	default:	430	default:
431	return false;	431	return false;
432	}	432	}
433		433
434	obj = radeon_fb->obj;	434	obj = radeon_fb->obj;
435	// if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {	435	// if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
436	// return -EINVAL;	436	// return -EINVAL;
437	// }	437	// }
-		438	base = rdev->mc.vram_location;
-		439
438	/* if scanout was in GTT this really wouldn't work */	440	/* if scanout was in GTT this really wouldn't work */
439	/* crtc offset is from display base addr not FB location */	441	/* crtc offset is from display base addr not FB location */
440	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;	442	radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
441		443
442	base -= radeon_crtc->legacy_display_base_addr;	444	base -= radeon_crtc->legacy_display_base_addr;
443		445
444	crtc_offset_cntl = 0;	446	crtc_offset_cntl = 0;
445		447
446	pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);	448	pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
447	crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +	449	crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
448	((crtc->fb->bits_per_pixel * 8) - 1)) /	450	((crtc->fb->bits_per_pixel * 8) - 1)) /
449	(crtc->fb->bits_per_pixel * 8));	451	(crtc->fb->bits_per_pixel * 8));
450	crtc_pitch \|= crtc_pitch << 16;	452	crtc_pitch \|= crtc_pitch << 16;
451		453
452	// radeon_object_get_tiling_flags(obj->driver_private,	454	// radeon_object_get_tiling_flags(obj->driver_private,
453	// &tiling_flags, NULL);	455	// &tiling_flags, NULL);
454	if (tiling_flags & RADEON_TILING_MICRO)	456	if (tiling_flags & RADEON_TILING_MICRO)
455	DRM_ERROR("trying to scanout microtiled buffer\n");	457	DRM_ERROR("trying to scanout microtiled buffer\n");
456		458
457	if (tiling_flags & RADEON_TILING_MACRO) {	459	if (tiling_flags & RADEON_TILING_MACRO) {
458	if (ASIC_IS_R300(rdev))	460	if (ASIC_IS_R300(rdev))
459	crtc_offset_cntl \|= (R300_CRTC_X_Y_MODE_EN \|	461	crtc_offset_cntl \|= (R300_CRTC_X_Y_MODE_EN \|
460	R300_CRTC_MICRO_TILE_BUFFER_DIS \|	462	R300_CRTC_MICRO_TILE_BUFFER_DIS \|
461	R300_CRTC_MACRO_TILE_EN);	463	R300_CRTC_MACRO_TILE_EN);
462	else	464	else
463	crtc_offset_cntl \|= RADEON_CRTC_TILE_EN;	465	crtc_offset_cntl \|= RADEON_CRTC_TILE_EN;
464	} else {	466	} else {
465	if (ASIC_IS_R300(rdev))	467	if (ASIC_IS_R300(rdev))
466	crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN \|	468	crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN \|
467	R300_CRTC_MICRO_TILE_BUFFER_DIS \|	469	R300_CRTC_MICRO_TILE_BUFFER_DIS \|
468	R300_CRTC_MACRO_TILE_EN);	470	R300_CRTC_MACRO_TILE_EN);
469	else	471	else
470	crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;	472	crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
471	}	473	}
472		474
473	if (tiling_flags & RADEON_TILING_MACRO) {	475	if (tiling_flags & RADEON_TILING_MACRO) {
474	if (ASIC_IS_R300(rdev)) {	476	if (ASIC_IS_R300(rdev)) {
475	crtc_tile_x0_y0 = x \| (y << 16);	477	crtc_tile_x0_y0 = x \| (y << 16);
476	base &= ~0x7ff;	478	base &= ~0x7ff;
477	} else {	479	} else {
478	int byteshift = crtc->fb->bits_per_pixel >> 4;	480	int byteshift = crtc->fb->bits_per_pixel >> 4;
479	int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;	481	int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
480	base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);	482	base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
481	crtc_offset_cntl \|= (y % 16);	483	crtc_offset_cntl \|= (y % 16);
482	}	484	}
483	} else {	485	} else {
484	int offset = y * pitch_pixels + x;	486	int offset = y * pitch_pixels + x;
485	switch (crtc->fb->bits_per_pixel) {	487	switch (crtc->fb->bits_per_pixel) {
486	case 8:	488	case 8:
487	offset *= 1;	489	offset *= 1;
488	break;	490	break;
489	case 15:	491	case 15:
490	case 16:	492	case 16:
491	offset *= 2;	493	offset *= 2;
492	break;	494	break;
493	case 24:	495	case 24:
494	offset *= 3;	496	offset *= 3;
495	break;	497	break;
496	case 32:	498	case 32:
497	offset *= 4;	499	offset *= 4;
498	break;	500	break;

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_legacy_crtc.c – Rev 1221 → 1246