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Rev 3192 Rev 3764
Line 60... Line 60...
60
 */
60
 */
61
static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
61
static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
62
{
62
{
63
	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
63
	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
64
	if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
64
	if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
-
 
65
		if (drv->cpu_addr) {
65
		*drv->cpu_addr = cpu_to_le32(seq);
66
		*drv->cpu_addr = cpu_to_le32(seq);
-
 
67
		}
66
	} else {
68
	} else {
67
		WREG32(drv->scratch_reg, seq);
69
		WREG32(drv->scratch_reg, seq);
68
	}
70
	}
69
}
71
}
Line 81... Line 83...
81
{
83
{
82
	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
84
	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
83
	u32 seq = 0;
85
	u32 seq = 0;
Line 84... Line 86...
84
 
86
 
-
 
87
	if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
85
	if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
88
		if (drv->cpu_addr) {
86
		seq = le32_to_cpu(*drv->cpu_addr);
89
		seq = le32_to_cpu(*drv->cpu_addr);
-
 
90
	} else {
-
 
91
			seq = lower_32_bits(atomic64_read(&drv->last_seq));
-
 
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		}
87
	} else {
93
	} else {
88
		seq = RREG32(drv->scratch_reg);
94
		seq = RREG32(drv->scratch_reg);
89
	}
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	}
90
	return seq;
96
	return seq;
Line 765... Line 771...
765
	int r;
771
	int r;
Line 766... Line 772...
766
 
772
 
767
	radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
773
	radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
768
	if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
774
	if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
-
 
775
		rdev->fence_drv[ring].scratch_reg = 0;
769
		rdev->fence_drv[ring].scratch_reg = 0;
776
		if (ring != R600_RING_TYPE_UVD_INDEX) {
-
 
777
		index = R600_WB_EVENT_OFFSET + ring * 4;
-
 
778
			rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
-
 
779
			rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
-
 
780
							 index;
-
 
781
 
-
 
782
		} else {
-
 
783
			/* put fence directly behind firmware */
-
 
784
			index = ALIGN(rdev->uvd_fw->size, 8);
-
 
785
			rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
-
 
786
			rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
-
 
787
		}
770
		index = R600_WB_EVENT_OFFSET + ring * 4;
788
 
771
	} else {
789
	} else {
772
		r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
790
		r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
773
	if (r) {
791
	if (r) {
774
		dev_err(rdev->dev, "fence failed to get scratch register\n");
792
		dev_err(rdev->dev, "fence failed to get scratch register\n");
775
		return r;
793
		return r;
776
	}
794
	}
777
		index = RADEON_WB_SCRATCH_OFFSET +
795
		index = RADEON_WB_SCRATCH_OFFSET +
778
			rdev->fence_drv[ring].scratch_reg -
796
			rdev->fence_drv[ring].scratch_reg -
779
			rdev->scratch.reg_base;
-
 
780
	}
797
			rdev->scratch.reg_base;
781
	rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
798
	rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
-
 
799
	rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
782
	rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
800
	}
783
	radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
801
	radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
784
	rdev->fence_drv[ring].initialized = true;
802
	rdev->fence_drv[ring].initialized = true;
785
	dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
803
	dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
786
		 ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
804
		 ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);