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Rev 1221 | Rev 1268 | ||
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Line 29... | Line 29... | ||
29 | #include "radeon.h" |
29 | #include "radeon.h" |
30 | #include "atom.h" |
30 | #include "atom.h" |
Line 31... | Line 31... | ||
31 | 31 | ||
Line -... | Line 32... | ||
- | 32 | extern int atom_debug; |
|
- | 33 | ||
- | 34 | /* evil but including atombios.h is much worse */ |
|
- | 35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
|
32 | extern int atom_debug; |
36 | struct drm_display_mode *mode); |
33 | 37 | ||
34 | uint32_t |
38 | uint32_t |
35 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
39 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
36 | { |
40 | { |
Line 165... | Line 169... | ||
165 | struct drm_display_mode *adjusted_mode) |
169 | struct drm_display_mode *adjusted_mode) |
166 | { |
170 | { |
167 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
171 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
168 | struct drm_device *dev = encoder->dev; |
172 | struct drm_device *dev = encoder->dev; |
169 | struct radeon_device *rdev = dev->dev_private; |
173 | struct radeon_device *rdev = dev->dev_private; |
170 | struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; |
174 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
Line 171... | Line 175... | ||
171 | 175 | ||
172 | if (mode->hdisplay < native_mode->panel_xres || |
176 | if (mode->hdisplay < native_mode->hdisplay || |
173 | mode->vdisplay < native_mode->panel_yres) { |
- | |
174 | if (ASIC_IS_AVIVO(rdev)) { |
177 | mode->vdisplay < native_mode->vdisplay) { |
175 | adjusted_mode->hdisplay = native_mode->panel_xres; |
178 | int mode_id = adjusted_mode->base.id; |
176 | adjusted_mode->vdisplay = native_mode->panel_yres; |
- | |
177 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; |
- | |
178 | adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; |
- | |
179 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width; |
- | |
180 | adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank; |
- | |
181 | adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus; |
- | |
182 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width; |
- | |
183 | /* update crtc values */ |
- | |
184 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
179 | *adjusted_mode = *native_mode; |
185 | /* adjust crtc values */ |
180 | if (!ASIC_IS_AVIVO(rdev)) { |
186 | adjusted_mode->crtc_hdisplay = native_mode->panel_xres; |
181 | adjusted_mode->hdisplay = mode->hdisplay; |
187 | adjusted_mode->crtc_vdisplay = native_mode->panel_yres; |
- | |
188 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank; |
- | |
189 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus; |
- | |
190 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width; |
- | |
191 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank; |
- | |
192 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus; |
- | |
193 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width; |
- | |
194 | } else { |
- | |
195 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; |
- | |
196 | adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; |
- | |
197 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width; |
- | |
198 | adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank; |
- | |
199 | adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus; |
- | |
200 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width; |
- | |
201 | /* update crtc values */ |
- | |
202 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
- | |
203 | /* adjust crtc values */ |
- | |
204 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank; |
- | |
205 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus; |
- | |
206 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width; |
- | |
207 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank; |
- | |
208 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus; |
- | |
209 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width; |
182 | adjusted_mode->vdisplay = mode->vdisplay; |
210 | } |
183 | } |
211 | adjusted_mode->flags = native_mode->flags; |
- | |
212 | adjusted_mode->clock = native_mode->dotclock; |
184 | adjusted_mode->base.id = mode_id; |
213 | } |
185 | } |
Line 214... | Line 186... | ||
214 | } |
186 | } |
215 | 187 | ||
216 | 188 | ||
217 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
189 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
218 | struct drm_display_mode *mode, |
190 | struct drm_display_mode *mode, |
- | 191 | struct drm_display_mode *adjusted_mode) |
|
- | 192 | { |
|
Line -... | Line 193... | ||
- | 193 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
- | 194 | struct drm_device *dev = encoder->dev; |
|
219 | struct drm_display_mode *adjusted_mode) |
195 | struct radeon_device *rdev = dev->dev_private; |
Line 220... | Line 196... | ||
220 | { |
196 | |
221 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
197 | /* set the active encoder to connector routing */ |
Line 222... | Line 198... | ||
222 | 198 | radeon_encoder_set_active_device(encoder); |
|
223 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
199 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
224 | 200 | ||
225 | if (radeon_encoder->rmx_type != RMX_OFF) |
201 | if (radeon_encoder->rmx_type != RMX_OFF) |
Line -... | Line 202... | ||
- | 202 | radeon_rmx_mode_fixup(encoder, mode, adjusted_mode); |
|
- | 203 | ||
- | 204 | /* hw bug */ |
|
- | 205 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
|
- | 206 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
|
- | 207 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
|
- | 208 | ||
- | 209 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
|
- | 210 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
|
- | 211 | if (tv_dac) { |
|
- | 212 | if (tv_dac->tv_std == TV_STD_NTSC || |
|
- | 213 | tv_dac->tv_std == TV_STD_NTSC_J || |
|
226 | radeon_rmx_mode_fixup(encoder, mode, adjusted_mode); |
214 | tv_dac->tv_std == TV_STD_PAL_M) |
227 | 215 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
|
Line 228... | Line 216... | ||
228 | /* hw bug */ |
216 | else |
229 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
217 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
Line 459... | Line 447... | ||
459 | case 2: |
447 | case 2: |
460 | switch (crev) { |
448 | switch (crev) { |
461 | case 1: |
449 | case 1: |
462 | args.v1.ucMisc = 0; |
450 | args.v1.ucMisc = 0; |
463 | args.v1.ucAction = action; |
451 | args.v1.ucAction = action; |
464 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
452 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
465 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
453 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
466 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
454 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
467 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
455 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
468 | if (dig->lvds_misc & (1 << 0)) |
456 | if (dig->lvds_misc & (1 << 0)) |
469 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
457 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
Line 484... | Line 472... | ||
484 | args.v2.ucAction = action; |
472 | args.v2.ucAction = action; |
485 | if (crev == 3) { |
473 | if (crev == 3) { |
486 | if (dig->coherent_mode) |
474 | if (dig->coherent_mode) |
487 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
475 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
488 | } |
476 | } |
489 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
477 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
490 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
478 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
491 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
479 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
492 | args.v2.ucTruncate = 0; |
480 | args.v2.ucTruncate = 0; |
493 | args.v2.ucSpatial = 0; |
481 | args.v2.ucSpatial = 0; |
494 | args.v2.ucTemporal = 0; |
482 | args.v2.ucTemporal = 0; |
Line 542... | Line 530... | ||
542 | radeon_connector = to_radeon_connector(connector); |
530 | radeon_connector = to_radeon_connector(connector); |
Line 543... | Line 531... | ||
543 | 531 | ||
544 | switch (connector->connector_type) { |
532 | switch (connector->connector_type) { |
545 | case DRM_MODE_CONNECTOR_DVII: |
533 | case DRM_MODE_CONNECTOR_DVII: |
546 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
534 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
547 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
535 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
548 | return ATOM_ENCODER_MODE_HDMI; |
536 | return ATOM_ENCODER_MODE_HDMI; |
549 | else if (radeon_connector->use_digital) |
537 | else if (radeon_connector->use_digital) |
550 | return ATOM_ENCODER_MODE_DVI; |
538 | return ATOM_ENCODER_MODE_DVI; |
551 | else |
539 | else |
552 | return ATOM_ENCODER_MODE_CRT; |
540 | return ATOM_ENCODER_MODE_CRT; |
553 | break; |
541 | break; |
554 | case DRM_MODE_CONNECTOR_DVID: |
542 | case DRM_MODE_CONNECTOR_DVID: |
555 | case DRM_MODE_CONNECTOR_HDMIA: |
543 | case DRM_MODE_CONNECTOR_HDMIA: |
556 | default: |
544 | default: |
557 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
545 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
558 | return ATOM_ENCODER_MODE_HDMI; |
546 | return ATOM_ENCODER_MODE_HDMI; |
559 | else |
547 | else |
560 | return ATOM_ENCODER_MODE_DVI; |
548 | return ATOM_ENCODER_MODE_DVI; |
561 | break; |
549 | break; |
Line 564... | Line 552... | ||
564 | break; |
552 | break; |
565 | case DRM_MODE_CONNECTOR_DisplayPort: |
553 | case DRM_MODE_CONNECTOR_DisplayPort: |
566 | /*if (radeon_output->MonType == MT_DP) |
554 | /*if (radeon_output->MonType == MT_DP) |
567 | return ATOM_ENCODER_MODE_DP; |
555 | return ATOM_ENCODER_MODE_DP; |
568 | else*/ |
556 | else*/ |
569 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
557 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
570 | return ATOM_ENCODER_MODE_HDMI; |
558 | return ATOM_ENCODER_MODE_HDMI; |
571 | else |
559 | else |
572 | return ATOM_ENCODER_MODE_DVI; |
560 | return ATOM_ENCODER_MODE_DVI; |
573 | break; |
561 | break; |
574 | case CONNECTOR_DVI_A: |
562 | case CONNECTOR_DVI_A: |
Line 732... | Line 720... | ||
732 | } |
720 | } |
Line 733... | Line 721... | ||
733 | 721 | ||
Line 734... | Line 722... | ||
734 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
722 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
735 | - | ||
736 | args.v1.ucAction = action; |
- | |
737 | 723 | ||
738 | if (ASIC_IS_DCE32(rdev)) { |
- | |
739 | if (radeon_encoder->pixel_clock > 165000) { |
724 | args.v1.ucAction = action; |
740 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100); |
725 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
- | 726 | args.v1.usInitInfo = radeon_connector->connector_object_id; |
|
741 | args.v2.acConfig.fDualLinkConnector = 1; |
727 | } else { |
- | 728 | if (radeon_encoder->pixel_clock > 165000) |
|
- | 729 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
|
742 | } else { |
730 | else |
- | 731 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
|
- | 732 | } |
|
- | 733 | if (ASIC_IS_DCE32(rdev)) { |
|
743 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100); |
734 | if (radeon_encoder->pixel_clock > 165000) |
744 | } |
735 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
Line 745... | Line 736... | ||
745 | if (dig->dig_block) |
736 | if (dig->dig_block) |
746 | args.v2.acConfig.ucEncoderSel = 1; |
737 | args.v2.acConfig.ucEncoderSel = 1; |
Line 764... | Line 755... | ||
764 | if (dig->coherent_mode) |
755 | if (dig->coherent_mode) |
765 | args.v2.acConfig.fCoherentMode = 1; |
756 | args.v2.acConfig.fCoherentMode = 1; |
766 | } |
757 | } |
767 | } else { |
758 | } else { |
768 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
759 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
769 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10); |
- | |
Line 770... | Line 760... | ||
770 | 760 | ||
771 | switch (radeon_encoder->encoder_id) { |
761 | switch (radeon_encoder->encoder_id) { |
772 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
762 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
773 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
763 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
Line 872... | Line 862... | ||
872 | struct radeon_device *rdev = dev->dev_private; |
862 | struct radeon_device *rdev = dev->dev_private; |
873 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
863 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
874 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
864 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
875 | int index = 0; |
865 | int index = 0; |
876 | bool is_dig = false; |
866 | bool is_dig = false; |
877 | int devices; |
- | |
Line 878... | Line 867... | ||
878 | 867 | ||
Line 879... | Line -... | ||
879 | memset(&args, 0, sizeof(args)); |
- | |
880 | - | ||
881 | /* on DPMS off we have no idea if active device is meaningful */ |
- | |
882 | if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device) |
- | |
883 | devices = radeon_encoder->devices; |
- | |
884 | else |
- | |
885 | devices = radeon_encoder->active_device; |
868 | memset(&args, 0, sizeof(args)); |
886 | 869 | ||
887 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
870 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
888 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
871 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
889 | radeon_encoder->active_device); |
872 | radeon_encoder->active_device); |
Line 912... | Line 895... | ||
912 | else |
895 | else |
913 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
896 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
914 | break; |
897 | break; |
915 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
898 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
916 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
899 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
917 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) |
900 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
918 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
901 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
919 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) |
902 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
920 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
903 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
921 | else |
904 | else |
922 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
905 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
923 | break; |
906 | break; |
924 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
907 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
925 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
908 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
926 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) |
909 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
927 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
910 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
928 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) |
911 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
929 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
912 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
930 | else |
913 | else |
931 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
914 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
932 | break; |
915 | break; |
933 | } |
916 | } |
Line 1102... | Line 1085... | ||
1102 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1085 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
1103 | } |
1086 | } |
1104 | } |
1087 | } |
Line 1105... | Line 1088... | ||
1105 | 1088 | ||
- | 1089 | /* set scaler clears this on some chips */ |
|
1106 | /* set scaler clears this on some chips */ |
1090 | if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { |
1107 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) |
1091 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) |
- | 1092 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
|
- | 1093 | AVIVO_D1MODE_INTERLEAVE_EN); |
|
1108 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN); |
1094 | } |
Line 1109... | Line 1095... | ||
1109 | } |
1095 | } |
1110 | 1096 | ||
1111 | static void |
1097 | static void |
Line 1151... | Line 1137... | ||
1151 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE); |
1137 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE); |
1152 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); |
1138 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); |
Line 1153... | Line 1139... | ||
1153 | 1139 | ||
1154 | /* setup and enable the encoder and transmitter */ |
1140 | /* setup and enable the encoder and transmitter */ |
- | 1141 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); |
|
1155 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); |
1142 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT); |
1156 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP); |
1143 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP); |
1157 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
1144 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
1158 | break; |
1145 | break; |
1159 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1146 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
Line 1266... | Line 1253... | ||
1266 | 1253 | ||
1267 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
1254 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
1268 | { |
1255 | { |
1269 | radeon_atom_output_lock(encoder, true); |
1256 | radeon_atom_output_lock(encoder, true); |
1270 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
- | |
1271 | - | ||
1272 | radeon_encoder_set_active_device(encoder); |
1257 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
Line 1273... | Line 1258... | ||
1273 | } |
1258 | } |
1274 | 1259 | ||
1275 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
1260 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |