Rev 1126 | Rev 1182 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1126 | Rev 1179 | ||
|---|---|---|---|
| Line 124... | Line 124... | ||
| 124 | drm_mode_connector_attach_encoder(connector, encoder); |
124 | drm_mode_connector_attach_encoder(connector, encoder); |
| 125 | } |
125 | } |
| 126 | } |
126 | } |
| 127 | } |
127 | } |
| Line -... | Line 128... | ||
| - | 128 | ||
| - | 129 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
|
| - | 130 | { |
|
| - | 131 | struct drm_device *dev = encoder->dev; |
|
| - | 132 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
| - | 133 | struct drm_connector *connector; |
|
| - | 134 | ||
| - | 135 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
| - | 136 | if (connector->encoder == encoder) { |
|
| - | 137 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| - | 138 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
|
| - | 139 | DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", |
|
| - | 140 | radeon_encoder->active_device, radeon_encoder->devices, |
|
| - | 141 | radeon_connector->devices, encoder->encoder_type); |
|
| - | 142 | } |
|
| - | 143 | } |
|
| - | 144 | } |
|
| 128 | 145 | ||
| 129 | static struct drm_connector * |
146 | static struct drm_connector * |
| 130 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
147 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
| 131 | { |
148 | { |
| 132 | struct drm_device *dev = encoder->dev; |
149 | struct drm_device *dev = encoder->dev; |
| Line 152... | Line 169... | ||
| 152 | struct radeon_device *rdev = dev->dev_private; |
169 | struct radeon_device *rdev = dev->dev_private; |
| 153 | struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; |
170 | struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; |
| Line 154... | Line 171... | ||
| 154 | 171 | ||
| 155 | if (mode->hdisplay < native_mode->panel_xres || |
172 | if (mode->hdisplay < native_mode->panel_xres || |
| 156 | mode->vdisplay < native_mode->panel_yres) { |
- | |
| 157 | radeon_encoder->flags |= RADEON_USE_RMX; |
173 | mode->vdisplay < native_mode->panel_yres) { |
| 158 | if (ASIC_IS_AVIVO(rdev)) { |
174 | if (ASIC_IS_AVIVO(rdev)) { |
| 159 | adjusted_mode->hdisplay = native_mode->panel_xres; |
175 | adjusted_mode->hdisplay = native_mode->panel_xres; |
| 160 | adjusted_mode->vdisplay = native_mode->panel_yres; |
176 | adjusted_mode->vdisplay = native_mode->panel_yres; |
| 161 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; |
177 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; |
| Line 199... | Line 215... | ||
| 199 | 215 | ||
| 200 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
216 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
| 201 | struct drm_display_mode *mode, |
217 | struct drm_display_mode *mode, |
| 202 | struct drm_display_mode *adjusted_mode) |
218 | struct drm_display_mode *adjusted_mode) |
| 203 | { |
- | |
| 204 | 219 | { |
|
| Line 205... | Line -... | ||
| 205 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | |
| 206 | - | ||
| 207 | radeon_encoder->flags &= ~RADEON_USE_RMX; |
220 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| Line 208... | Line 221... | ||
| 208 | 221 | ||
| 209 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
222 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| Line 225... | Line 238... | ||
| 225 | struct drm_device *dev = encoder->dev; |
238 | struct drm_device *dev = encoder->dev; |
| 226 | struct radeon_device *rdev = dev->dev_private; |
239 | struct radeon_device *rdev = dev->dev_private; |
| 227 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
240 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 228 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
241 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
| 229 | int index = 0, num = 0; |
242 | int index = 0, num = 0; |
| 230 | /* fixme - fill in enc_priv for atom dac */ |
243 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
| 231 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
244 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
| Line -... | Line 245... | ||
| - | 245 | ||
| - | 246 | if (dac_info->tv_std) |
|
| - | 247 | tv_std = dac_info->tv_std; |
|
| 232 | 248 | ||
| Line 233... | Line 249... | ||
| 233 | memset(&args, 0, sizeof(args)); |
249 | memset(&args, 0, sizeof(args)); |
| 234 | 250 | ||
| 235 | switch (radeon_encoder->encoder_id) { |
251 | switch (radeon_encoder->encoder_id) { |
| Line 245... | Line 261... | ||
| 245 | break; |
261 | break; |
| 246 | } |
262 | } |
| Line 247... | Line 263... | ||
| 247 | 263 | ||
| Line 248... | Line 264... | ||
| 248 | args.ucAction = action; |
264 | args.ucAction = action; |
| 249 | 265 | ||
| 250 | if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
266 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
| 251 | args.ucDacStandard = ATOM_DAC1_PS2; |
267 | args.ucDacStandard = ATOM_DAC1_PS2; |
| 252 | else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
268 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 253 | args.ucDacStandard = ATOM_DAC1_CV; |
269 | args.ucDacStandard = ATOM_DAC1_CV; |
| 254 | else { |
270 | else { |
| 255 | switch (tv_std) { |
271 | switch (tv_std) { |
| Line 280... | Line 296... | ||
| 280 | struct drm_device *dev = encoder->dev; |
296 | struct drm_device *dev = encoder->dev; |
| 281 | struct radeon_device *rdev = dev->dev_private; |
297 | struct radeon_device *rdev = dev->dev_private; |
| 282 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
298 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 283 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
299 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
| 284 | int index = 0; |
300 | int index = 0; |
| 285 | /* fixme - fill in enc_priv for atom dac */ |
301 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
| 286 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
302 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
| Line -... | Line 303... | ||
| - | 303 | ||
| - | 304 | if (dac_info->tv_std) |
|
| - | 305 | tv_std = dac_info->tv_std; |
|
| 287 | 306 | ||
| Line 288... | Line 307... | ||
| 288 | memset(&args, 0, sizeof(args)); |
307 | memset(&args, 0, sizeof(args)); |
| Line 289... | Line 308... | ||
| 289 | 308 | ||
| Line 290... | Line 309... | ||
| 290 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
309 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
| 291 | 310 | ||
| 292 | args.sTVEncoder.ucAction = action; |
311 | args.sTVEncoder.ucAction = action; |
| 293 | 312 | ||
| 294 | if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
313 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 295 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
314 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
| Line 521... | Line 540... | ||
| 521 | 540 | ||
| Line 522... | Line 541... | ||
| 522 | radeon_connector = to_radeon_connector(connector); |
541 | radeon_connector = to_radeon_connector(connector); |
| 523 | 542 | ||
| - | 543 | switch (connector->connector_type) { |
|
| 524 | switch (connector->connector_type) { |
544 | case DRM_MODE_CONNECTOR_DVII: |
| 525 | case DRM_MODE_CONNECTOR_DVII: |
545 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
| 526 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
546 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
| 527 | return ATOM_ENCODER_MODE_HDMI; |
547 | return ATOM_ENCODER_MODE_HDMI; |
| 528 | else if (radeon_connector->use_digital) |
548 | else if (radeon_connector->use_digital) |
| 529 | return ATOM_ENCODER_MODE_DVI; |
549 | return ATOM_ENCODER_MODE_DVI; |
| 530 | else |
550 | else |
| 531 | return ATOM_ENCODER_MODE_CRT; |
551 | return ATOM_ENCODER_MODE_CRT; |
| 532 | break; |
552 | break; |
| 533 | case DRM_MODE_CONNECTOR_DVID: |
- | |
| 534 | case DRM_MODE_CONNECTOR_HDMIA: |
553 | case DRM_MODE_CONNECTOR_DVID: |
| 535 | case DRM_MODE_CONNECTOR_HDMIB: |
554 | case DRM_MODE_CONNECTOR_HDMIA: |
| 536 | default: |
555 | default: |
| 537 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
556 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) |
| 538 | return ATOM_ENCODER_MODE_HDMI; |
557 | return ATOM_ENCODER_MODE_HDMI; |
| Line 806... | Line 825... | ||
| 806 | 825 | ||
| Line 807... | Line 826... | ||
| 807 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
826 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| Line 808... | Line -... | ||
| 808 | - | ||
| 809 | } |
- | |
| 810 | - | ||
| 811 | static void atom_rv515_force_tv_scaler(struct radeon_device *rdev) |
- | |
| 812 | { |
- | |
| 813 | - | ||
| 814 | WREG32(0x659C, 0x0); |
- | |
| 815 | WREG32(0x6594, 0x705); |
- | |
| 816 | WREG32(0x65A4, 0x10001); |
- | |
| 817 | WREG32(0x65D8, 0x0); |
- | |
| 818 | WREG32(0x65B0, 0x0); |
- | |
| 819 | WREG32(0x65C0, 0x0); |
- | |
| 820 | WREG32(0x65D4, 0x0); |
- | |
| 821 | WREG32(0x6578, 0x0); |
- | |
| 822 | WREG32(0x657C, 0x841880A8); |
- | |
| 823 | WREG32(0x6578, 0x1); |
- | |
| 824 | WREG32(0x657C, 0x84208680); |
- | |
| 825 | WREG32(0x6578, 0x2); |
- | |
| 826 | WREG32(0x657C, 0xBFF880B0); |
- | |
| 827 | WREG32(0x6578, 0x100); |
- | |
| 828 | WREG32(0x657C, 0x83D88088); |
- | |
| 829 | WREG32(0x6578, 0x101); |
- | |
| 830 | WREG32(0x657C, 0x84608680); |
- | |
| 831 | WREG32(0x6578, 0x102); |
- | |
| 832 | WREG32(0x657C, 0xBFF080D0); |
- | |
| 833 | WREG32(0x6578, 0x200); |
- | |
| 834 | WREG32(0x657C, 0x83988068); |
- | |
| 835 | WREG32(0x6578, 0x201); |
- | |
| 836 | WREG32(0x657C, 0x84A08680); |
- | |
| 837 | WREG32(0x6578, 0x202); |
- | |
| 838 | WREG32(0x657C, 0xBFF080F8); |
- | |
| 839 | WREG32(0x6578, 0x300); |
- | |
| 840 | WREG32(0x657C, 0x83588058); |
- | |
| 841 | WREG32(0x6578, 0x301); |
- | |
| 842 | WREG32(0x657C, 0x84E08660); |
- | |
| 843 | WREG32(0x6578, 0x302); |
- | |
| 844 | WREG32(0x657C, 0xBFF88120); |
- | |
| 845 | WREG32(0x6578, 0x400); |
- | |
| 846 | WREG32(0x657C, 0x83188040); |
- | |
| 847 | WREG32(0x6578, 0x401); |
- | |
| 848 | WREG32(0x657C, 0x85008660); |
- | |
| 849 | WREG32(0x6578, 0x402); |
- | |
| 850 | WREG32(0x657C, 0xBFF88150); |
- | |
| 851 | WREG32(0x6578, 0x500); |
- | |
| 852 | WREG32(0x657C, 0x82D88030); |
- | |
| 853 | WREG32(0x6578, 0x501); |
- | |
| 854 | WREG32(0x657C, 0x85408640); |
- | |
| 855 | WREG32(0x6578, 0x502); |
- | |
| 856 | WREG32(0x657C, 0xBFF88180); |
- | |
| 857 | WREG32(0x6578, 0x600); |
- | |
| 858 | WREG32(0x657C, 0x82A08018); |
- | |
| 859 | WREG32(0x6578, 0x601); |
- | |
| 860 | WREG32(0x657C, 0x85808620); |
- | |
| 861 | WREG32(0x6578, 0x602); |
- | |
| 862 | WREG32(0x657C, 0xBFF081B8); |
- | |
| 863 | WREG32(0x6578, 0x700); |
- | |
| 864 | WREG32(0x657C, 0x82608010); |
- | |
| 865 | WREG32(0x6578, 0x701); |
- | |
| 866 | WREG32(0x657C, 0x85A08600); |
- | |
| 867 | WREG32(0x6578, 0x702); |
- | |
| 868 | WREG32(0x657C, 0x800081F0); |
- | |
| 869 | WREG32(0x6578, 0x800); |
- | |
| 870 | WREG32(0x657C, 0x8228BFF8); |
- | |
| 871 | WREG32(0x6578, 0x801); |
- | |
| 872 | WREG32(0x657C, 0x85E085E0); |
- | |
| 873 | WREG32(0x6578, 0x802); |
- | |
| 874 | WREG32(0x657C, 0xBFF88228); |
- | |
| 875 | WREG32(0x6578, 0x10000); |
- | |
| 876 | WREG32(0x657C, 0x82A8BF00); |
- | |
| 877 | WREG32(0x6578, 0x10001); |
- | |
| 878 | WREG32(0x657C, 0x82A08CC0); |
- | |
| 879 | WREG32(0x6578, 0x10002); |
- | |
| 880 | WREG32(0x657C, 0x8008BEF8); |
- | |
| 881 | WREG32(0x6578, 0x10100); |
- | |
| 882 | WREG32(0x657C, 0x81F0BF28); |
- | |
| 883 | WREG32(0x6578, 0x10101); |
- | |
| 884 | WREG32(0x657C, 0x83608CA0); |
- | |
| 885 | WREG32(0x6578, 0x10102); |
- | |
| 886 | WREG32(0x657C, 0x8018BED0); |
- | |
| 887 | WREG32(0x6578, 0x10200); |
- | |
| 888 | WREG32(0x657C, 0x8148BF38); |
- | |
| 889 | WREG32(0x6578, 0x10201); |
- | |
| 890 | WREG32(0x657C, 0x84408C80); |
- | |
| 891 | WREG32(0x6578, 0x10202); |
- | |
| 892 | WREG32(0x657C, 0x8008BEB8); |
- | |
| 893 | WREG32(0x6578, 0x10300); |
- | |
| 894 | WREG32(0x657C, 0x80B0BF78); |
- | |
| 895 | WREG32(0x6578, 0x10301); |
- | |
| 896 | WREG32(0x657C, 0x85008C20); |
- | |
| 897 | WREG32(0x6578, 0x10302); |
- | |
| 898 | WREG32(0x657C, 0x8020BEA0); |
- | |
| 899 | WREG32(0x6578, 0x10400); |
- | |
| 900 | WREG32(0x657C, 0x8028BF90); |
- | |
| 901 | WREG32(0x6578, 0x10401); |
- | |
| 902 | WREG32(0x657C, 0x85E08BC0); |
- | |
| 903 | WREG32(0x6578, 0x10402); |
- | |
| 904 | WREG32(0x657C, 0x8018BE90); |
- | |
| 905 | WREG32(0x6578, 0x10500); |
- | |
| 906 | WREG32(0x657C, 0xBFB8BFB0); |
- | |
| 907 | WREG32(0x6578, 0x10501); |
- | |
| 908 | WREG32(0x657C, 0x86C08B40); |
- | |
| 909 | WREG32(0x6578, 0x10502); |
- | |
| 910 | WREG32(0x657C, 0x8010BE90); |
- | |
| 911 | WREG32(0x6578, 0x10600); |
- | |
| 912 | WREG32(0x657C, 0xBF58BFC8); |
- | |
| 913 | WREG32(0x6578, 0x10601); |
- | |
| 914 | WREG32(0x657C, 0x87A08AA0); |
- | |
| 915 | WREG32(0x6578, 0x10602); |
- | |
| 916 | WREG32(0x657C, 0x8010BE98); |
- | |
| 917 | WREG32(0x6578, 0x10700); |
- | |
| 918 | WREG32(0x657C, 0xBF10BFF0); |
- | |
| 919 | WREG32(0x6578, 0x10701); |
- | |
| 920 | WREG32(0x657C, 0x886089E0); |
- | |
| 921 | WREG32(0x6578, 0x10702); |
- | |
| 922 | WREG32(0x657C, 0x8018BEB0); |
- | |
| 923 | WREG32(0x6578, 0x10800); |
- | |
| 924 | WREG32(0x657C, 0xBED8BFE8); |
- | |
| 925 | WREG32(0x6578, 0x10801); |
- | |
| 926 | WREG32(0x657C, 0x89408940); |
- | |
| 927 | WREG32(0x6578, 0x10802); |
- | |
| 928 | WREG32(0x657C, 0xBFE8BED8); |
- | |
| 929 | WREG32(0x6578, 0x20000); |
- | |
| 930 | WREG32(0x657C, 0x80008000); |
- | |
| 931 | WREG32(0x6578, 0x20001); |
- | |
| 932 | WREG32(0x657C, 0x90008000); |
- | |
| 933 | WREG32(0x6578, 0x20002); |
- | |
| 934 | WREG32(0x657C, 0x80008000); |
- | |
| 935 | WREG32(0x6578, 0x20003); |
- | |
| 936 | WREG32(0x657C, 0x80008000); |
- | |
| 937 | WREG32(0x6578, 0x20100); |
- | |
| 938 | WREG32(0x657C, 0x80108000); |
- | |
| 939 | WREG32(0x6578, 0x20101); |
- | |
| 940 | WREG32(0x657C, 0x8FE0BF70); |
- | |
| 941 | WREG32(0x6578, 0x20102); |
- | |
| 942 | WREG32(0x657C, 0xBFE880C0); |
- | |
| 943 | WREG32(0x6578, 0x20103); |
- | |
| 944 | WREG32(0x657C, 0x80008000); |
- | |
| 945 | WREG32(0x6578, 0x20200); |
- | |
| 946 | WREG32(0x657C, 0x8018BFF8); |
- | |
| 947 | WREG32(0x6578, 0x20201); |
- | |
| 948 | WREG32(0x657C, 0x8F80BF08); |
- | |
| 949 | WREG32(0x6578, 0x20202); |
- | |
| 950 | WREG32(0x657C, 0xBFD081A0); |
- | |
| 951 | WREG32(0x6578, 0x20203); |
- | |
| 952 | WREG32(0x657C, 0xBFF88000); |
- | |
| 953 | WREG32(0x6578, 0x20300); |
- | |
| 954 | WREG32(0x657C, 0x80188000); |
- | |
| 955 | WREG32(0x6578, 0x20301); |
- | |
| 956 | WREG32(0x657C, 0x8EE0BEC0); |
- | |
| 957 | WREG32(0x6578, 0x20302); |
- | |
| 958 | WREG32(0x657C, 0xBFB082A0); |
- | |
| 959 | WREG32(0x6578, 0x20303); |
- | |
| 960 | WREG32(0x657C, 0x80008000); |
- | |
| 961 | WREG32(0x6578, 0x20400); |
- | |
| 962 | WREG32(0x657C, 0x80188000); |
- | |
| 963 | WREG32(0x6578, 0x20401); |
- | |
| 964 | WREG32(0x657C, 0x8E00BEA0); |
- | |
| 965 | WREG32(0x6578, 0x20402); |
- | |
| 966 | WREG32(0x657C, 0xBF8883C0); |
- | |
| 967 | WREG32(0x6578, 0x20403); |
- | |
| 968 | WREG32(0x657C, 0x80008000); |
- | |
| 969 | WREG32(0x6578, 0x20500); |
- | |
| 970 | WREG32(0x657C, 0x80188000); |
- | |
| 971 | WREG32(0x6578, 0x20501); |
- | |
| 972 | WREG32(0x657C, 0x8D00BE90); |
- | |
| 973 | WREG32(0x6578, 0x20502); |
- | |
| 974 | WREG32(0x657C, 0xBF588500); |
- | |
| 975 | WREG32(0x6578, 0x20503); |
- | |
| 976 | WREG32(0x657C, 0x80008008); |
- | |
| 977 | WREG32(0x6578, 0x20600); |
- | |
| 978 | WREG32(0x657C, 0x80188000); |
- | |
| 979 | WREG32(0x6578, 0x20601); |
- | |
| 980 | WREG32(0x657C, 0x8BC0BE98); |
- | |
| 981 | WREG32(0x6578, 0x20602); |
- | |
| 982 | WREG32(0x657C, 0xBF308660); |
- | |
| 983 | WREG32(0x6578, 0x20603); |
- | |
| 984 | WREG32(0x657C, 0x80008008); |
- | |
| 985 | WREG32(0x6578, 0x20700); |
- | |
| 986 | WREG32(0x657C, 0x80108000); |
- | |
| 987 | WREG32(0x6578, 0x20701); |
- | |
| 988 | WREG32(0x657C, 0x8A80BEB0); |
- | |
| 989 | WREG32(0x6578, 0x20702); |
- | |
| 990 | WREG32(0x657C, 0xBF0087C0); |
- | |
| 991 | WREG32(0x6578, 0x20703); |
- | |
| 992 | WREG32(0x657C, 0x80008008); |
- | |
| 993 | WREG32(0x6578, 0x20800); |
- | |
| 994 | WREG32(0x657C, 0x80108000); |
- | |
| 995 | WREG32(0x6578, 0x20801); |
- | |
| 996 | WREG32(0x657C, 0x8920BED0); |
- | |
| 997 | WREG32(0x6578, 0x20802); |
- | |
| 998 | WREG32(0x657C, 0xBED08920); |
- | |
| 999 | WREG32(0x6578, 0x20803); |
- | |
| 1000 | WREG32(0x657C, 0x80008010); |
- | |
| 1001 | WREG32(0x6578, 0x30000); |
- | |
| 1002 | WREG32(0x657C, 0x90008000); |
- | |
| 1003 | WREG32(0x6578, 0x30001); |
- | |
| 1004 | WREG32(0x657C, 0x80008000); |
- | |
| 1005 | WREG32(0x6578, 0x30100); |
- | |
| 1006 | WREG32(0x657C, 0x8FE0BF90); |
- | |
| 1007 | WREG32(0x6578, 0x30101); |
- | |
| 1008 | WREG32(0x657C, 0xBFF880A0); |
- | |
| 1009 | WREG32(0x6578, 0x30200); |
- | |
| 1010 | WREG32(0x657C, 0x8F60BF40); |
- | |
| 1011 | WREG32(0x6578, 0x30201); |
- | |
| 1012 | WREG32(0x657C, 0xBFE88180); |
- | |
| 1013 | WREG32(0x6578, 0x30300); |
- | |
| 1014 | WREG32(0x657C, 0x8EC0BF00); |
- | |
| 1015 | WREG32(0x6578, 0x30301); |
- | |
| 1016 | WREG32(0x657C, 0xBFC88280); |
- | |
| 1017 | WREG32(0x6578, 0x30400); |
- | |
| 1018 | WREG32(0x657C, 0x8DE0BEE0); |
- | |
| 1019 | WREG32(0x6578, 0x30401); |
- | |
| 1020 | WREG32(0x657C, 0xBFA083A0); |
- | |
| 1021 | WREG32(0x6578, 0x30500); |
- | |
| 1022 | WREG32(0x657C, 0x8CE0BED0); |
- | |
| 1023 | WREG32(0x6578, 0x30501); |
- | |
| 1024 | WREG32(0x657C, 0xBF7884E0); |
- | |
| 1025 | WREG32(0x6578, 0x30600); |
- | |
| 1026 | WREG32(0x657C, 0x8BA0BED8); |
- | |
| 1027 | WREG32(0x6578, 0x30601); |
- | |
| 1028 | WREG32(0x657C, 0xBF508640); |
- | |
| 1029 | WREG32(0x6578, 0x30700); |
- | |
| 1030 | WREG32(0x657C, 0x8A60BEE8); |
- | |
| 1031 | WREG32(0x6578, 0x30701); |
- | |
| 1032 | WREG32(0x657C, 0xBF2087A0); |
- | |
| 1033 | WREG32(0x6578, 0x30800); |
- | |
| 1034 | WREG32(0x657C, 0x8900BF00); |
- | |
| 1035 | WREG32(0x6578, 0x30801); |
- | |
| 1036 | WREG32(0x657C, 0xBF008900); |
827 | |
| 1037 | } |
828 | } |
| 1038 | 829 | ||
| 1039 | static void |
830 | static void |
| 1040 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
831 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
| Line 1054... | Line 845... | ||
| 1054 | else |
845 | else |
| 1055 | reg = RADEON_BIOS_3_SCRATCH; |
846 | reg = RADEON_BIOS_3_SCRATCH; |
| Line 1056... | Line 847... | ||
| 1056 | 847 | ||
| 1057 | /* XXX: fix up scratch reg handling */ |
848 | /* XXX: fix up scratch reg handling */ |
| 1058 | temp = RREG32(reg); |
849 | temp = RREG32(reg); |
| 1059 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) |
850 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1060 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
851 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
| 1061 | (radeon_crtc->crtc_id << 18))); |
852 | (radeon_crtc->crtc_id << 18))); |
| 1062 | else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
853 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1063 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
854 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
| 1064 | else |
855 | else |
| Line 1065... | Line 856... | ||
| 1065 | WREG32(reg, 0); |
856 | WREG32(reg, 0); |
| Line 1072... | Line 863... | ||
| 1072 | 863 | ||
| 1073 | WREG32(reg, temp); |
864 | WREG32(reg, temp); |
| Line 1074... | Line 865... | ||
| 1074 | } |
865 | } |
| 1075 | - | ||
| 1076 | static void |
- | |
| 1077 | atombios_overscan_setup(struct drm_encoder *encoder, |
- | |
| 1078 | struct drm_display_mode *mode, |
- | |
| 1079 | struct drm_display_mode *adjusted_mode) |
- | |
| 1080 | { |
- | |
| 1081 | struct drm_device *dev = encoder->dev; |
- | |
| 1082 | struct radeon_device *rdev = dev->dev_private; |
- | |
| 1083 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | |
| 1084 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
- | |
| 1085 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
- | |
| 1086 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
- | |
| 1087 | - | ||
| 1088 | memset(&args, 0, sizeof(args)); |
- | |
| 1089 | - | ||
| 1090 | args.usOverscanRight = 0; |
- | |
| 1091 | args.usOverscanLeft = 0; |
- | |
| 1092 | args.usOverscanBottom = 0; |
- | |
| 1093 | args.usOverscanTop = 0; |
- | |
| 1094 | args.ucCRTC = radeon_crtc->crtc_id; |
- | |
| 1095 | - | ||
| 1096 | if (radeon_encoder->flags & RADEON_USE_RMX) { |
- | |
| 1097 | if (radeon_encoder->rmx_type == RMX_FULL) { |
- | |
| 1098 | args.usOverscanRight = 0; |
- | |
| 1099 | args.usOverscanLeft = 0; |
- | |
| 1100 | args.usOverscanBottom = 0; |
- | |
| 1101 | args.usOverscanTop = 0; |
- | |
| 1102 | } else if (radeon_encoder->rmx_type == RMX_CENTER) { |
- | |
| 1103 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
- | |
| 1104 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
- | |
| 1105 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
- | |
| 1106 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
- | |
| 1107 | } else if (radeon_encoder->rmx_type == RMX_ASPECT) { |
- | |
| 1108 | int a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
- | |
| 1109 | int a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
- | |
| 1110 | - | ||
| 1111 | if (a1 > a2) { |
- | |
| 1112 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
- | |
| 1113 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
- | |
| 1114 | } else if (a2 > a1) { |
- | |
| 1115 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
- | |
| 1116 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
- | |
| 1117 | } |
- | |
| 1118 | } |
- | |
| 1119 | } |
- | |
| 1120 | - | ||
| 1121 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
- | |
| 1122 | - | ||
| 1123 | } |
- | |
| 1124 | - | ||
| 1125 | static void |
- | |
| 1126 | atombios_scaler_setup(struct drm_encoder *encoder) |
- | |
| 1127 | { |
- | |
| 1128 | struct drm_device *dev = encoder->dev; |
- | |
| 1129 | struct radeon_device *rdev = dev->dev_private; |
- | |
| 1130 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
- | |
| 1131 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
- | |
| 1132 | ENABLE_SCALER_PS_ALLOCATION args; |
- | |
| 1133 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
- | |
| 1134 | /* fixme - fill in enc_priv for atom dac */ |
- | |
| 1135 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
- | |
| 1136 | - | ||
| 1137 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
- | |
| 1138 | return; |
- | |
| 1139 | - | ||
| 1140 | memset(&args, 0, sizeof(args)); |
- | |
| 1141 | - | ||
| 1142 | args.ucScaler = radeon_crtc->crtc_id; |
- | |
| 1143 | - | ||
| 1144 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { |
- | |
| 1145 | switch (tv_std) { |
- | |
| 1146 | case TV_STD_NTSC: |
- | |
| 1147 | default: |
- | |
| 1148 | args.ucTVStandard = ATOM_TV_NTSC; |
- | |
| 1149 | break; |
- | |
| 1150 | case TV_STD_PAL: |
- | |
| 1151 | args.ucTVStandard = ATOM_TV_PAL; |
- | |
| 1152 | break; |
- | |
| 1153 | case TV_STD_PAL_M: |
- | |
| 1154 | args.ucTVStandard = ATOM_TV_PALM; |
- | |
| 1155 | break; |
- | |
| 1156 | case TV_STD_PAL_60: |
- | |
| 1157 | args.ucTVStandard = ATOM_TV_PAL60; |
- | |
| 1158 | break; |
- | |
| 1159 | case TV_STD_NTSC_J: |
- | |
| 1160 | args.ucTVStandard = ATOM_TV_NTSCJ; |
- | |
| 1161 | break; |
- | |
| 1162 | case TV_STD_SCART_PAL: |
- | |
| 1163 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
- | |
| 1164 | break; |
- | |
| 1165 | case TV_STD_SECAM: |
- | |
| 1166 | args.ucTVStandard = ATOM_TV_SECAM; |
- | |
| 1167 | break; |
- | |
| 1168 | case TV_STD_PAL_CN: |
- | |
| 1169 | args.ucTVStandard = ATOM_TV_PALCN; |
- | |
| 1170 | break; |
- | |
| 1171 | } |
- | |
| 1172 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
- | |
| 1173 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) { |
- | |
| 1174 | args.ucTVStandard = ATOM_TV_CV; |
- | |
| 1175 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
- | |
| 1176 | } else if (radeon_encoder->flags & RADEON_USE_RMX) { |
- | |
| 1177 | if (radeon_encoder->rmx_type == RMX_FULL) |
- | |
| 1178 | args.ucEnable = ATOM_SCALER_EXPANSION; |
- | |
| 1179 | else if (radeon_encoder->rmx_type == RMX_CENTER) |
- | |
| 1180 | args.ucEnable = ATOM_SCALER_CENTER; |
- | |
| 1181 | else if (radeon_encoder->rmx_type == RMX_ASPECT) |
- | |
| 1182 | args.ucEnable = ATOM_SCALER_EXPANSION; |
- | |
| 1183 | } else { |
- | |
| 1184 | if (ASIC_IS_AVIVO(rdev)) |
- | |
| 1185 | args.ucEnable = ATOM_SCALER_DISABLE; |
- | |
| 1186 | else |
- | |
| 1187 | args.ucEnable = ATOM_SCALER_CENTER; |
- | |
| 1188 | } |
- | |
| 1189 | - | ||
| 1190 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
- | |
| 1191 | - | ||
| 1192 | if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) |
- | |
| 1193 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) { |
- | |
| 1194 | atom_rv515_force_tv_scaler(rdev); |
- | |
| 1195 | } |
- | |
| 1196 | - | ||
| 1197 | } |
- | |
| 1198 | 866 | ||
| 1199 | static void |
867 | static void |
| 1200 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
868 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
| 1201 | { |
869 | { |
| 1202 | struct drm_device *dev = encoder->dev; |
870 | struct drm_device *dev = encoder->dev; |
| 1203 | struct radeon_device *rdev = dev->dev_private; |
871 | struct radeon_device *rdev = dev->dev_private; |
| 1204 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
872 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1205 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
873 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
| - | 874 | int index = 0; |
|
| Line 1206... | Line 875... | ||
| 1206 | int index = 0; |
875 | bool is_dig = false; |
| Line -... | Line 876... | ||
| - | 876 | int devices; |
|
| - | 877 | ||
| - | 878 | memset(&args, 0, sizeof(args)); |
|
| - | 879 | ||
| - | 880 | /* on DPMS off we have no idea if active device is meaningful */ |
|
| - | 881 | if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device) |
|
| - | 882 | devices = radeon_encoder->devices; |
|
| - | 883 | else |
|
| - | 884 | devices = radeon_encoder->active_device; |
|
| 1207 | bool is_dig = false; |
885 | |
| 1208 | 886 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
|
| 1209 | memset(&args, 0, sizeof(args)); |
887 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
| 1210 | 888 | radeon_encoder->active_device); |
|
| 1211 | switch (radeon_encoder->encoder_id) { |
889 | switch (radeon_encoder->encoder_id) { |
| Line 1233... | Line 911... | ||
| 1233 | else |
911 | else |
| 1234 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
912 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
| 1235 | break; |
913 | break; |
| 1236 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
914 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1237 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
915 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1238 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) |
916 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) |
| 1239 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
917 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
| 1240 | else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
918 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) |
| 1241 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
919 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
| 1242 | else |
920 | else |
| 1243 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
921 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
| 1244 | break; |
922 | break; |
| 1245 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
923 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1246 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
924 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1247 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) |
925 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) |
| 1248 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
926 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
| 1249 | else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
927 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) |
| 1250 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
928 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
| 1251 | else |
929 | else |
| 1252 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
930 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
| 1253 | break; |
931 | break; |
| 1254 | } |
932 | } |
| Line 1331... | Line 1009... | ||
| 1331 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1009 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1332 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
1010 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
| 1333 | break; |
1011 | break; |
| 1334 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1012 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1335 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1013 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1336 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) |
1014 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1337 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1015 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
| 1338 | else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
1016 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1339 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1017 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
| 1340 | else |
1018 | else |
| 1341 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
1019 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
| 1342 | break; |
1020 | break; |
| 1343 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1021 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1344 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1022 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1345 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) |
1023 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1346 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
1024 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
| 1347 | else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
1025 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1348 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1026 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
| 1349 | else |
1027 | else |
| 1350 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
1028 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
| 1351 | break; |
1029 | break; |
| 1352 | } |
1030 | } |
| Line 1371... | Line 1049... | ||
| 1371 | break; |
1049 | break; |
| 1372 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1050 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1373 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
1051 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
| 1374 | break; |
1052 | break; |
| 1375 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1053 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1376 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) |
1054 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1377 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1055 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1378 | else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
1056 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1379 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1057 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1380 | else |
1058 | else |
| 1381 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
1059 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
| 1382 | break; |
1060 | break; |
| 1383 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1061 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1384 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) |
1062 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1385 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1063 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1386 | else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) |
1064 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 1387 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1065 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1388 | else |
1066 | else |
| 1389 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
1067 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
| 1390 | break; |
1068 | break; |
| 1391 | } |
1069 | } |
| Line 1446... | Line 1124... | ||
| 1446 | dig->dig_block = radeon_crtc->crtc_id; |
1124 | dig->dig_block = radeon_crtc->crtc_id; |
| 1447 | } |
1125 | } |
| 1448 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1126 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
| Line 1449... | Line 1127... | ||
| 1449 | 1127 | ||
| 1450 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
- | |
| 1451 | atombios_overscan_setup(encoder, mode, adjusted_mode); |
- | |
| 1452 | atombios_scaler_setup(encoder); |
1128 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| Line 1453... | Line 1129... | ||
| 1453 | atombios_set_encoder_crtc_source(encoder); |
1129 | atombios_set_encoder_crtc_source(encoder); |
| 1454 | 1130 | ||
| 1455 | if (ASIC_IS_AVIVO(rdev)) { |
1131 | if (ASIC_IS_AVIVO(rdev)) { |
| 1456 | if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
1132 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
| 1457 | atombios_yuv_setup(encoder, true); |
1133 | atombios_yuv_setup(encoder, true); |
| 1458 | else |
1134 | else |
| Line 1489... | Line 1165... | ||
| 1489 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
1165 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1490 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1166 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1491 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1167 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1492 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1493 | atombios_dac_setup(encoder, ATOM_ENABLE); |
1169 | atombios_dac_setup(encoder, ATOM_ENABLE); |
| 1494 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
1170 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
| 1495 | atombios_tv_setup(encoder, ATOM_ENABLE); |
1171 | atombios_tv_setup(encoder, ATOM_ENABLE); |
| 1496 | break; |
1172 | break; |
| 1497 | } |
1173 | } |
| 1498 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
1174 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
| 1499 | } |
1175 | } |
| Line 1500... | Line 1176... | ||
| 1500 | 1176 | ||
| 1501 | static bool |
1177 | static bool |
| 1502 | atombios_dac_load_detect(struct drm_encoder *encoder) |
1178 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
| 1503 | { |
1179 | { |
| 1504 | struct drm_device *dev = encoder->dev; |
1180 | struct drm_device *dev = encoder->dev; |
| 1505 | struct radeon_device *rdev = dev->dev_private; |
1181 | struct radeon_device *rdev = dev->dev_private; |
| - | 1182 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
| Line 1506... | Line 1183... | ||
| 1506 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1183 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 1507 | 1184 | ||
| 1508 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
1185 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
| 1509 | ATOM_DEVICE_CV_SUPPORT | |
1186 | ATOM_DEVICE_CV_SUPPORT | |
| Line 1522... | Line 1199... | ||
| 1522 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
1199 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
| 1523 | args.sDacload.ucDacType = ATOM_DAC_A; |
1200 | args.sDacload.ucDacType = ATOM_DAC_A; |
| 1524 | else |
1201 | else |
| 1525 | args.sDacload.ucDacType = ATOM_DAC_B; |
1202 | args.sDacload.ucDacType = ATOM_DAC_B; |
| Line 1526... | Line 1203... | ||
| 1526 | 1203 | ||
| 1527 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) |
1204 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
| 1528 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
1205 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
| 1529 | else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) |
1206 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
| 1530 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
1207 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
| 1531 | else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
1208 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
| 1532 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1209 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
| 1533 | if (crev >= 3) |
1210 | if (crev >= 3) |
| 1534 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1211 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
| 1535 | } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1212 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 1536 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1213 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
| 1537 | if (crev >= 3) |
1214 | if (crev >= 3) |
| 1538 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
1215 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
| Line 1549... | Line 1226... | ||
| 1549 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
1226 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
| 1550 | { |
1227 | { |
| 1551 | struct drm_device *dev = encoder->dev; |
1228 | struct drm_device *dev = encoder->dev; |
| 1552 | struct radeon_device *rdev = dev->dev_private; |
1229 | struct radeon_device *rdev = dev->dev_private; |
| 1553 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1230 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| - | 1231 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| 1554 | uint32_t bios_0_scratch; |
1232 | uint32_t bios_0_scratch; |
| Line 1555... | Line 1233... | ||
| 1555 | 1233 | ||
| 1556 | if (!atombios_dac_load_detect(encoder)) { |
1234 | if (!atombios_dac_load_detect(encoder, connector)) { |
| 1557 | DRM_DEBUG("detect returned false \n"); |
1235 | DRM_DEBUG("detect returned false \n"); |
| 1558 | return connector_status_unknown; |
1236 | return connector_status_unknown; |
| Line 1559... | Line 1237... | ||
| 1559 | } |
1237 | } |
| 1560 | 1238 | ||
| 1561 | if (rdev->family >= CHIP_R600) |
1239 | if (rdev->family >= CHIP_R600) |
| 1562 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
1240 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
| Line 1563... | Line 1241... | ||
| 1563 | else |
1241 | else |
| 1564 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1242 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
| 1565 | 1243 | ||
| 1566 | DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch); |
1244 | DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
| - | 1245 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
|
| 1567 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
1246 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
| 1568 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1247 | return connector_status_connected; |
| 1569 | return connector_status_connected; |
1248 | } |
| - | 1249 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
|
| 1570 | } else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
1250 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
| 1571 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1251 | return connector_status_connected; |
| 1572 | return connector_status_connected; |
1252 | } |
| - | 1253 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
|
| 1573 | } else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
1254 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
| 1574 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1255 | return connector_status_connected; |
| 1575 | return connector_status_connected; |
1256 | } |
| 1576 | } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
1257 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 1577 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1258 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
| 1578 | return connector_status_connected; /* CTV */ |
1259 | return connector_status_connected; /* CTV */ |
| Line 1584... | Line 1265... | ||
| 1584 | 1265 | ||
| 1585 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
1266 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
| 1586 | { |
1267 | { |
| 1587 | radeon_atom_output_lock(encoder, true); |
1268 | radeon_atom_output_lock(encoder, true); |
| - | 1269 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
|
| - | 1270 | ||
| 1588 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
1271 | radeon_encoder_set_active_device(encoder); |
| Line 1589... | Line 1272... | ||
| 1589 | } |
1272 | } |
| 1590 | 1273 | ||
| 1591 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
1274 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
| 1592 | { |
1275 | { |
| 1593 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
1276 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
| Line -... | Line 1277... | ||
| - | 1277 | radeon_atom_output_lock(encoder, false); |
|
| - | 1278 | } |
|
| - | 1279 | ||
| - | 1280 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
|
| - | 1281 | { |
|
| - | 1282 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
|
| - | 1283 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
|
| 1594 | radeon_atom_output_lock(encoder, false); |
1284 | radeon_encoder->active_device = 0; |
| 1595 | } |
1285 | } |
| 1596 | 1286 | ||
| 1597 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
1287 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
| 1598 | .dpms = radeon_atom_encoder_dpms, |
1288 | .dpms = radeon_atom_encoder_dpms, |
| 1599 | .mode_fixup = radeon_atom_mode_fixup, |
1289 | .mode_fixup = radeon_atom_mode_fixup, |
| - | 1290 | .prepare = radeon_atom_encoder_prepare, |
|
| 1600 | .prepare = radeon_atom_encoder_prepare, |
1291 | .mode_set = radeon_atom_encoder_mode_set, |
| 1601 | .mode_set = radeon_atom_encoder_mode_set, |
1292 | .commit = radeon_atom_encoder_commit, |
| Line 1602... | Line 1293... | ||
| 1602 | .commit = radeon_atom_encoder_commit, |
1293 | .disable = radeon_atom_encoder_disable, |
| 1603 | /* no detect for TMDS/LVDS yet */ |
1294 | /* no detect for TMDS/LVDS yet */ |
| Line 1622... | Line 1313... | ||
| 1622 | 1313 | ||
| 1623 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
1314 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
| 1624 | .destroy = radeon_enc_destroy, |
1315 | .destroy = radeon_enc_destroy, |
| Line -... | Line 1316... | ||
| - | 1316 | }; |
|
| - | 1317 | ||
| - | 1318 | struct radeon_encoder_atom_dac * |
|
| - | 1319 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
|
| - | 1320 | { |
|
| - | 1321 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
|
| - | 1322 | ||
| - | 1323 | if (!dac) |
|
| - | 1324 | return NULL; |
|
| - | 1325 | ||
| - | 1326 | dac->tv_std = TV_STD_NTSC; |
|
| - | 1327 | return dac; |
|
| 1625 | }; |
1328 | } |
| 1626 | 1329 | ||
| 1627 | struct radeon_encoder_atom_dig * |
1330 | struct radeon_encoder_atom_dig * |
| 1628 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
1331 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
| Line 1665... | Line 1368... | ||
| 1665 | 1368 | ||
| Line 1666... | Line 1369... | ||
| 1666 | radeon_encoder->enc_priv = NULL; |
1369 | radeon_encoder->enc_priv = NULL; |
| 1667 | 1370 | ||
| - | 1371 | radeon_encoder->encoder_id = encoder_id; |
|
| Line 1668... | Line 1372... | ||
| 1668 | radeon_encoder->encoder_id = encoder_id; |
1372 | radeon_encoder->devices = supported_device; |
| 1669 | radeon_encoder->devices = supported_device; |
1373 | radeon_encoder->rmx_type = RMX_OFF; |
| 1670 | 1374 | ||
| 1671 | switch (radeon_encoder->encoder_id) { |
1375 | switch (radeon_encoder->encoder_id) { |
| Line 1689... | Line 1393... | ||
| 1689 | break; |
1393 | break; |
| 1690 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
1394 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1691 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
1395 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1692 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
1396 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1693 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
1397 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
| - | 1398 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
|
| 1694 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
1399 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
| 1695 | break; |
1400 | break; |
| 1696 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1401 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 1697 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1402 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1698 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
1403 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 1699 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
1404 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1700 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1405 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1701 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
1406 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1702 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
1407 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| - | 1408 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
|
| - | 1409 | radeon_encoder->rmx_type = RMX_FULL; |
|
| - | 1410 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
|
| - | 1411 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
|
| - | 1412 | } else { |
|
| 1703 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
1413 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 1704 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
1414 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
| - | 1415 | } |
|
| 1705 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
1416 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
| 1706 | break; |
1417 | break; |
| 1707 | } |
1418 | } |
| 1708 | } |
1419 | } |