Rev 6938 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 6938 | Rev 7146 | ||
|---|---|---|---|
| Line 87... | Line 87... | ||
| 87 | 87 | ||
| Line 88... | Line 88... | ||
| 88 | WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); |
88 | WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); |
| Line 89... | Line 89... | ||
| 89 | 89 | ||
| - | 90 | do { |
|
| - | 91 | unsigned value1, value2; |
|
| 90 | do { |
92 | udelay(10); |
| - | 93 | temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); |
|
| - | 94 | ||
| - | 95 | value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK; |
|
| - | 96 | value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT; |
|
| - | 97 | ||
| - | 98 | if (!value1 && !value2) |
|
| 91 | temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); |
99 | break; |
| Line 92... | Line 100... | ||
| 92 | } while ((temp & 0x1) && retries++ < 10000); |
100 | } while (retries++ < 50); |
| 93 | 101 | ||
| Line 94... | Line 102... | ||
| 94 | if (retries == 10000) |
102 | if (retries == 10000) |
| Line 148... | Line 156... | ||
| 148 | mst_conn->enabled_attribs = idx; |
156 | mst_conn->enabled_attribs = idx; |
| 149 | return 0; |
157 | return 0; |
| 150 | } |
158 | } |
| 151 | 159 | ||
| Line 152... | Line 160... | ||
| 152 | static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y) |
160 | static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp) |
| 153 | { |
161 | { |
| 154 | struct drm_device *dev = mst->base.dev; |
162 | struct drm_device *dev = mst->base.dev; |
| 155 | struct radeon_device *rdev = dev->dev_private; |
163 | struct radeon_device *rdev = dev->dev_private; |
| 156 | struct radeon_encoder_mst *mst_enc = mst->enc_priv; |
164 | struct radeon_encoder_mst *mst_enc = mst->enc_priv; |
| 157 | uint32_t val, temp; |
165 | uint32_t val, temp; |
| 158 | uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); |
166 | uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); |
| 159 | int retries = 0; |
167 | int retries = 0; |
| - | 168 | uint32_t x = drm_fixp2int(avg_time_slots_per_mtp); |
|
| - | 169 | uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26); |
|
| Line 160... | Line 170... | ||
| 160 | 170 | ||
| Line 161... | Line 171... | ||
| 161 | val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y); |
171 | val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y); |
| Line 162... | Line 172... | ||
| 162 | 172 | ||
| 163 | WREG32(NI_DP_MSE_RATE_CNTL + offset, val); |
173 | WREG32(NI_DP_MSE_RATE_CNTL + offset, val); |
| - | 174 | ||
| 164 | 175 | do { |
|
| Line 165... | Line 176... | ||
| 165 | do { |
176 | temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); |
| 166 | temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); |
177 | udelay(10); |
| 167 | } while ((temp & 0x1) && (retries++ < 10000)); |
178 | } while ((temp & 0x1) && (retries++ < 10000)); |
| Line 244... | Line 255... | ||
| 244 | drm_connector_cleanup(connector); |
255 | drm_connector_cleanup(connector); |
| 245 | kfree(radeon_connector); |
256 | kfree(radeon_connector); |
| 246 | } |
257 | } |
| 247 | 258 | ||
| Line 248... | Line -... | ||
| 248 | static int radeon_connector_dpms(struct drm_connector *connector, int mode) |
- | |
| 249 | { |
- | |
| 250 | DRM_DEBUG_KMS("\n"); |
- | |
| 251 | return 0; |
- | |
| 252 | } |
- | |
| 253 | - | ||
| 254 | static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = { |
259 | static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = { |
| 255 | .dpms = radeon_connector_dpms, |
260 | .dpms = drm_helper_connector_dpms, |
| 256 | .detect = radeon_dp_mst_detect, |
261 | .detect = radeon_dp_mst_detect, |
| 257 | .fill_modes = drm_helper_probe_single_connector_modes, |
262 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 258 | .destroy = radeon_dp_mst_connector_destroy, |
263 | .destroy = radeon_dp_mst_connector_destroy, |
| 259 | }; |
264 | }; |
| Line 392... | Line 397... | ||
| 392 | struct radeon_connector *radeon_connector; |
397 | struct radeon_connector *radeon_connector; |
| 393 | struct drm_crtc *crtc; |
398 | struct drm_crtc *crtc; |
| 394 | struct radeon_crtc *radeon_crtc; |
399 | struct radeon_crtc *radeon_crtc; |
| 395 | int ret, slots; |
400 | int ret, slots; |
| 396 | 401 | s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp; |
|
| 397 | if (!ASIC_IS_DCE5(rdev)) { |
- | |
| - | 402 | if (!ASIC_IS_DCE5(rdev)) { |
|
| 398 | DRM_ERROR("got mst dpms on non-DCE5\n"); |
403 | DRM_ERROR("got mst dpms on non-DCE5\n"); |
| 399 | return; |
404 | return; |
| 400 | } |
405 | } |
| 401 | 406 | ||
| Line 454... | Line 459... | ||
| 454 | radeon_connector->mst_port->hpd.hpd, true); |
459 | radeon_connector->mst_port->hpd.hpd, true); |
| 455 | 460 | ||
| Line 456... | Line 461... | ||
| 456 | mst_enc->enc_active = true; |
461 | mst_enc->enc_active = true; |
| 457 | radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); |
462 | radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); |
| - | 463 | ||
| - | 464 | fixed_pbn = drm_int2fixp(mst_enc->pbn); |
|
| - | 465 | fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div); |
|
| - | 466 | avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot); |
|
| 458 | radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0); |
467 | radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp); |
| Line 459... | Line 468... | ||
| 459 | 468 | ||
| 460 | atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0, |
469 | atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0, |
| 461 | mst_enc->fe); |
470 | mst_enc->fe); |
| Line 508... | Line 517... | ||
| 508 | struct drm_display_mode *adjusted_mode) |
517 | struct drm_display_mode *adjusted_mode) |
| 509 | { |
518 | { |
| 510 | struct radeon_encoder_mst *mst_enc; |
519 | struct radeon_encoder_mst *mst_enc; |
| 511 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
520 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 512 | int bpp = 24; |
521 | struct radeon_connector_atom_dig *dig_connector; |
| - | 522 | int bpp = 24; |
|
| 513 | 523 | ||
| Line 514... | Line 524... | ||
| 514 | mst_enc = radeon_encoder->enc_priv; |
524 | mst_enc = radeon_encoder->enc_priv; |
| Line 515... | Line 525... | ||
| 515 | 525 | ||
| Line 521... | Line 531... | ||
| 521 | mst_enc->connector->devices, mst_enc->primary->base.encoder_type); |
531 | mst_enc->connector->devices, mst_enc->primary->base.encoder_type); |
| 522 | 532 | ||
| Line 523... | Line 533... | ||
| 523 | 533 | ||
| 524 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
- | |
| 525 | { |
- | |
| 526 | struct radeon_connector_atom_dig *dig_connector; |
534 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 527 | dig_connector = mst_enc->connector->con_priv; |
535 | dig_connector = mst_enc->connector->con_priv; |
| 528 | dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); |
536 | dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); |
| 529 | dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); |
537 | dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); |
| 530 | DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector, |
538 | DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector, |
| 531 | dig_connector->dp_lane_count, dig_connector->dp_clock); |
- | |
| 532 | } |
539 | dig_connector->dp_lane_count, dig_connector->dp_clock); |
| 533 | return true; |
540 | return true; |
| Line 534... | Line 541... | ||
| 534 | } |
541 | } |
| 535 | 542 | ||