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Rev 1268 | Rev 1404 | ||
---|---|---|---|
Line 232... | Line 232... | ||
232 | "INTERNAL_KLDSCP_LVTMA", |
232 | "INTERNAL_KLDSCP_LVTMA", |
233 | "INTERNAL_UNIPHY1", |
233 | "INTERNAL_UNIPHY1", |
234 | "INTERNAL_UNIPHY2", |
234 | "INTERNAL_UNIPHY2", |
235 | }; |
235 | }; |
Line 236... | Line 236... | ||
236 | 236 | ||
237 | static const char *connector_names[13] = { |
237 | static const char *connector_names[15] = { |
238 | "Unknown", |
238 | "Unknown", |
239 | "VGA", |
239 | "VGA", |
240 | "DVI-I", |
240 | "DVI-I", |
241 | "DVI-D", |
241 | "DVI-D", |
Line 246... | Line 246... | ||
246 | "Component", |
246 | "Component", |
247 | "DIN", |
247 | "DIN", |
248 | "DisplayPort", |
248 | "DisplayPort", |
249 | "HDMI-A", |
249 | "HDMI-A", |
250 | "HDMI-B", |
250 | "HDMI-B", |
- | 251 | "TV", |
|
- | 252 | "eDP", |
|
- | 253 | }; |
|
- | 254 | ||
- | 255 | static const char *hpd_names[7] = { |
|
- | 256 | "NONE", |
|
- | 257 | "HPD1", |
|
- | 258 | "HPD2", |
|
- | 259 | "HPD3", |
|
- | 260 | "HPD4", |
|
- | 261 | "HPD5", |
|
- | 262 | "HPD6", |
|
251 | }; |
263 | }; |
Line 252... | Line 264... | ||
252 | 264 | ||
253 | static void radeon_print_display_setup(struct drm_device *dev) |
265 | static void radeon_print_display_setup(struct drm_device *dev) |
254 | { |
266 | { |
Line 262... | Line 274... | ||
262 | DRM_INFO("Radeon Display Connectors\n"); |
274 | DRM_INFO("Radeon Display Connectors\n"); |
263 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
275 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
264 | radeon_connector = to_radeon_connector(connector); |
276 | radeon_connector = to_radeon_connector(connector); |
265 | DRM_INFO("Connector %d:\n", i); |
277 | DRM_INFO("Connector %d:\n", i); |
266 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
278 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
- | 279 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
|
- | 280 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
|
267 | if (radeon_connector->ddc_bus) |
281 | if (radeon_connector->ddc_bus) { |
268 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
282 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
269 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
283 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
270 | radeon_connector->ddc_bus->rec.mask_data_reg, |
284 | radeon_connector->ddc_bus->rec.mask_data_reg, |
271 | radeon_connector->ddc_bus->rec.a_clk_reg, |
285 | radeon_connector->ddc_bus->rec.a_clk_reg, |
272 | radeon_connector->ddc_bus->rec.a_data_reg, |
286 | radeon_connector->ddc_bus->rec.a_data_reg, |
273 | radeon_connector->ddc_bus->rec.put_clk_reg, |
287 | radeon_connector->ddc_bus->rec.en_clk_reg, |
274 | radeon_connector->ddc_bus->rec.put_data_reg, |
288 | radeon_connector->ddc_bus->rec.en_data_reg, |
275 | radeon_connector->ddc_bus->rec.get_clk_reg, |
289 | radeon_connector->ddc_bus->rec.y_clk_reg, |
276 | radeon_connector->ddc_bus->rec.get_data_reg); |
290 | radeon_connector->ddc_bus->rec.y_data_reg); |
- | 291 | } else { |
|
- | 292 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
|
- | 293 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
|
- | 294 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
|
- | 295 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
|
- | 296 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
|
- | 297 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
|
- | 298 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
|
- | 299 | } |
|
277 | DRM_INFO(" Encoders:\n"); |
300 | DRM_INFO(" Encoders:\n"); |
278 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
301 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
279 | radeon_encoder = to_radeon_encoder(encoder); |
302 | radeon_encoder = to_radeon_encoder(encoder); |
280 | devices = radeon_encoder->devices & radeon_connector->devices; |
303 | devices = radeon_encoder->devices & radeon_connector->devices; |
281 | if (devices) { |
304 | if (devices) { |
Line 315... | Line 338... | ||
315 | if (rdev->is_atom_bios) { |
338 | if (rdev->is_atom_bios) { |
316 | if (rdev->family >= CHIP_R600) |
339 | if (rdev->family >= CHIP_R600) |
317 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
340 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
318 | else |
341 | else |
319 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
342 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
320 | } else |
343 | } else { |
321 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
344 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
- | 345 | if (ret == false) |
|
- | 346 | ret = radeon_get_legacy_connector_info_from_table(dev); |
|
- | 347 | } |
|
322 | } else { |
348 | } else { |
323 | if (!ASIC_IS_AVIVO(rdev)) |
349 | if (!ASIC_IS_AVIVO(rdev)) |
324 | ret = radeon_get_legacy_connector_info_from_table(dev); |
350 | ret = radeon_get_legacy_connector_info_from_table(dev); |
325 | } |
351 | } |
326 | if (ret) { |
352 | if (ret) { |
- | 353 | radeon_setup_encoder_clones(dev); |
|
327 | radeon_print_display_setup(dev); |
354 | radeon_print_display_setup(dev); |
328 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
355 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
329 | radeon_ddc_dump(drm_connector); |
356 | radeon_ddc_dump(drm_connector); |
330 | } |
357 | } |
Line 334... | Line 361... | ||
334 | 361 | ||
335 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
362 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
336 | { |
363 | { |
Line -... | Line 364... | ||
- | 364 | int ret = 0; |
|
- | 365 | ||
- | 366 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
|
- | 367 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { |
|
- | 368 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
|
- | 369 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
|
- | 370 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) |
|
337 | int ret = 0; |
371 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
338 | 372 | } |
|
339 | if (!radeon_connector->ddc_bus) |
373 | if (!radeon_connector->ddc_bus) |
340 | return -1; |
374 | return -1; |
341 | if (!radeon_connector->edid) { |
375 | if (!radeon_connector->edid) { |
342 | radeon_i2c_do_lock(radeon_connector, 1); |
376 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
343 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
377 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
Line 344... | Line 378... | ||
344 | radeon_i2c_do_lock(radeon_connector, 0); |
378 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
345 | } |
379 | } |
346 | 380 | ||
Line 359... | Line 393... | ||
359 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
393 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
360 | int ret = 0; |
394 | int ret = 0; |
Line 361... | Line 395... | ||
361 | 395 | ||
362 | if (!radeon_connector->ddc_bus) |
396 | if (!radeon_connector->ddc_bus) |
363 | return -1; |
397 | return -1; |
364 | radeon_i2c_do_lock(radeon_connector, 1); |
398 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
365 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
399 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
366 | radeon_i2c_do_lock(radeon_connector, 0); |
400 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
367 | if (edid) { |
401 | if (edid) { |
368 | kfree(edid); |
402 | kfree(edid); |
369 | } |
403 | } |
370 | return ret; |
404 | return ret; |
Line 384... | Line 418... | ||
384 | uint64_t freq, |
418 | uint64_t freq, |
385 | uint32_t *dot_clock_p, |
419 | uint32_t *dot_clock_p, |
386 | uint32_t *fb_div_p, |
420 | uint32_t *fb_div_p, |
387 | uint32_t *frac_fb_div_p, |
421 | uint32_t *frac_fb_div_p, |
388 | uint32_t *ref_div_p, |
422 | uint32_t *ref_div_p, |
389 | uint32_t *post_div_p, |
423 | uint32_t *post_div_p) |
390 | int flags) |
- | |
391 | { |
424 | { |
392 | uint32_t min_ref_div = pll->min_ref_div; |
425 | uint32_t min_ref_div = pll->min_ref_div; |
393 | uint32_t max_ref_div = pll->max_ref_div; |
426 | uint32_t max_ref_div = pll->max_ref_div; |
- | 427 | uint32_t min_post_div = pll->min_post_div; |
|
- | 428 | uint32_t max_post_div = pll->max_post_div; |
|
394 | uint32_t min_fractional_feed_div = 0; |
429 | uint32_t min_fractional_feed_div = 0; |
395 | uint32_t max_fractional_feed_div = 0; |
430 | uint32_t max_fractional_feed_div = 0; |
396 | uint32_t best_vco = pll->best_vco; |
431 | uint32_t best_vco = pll->best_vco; |
397 | uint32_t best_post_div = 1; |
432 | uint32_t best_post_div = 1; |
398 | uint32_t best_ref_div = 1; |
433 | uint32_t best_ref_div = 1; |
Line 404... | Line 439... | ||
404 | uint32_t post_div; |
439 | uint32_t post_div; |
Line 405... | Line 440... | ||
405 | 440 | ||
406 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
441 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
Line 407... | Line 442... | ||
407 | freq = freq * 1000; |
442 | freq = freq * 1000; |
408 | 443 | ||
409 | if (flags & RADEON_PLL_USE_REF_DIV) |
444 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
410 | min_ref_div = max_ref_div = pll->reference_div; |
445 | min_ref_div = max_ref_div = pll->reference_div; |
411 | else { |
446 | else { |
412 | while (min_ref_div < max_ref_div-1) { |
447 | while (min_ref_div < max_ref_div-1) { |
Line 419... | Line 454... | ||
419 | else |
454 | else |
420 | break; |
455 | break; |
421 | } |
456 | } |
422 | } |
457 | } |
Line -... | Line 458... | ||
- | 458 | ||
- | 459 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
|
- | 460 | min_post_div = max_post_div = pll->post_div; |
|
423 | 461 | ||
424 | if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
462 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
425 | min_fractional_feed_div = pll->min_frac_feedback_div; |
463 | min_fractional_feed_div = pll->min_frac_feedback_div; |
426 | max_fractional_feed_div = pll->max_frac_feedback_div; |
464 | max_fractional_feed_div = pll->max_frac_feedback_div; |
Line 427... | Line 465... | ||
427 | } |
465 | } |
428 | 466 | ||
Line 429... | Line 467... | ||
429 | for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { |
467 | for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { |
430 | uint32_t ref_div; |
468 | uint32_t ref_div; |
Line 431... | Line 469... | ||
431 | 469 | ||
432 | if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
470 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
433 | continue; |
471 | continue; |
434 | 472 | ||
435 | /* legacy radeons only have a few post_divs */ |
473 | /* legacy radeons only have a few post_divs */ |
436 | if (flags & RADEON_PLL_LEGACY) { |
474 | if (pll->flags & RADEON_PLL_LEGACY) { |
437 | if ((post_div == 5) || |
475 | if ((post_div == 5) || |
Line 478... | Line 516... | ||
478 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
516 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
479 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
517 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
480 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
518 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
481 | current_freq = radeon_div(tmp, ref_div * post_div); |
519 | current_freq = radeon_div(tmp, ref_div * post_div); |
Line 482... | Line 520... | ||
482 | 520 | ||
483 | if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
521 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
484 | error = freq - current_freq; |
522 | error = freq - current_freq; |
485 | error = error < 0 ? 0xffffffff : error; |
523 | error = error < 0 ? 0xffffffff : error; |
486 | } else |
524 | } else |
487 | error = abs(current_freq - freq); |
525 | error = abs(current_freq - freq); |
Line 505... | Line 543... | ||
505 | best_feedback_div = feedback_div; |
543 | best_feedback_div = feedback_div; |
506 | best_frac_feedback_div = frac_feedback_div; |
544 | best_frac_feedback_div = frac_feedback_div; |
507 | best_freq = current_freq; |
545 | best_freq = current_freq; |
508 | best_error = error; |
546 | best_error = error; |
509 | best_vco_diff = vco_diff; |
547 | best_vco_diff = vco_diff; |
510 | } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
548 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
511 | ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
549 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
512 | ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
550 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
513 | ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
551 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
514 | ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
552 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
515 | ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
553 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
516 | best_post_div = post_div; |
554 | best_post_div = post_div; |
517 | best_ref_div = ref_div; |
555 | best_ref_div = ref_div; |
518 | best_feedback_div = feedback_div; |
556 | best_feedback_div = feedback_div; |
519 | best_frac_feedback_div = frac_feedback_div; |
557 | best_frac_feedback_div = frac_feedback_div; |
520 | best_freq = current_freq; |
558 | best_freq = current_freq; |
Line 540... | Line 578... | ||
540 | *frac_fb_div_p = best_frac_feedback_div; |
578 | *frac_fb_div_p = best_frac_feedback_div; |
541 | *ref_div_p = best_ref_div; |
579 | *ref_div_p = best_ref_div; |
542 | *post_div_p = best_post_div; |
580 | *post_div_p = best_post_div; |
543 | } |
581 | } |
Line -... | Line 582... | ||
- | 582 | ||
- | 583 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
|
- | 584 | uint64_t freq, |
|
- | 585 | uint32_t *dot_clock_p, |
|
- | 586 | uint32_t *fb_div_p, |
|
- | 587 | uint32_t *frac_fb_div_p, |
|
- | 588 | uint32_t *ref_div_p, |
|
- | 589 | uint32_t *post_div_p) |
|
- | 590 | { |
|
- | 591 | fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; |
|
- | 592 | fixed20_12 pll_out_max, pll_out_min; |
|
- | 593 | fixed20_12 pll_in_max, pll_in_min; |
|
- | 594 | fixed20_12 reference_freq; |
|
- | 595 | fixed20_12 error, ffreq, a, b; |
|
- | 596 | ||
- | 597 | pll_out_max.full = rfixed_const(pll->pll_out_max); |
|
- | 598 | pll_out_min.full = rfixed_const(pll->pll_out_min); |
|
- | 599 | pll_in_max.full = rfixed_const(pll->pll_in_max); |
|
- | 600 | pll_in_min.full = rfixed_const(pll->pll_in_min); |
|
- | 601 | reference_freq.full = rfixed_const(pll->reference_freq); |
|
- | 602 | do_div(freq, 10); |
|
- | 603 | ffreq.full = rfixed_const(freq); |
|
- | 604 | error.full = rfixed_const(100 * 100); |
|
- | 605 | ||
- | 606 | /* max p */ |
|
- | 607 | p.full = rfixed_div(pll_out_max, ffreq); |
|
- | 608 | p.full = rfixed_floor(p); |
|
- | 609 | ||
- | 610 | /* min m */ |
|
- | 611 | m.full = rfixed_div(reference_freq, pll_in_max); |
|
- | 612 | m.full = rfixed_ceil(m); |
|
- | 613 | ||
- | 614 | while (1) { |
|
- | 615 | n.full = rfixed_div(ffreq, reference_freq); |
|
- | 616 | n.full = rfixed_mul(n, m); |
|
- | 617 | n.full = rfixed_mul(n, p); |
|
- | 618 | ||
- | 619 | f_vco.full = rfixed_div(n, m); |
|
- | 620 | f_vco.full = rfixed_mul(f_vco, reference_freq); |
|
- | 621 | ||
- | 622 | f_pclk.full = rfixed_div(f_vco, p); |
|
- | 623 | ||
- | 624 | if (f_pclk.full > ffreq.full) |
|
- | 625 | error.full = f_pclk.full - ffreq.full; |
|
- | 626 | else |
|
- | 627 | error.full = ffreq.full - f_pclk.full; |
|
- | 628 | error.full = rfixed_div(error, f_pclk); |
|
- | 629 | a.full = rfixed_const(100 * 100); |
|
- | 630 | error.full = rfixed_mul(error, a); |
|
- | 631 | ||
- | 632 | a.full = rfixed_mul(m, p); |
|
- | 633 | a.full = rfixed_div(n, a); |
|
- | 634 | best_freq.full = rfixed_mul(reference_freq, a); |
|
- | 635 | ||
- | 636 | if (rfixed_trunc(error) < 25) |
|
- | 637 | break; |
|
- | 638 | ||
- | 639 | a.full = rfixed_const(1); |
|
- | 640 | m.full = m.full + a.full; |
|
- | 641 | a.full = rfixed_div(reference_freq, m); |
|
- | 642 | if (a.full >= pll_in_min.full) |
|
- | 643 | continue; |
|
- | 644 | ||
- | 645 | m.full = rfixed_div(reference_freq, pll_in_max); |
|
- | 646 | m.full = rfixed_ceil(m); |
|
- | 647 | a.full= rfixed_const(1); |
|
- | 648 | p.full = p.full - a.full; |
|
- | 649 | a.full = rfixed_mul(p, ffreq); |
|
- | 650 | if (a.full >= pll_out_min.full) |
|
- | 651 | continue; |
|
- | 652 | else { |
|
- | 653 | DRM_ERROR("Unable to find pll dividers\n"); |
|
- | 654 | break; |
|
- | 655 | } |
|
- | 656 | } |
|
- | 657 | ||
- | 658 | a.full = rfixed_const(10); |
|
- | 659 | b.full = rfixed_mul(n, a); |
|
- | 660 | ||
- | 661 | frac_n.full = rfixed_floor(n); |
|
- | 662 | frac_n.full = rfixed_mul(frac_n, a); |
|
- | 663 | frac_n.full = b.full - frac_n.full; |
|
- | 664 | ||
- | 665 | *dot_clock_p = rfixed_trunc(best_freq); |
|
- | 666 | *fb_div_p = rfixed_trunc(n); |
|
- | 667 | *frac_fb_div_p = rfixed_trunc(frac_n); |
|
- | 668 | *ref_div_p = rfixed_trunc(m); |
|
- | 669 | *post_div_p = rfixed_trunc(p); |
|
- | 670 | ||
- | 671 | DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); |
|
- | 672 | } |
|
544 | 673 | ||
545 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
674 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
546 | { |
675 | { |
547 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
676 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
Line 630... | Line 759... | ||
630 | { TV_STD_SCART_PAL, "scart-pal" }, |
759 | { TV_STD_SCART_PAL, "scart-pal" }, |
631 | { TV_STD_PAL_CN, "pal-cn" }, |
760 | { TV_STD_PAL_CN, "pal-cn" }, |
632 | { TV_STD_SECAM, "secam" }, |
761 | { TV_STD_SECAM, "secam" }, |
633 | }; |
762 | }; |
Line 634... | Line 763... | ||
634 | 763 | ||
635 | int radeon_modeset_create_props(struct radeon_device *rdev) |
764 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
636 | { |
765 | { |
Line 637... | Line 766... | ||
637 | int i, sz; |
766 | int i, sz; |
638 | 767 | ||
Line 643... | Line 772... | ||
643 | "coherent", 2); |
772 | "coherent", 2); |
644 | if (!rdev->mode_info.coherent_mode_property) |
773 | if (!rdev->mode_info.coherent_mode_property) |
645 | return -ENOMEM; |
774 | return -ENOMEM; |
Line 646... | Line 775... | ||
646 | 775 | ||
647 | rdev->mode_info.coherent_mode_property->values[0] = 0; |
776 | rdev->mode_info.coherent_mode_property->values[0] = 0; |
648 | rdev->mode_info.coherent_mode_property->values[0] = 1; |
777 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
Line 649... | Line 778... | ||
649 | } |
778 | } |
650 | 779 | ||
651 | if (!ASIC_IS_AVIVO(rdev)) { |
780 | if (!ASIC_IS_AVIVO(rdev)) { |
Line 667... | Line 796... | ||
667 | DRM_MODE_PROP_RANGE, |
796 | DRM_MODE_PROP_RANGE, |
668 | "load detection", 2); |
797 | "load detection", 2); |
669 | if (!rdev->mode_info.load_detect_property) |
798 | if (!rdev->mode_info.load_detect_property) |
670 | return -ENOMEM; |
799 | return -ENOMEM; |
671 | rdev->mode_info.load_detect_property->values[0] = 0; |
800 | rdev->mode_info.load_detect_property->values[0] = 0; |
672 | rdev->mode_info.load_detect_property->values[0] = 1; |
801 | rdev->mode_info.load_detect_property->values[1] = 1; |
Line 673... | Line 802... | ||
673 | 802 | ||
Line 674... | Line 803... | ||
674 | drm_mode_create_scaling_mode_property(rdev->ddev); |
803 | drm_mode_create_scaling_mode_property(rdev->ddev); |
675 | 804 | ||
Line 724... | Line 853... | ||
724 | /* okay we should have all the bios connectors */ |
853 | /* okay we should have all the bios connectors */ |
725 | ret = radeon_setup_enc_conn(rdev->ddev); |
854 | ret = radeon_setup_enc_conn(rdev->ddev); |
726 | if (!ret) { |
855 | if (!ret) { |
727 | return ret; |
856 | return ret; |
728 | } |
857 | } |
- | 858 | /* initialize hpd */ |
|
- | 859 | radeon_hpd_init(rdev); |
|
729 | drm_helper_initial_config(rdev->ddev); |
860 | drm_helper_initial_config(rdev->ddev); |
730 | return 0; |
861 | return 0; |
731 | } |
862 | } |
Line 732... | Line 863... | ||
732 | 863 | ||
733 | void radeon_modeset_fini(struct radeon_device *rdev) |
864 | void radeon_modeset_fini(struct radeon_device *rdev) |
734 | { |
865 | { |
- | 866 | if (rdev->mode_info.mode_config_initialized) { |
|
735 | if (rdev->mode_info.mode_config_initialized) { |
867 | radeon_hpd_fini(rdev); |
736 | drm_mode_config_cleanup(rdev->ddev); |
868 | drm_mode_config_cleanup(rdev->ddev); |
737 | rdev->mode_info.mode_config_initialized = false; |
869 | rdev->mode_info.mode_config_initialized = false; |
738 | } |
870 | } |
Line 751... | Line 883... | ||
751 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
883 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
752 | radeon_encoder = to_radeon_encoder(encoder); |
884 | radeon_encoder = to_radeon_encoder(encoder); |
753 | if (encoder->crtc != crtc) |
885 | if (encoder->crtc != crtc) |
754 | continue; |
886 | continue; |
755 | if (first) { |
887 | if (first) { |
- | 888 | /* set scaling */ |
|
- | 889 | if (radeon_encoder->rmx_type == RMX_OFF) |
|
- | 890 | radeon_crtc->rmx_type = RMX_OFF; |
|
- | 891 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
|
- | 892 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
|
756 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
893 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
- | 894 | else |
|
- | 895 | radeon_crtc->rmx_type = RMX_OFF; |
|
- | 896 | /* copy native mode */ |
|
757 | memcpy(&radeon_crtc->native_mode, |
897 | memcpy(&radeon_crtc->native_mode, |
758 | &radeon_encoder->native_mode, |
898 | &radeon_encoder->native_mode, |
759 | sizeof(struct drm_display_mode)); |
899 | sizeof(struct drm_display_mode)); |
760 | first = false; |
900 | first = false; |
761 | } else { |
901 | } else { |