WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_device.c

 //#include
 #include
 #include
 #include
 #include
+#include
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "atom.h"
 int radeon_deep_color = 0;
 int radeon_use_pflipirq = 2;
 int irq_override = 0;
 int radeon_bapm = -1;
 int radeon_backlight = 0;
+int radeon_auxch = -1;
+int radeon_mst = 0;
 extern display_t *os_display;
 extern struct drm_device *main_device;
 extern videomode_t usermode;
+ *
  * Clear GPU surface registers (r1xx-r5xx).
  */
 void radeon_surface_init(struct radeon_device *rdev)
+{
-    /* FIXME: check this out */
+	/* FIXME: check this out */
-    if (rdev->family < CHIP_R600) {
+	if (rdev->family < CHIP_R600) {
-        int i;
+		int i;
 		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 			if (rdev->surface_regs[i].bo)
 				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 			else
-           radeon_clear_surface_reg(rdev, i);
+				radeon_clear_surface_reg(rdev, i);
+		}
 		/* enable surfaces */
 		WREG32(RADEON_SURFACE_CNTL, 0);
+	}
+}
 /*
+ *
  * Init CP scratch register driver information (r1xx-r5xx)
  */
 void radeon_scratch_init(struct radeon_device *rdev)
+{
-    int i;
+	int i;
-    /* FIXME: check this out */
+	/* FIXME: check this out */
-    if (rdev->family < CHIP_R300) {
+	if (rdev->family < CHIP_R300) {
-        rdev->scratch.num_reg = 5;
+		rdev->scratch.num_reg = 5;
-    } else {
+	} else {
-        rdev->scratch.num_reg = 7;
+		rdev->scratch.num_reg = 7;
+	}
 	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
-    for (i = 0; i < rdev->scratch.num_reg; i++) {
+	for (i = 0; i < rdev->scratch.num_reg; i++) {
-        rdev->scratch.free[i] = true;
+		rdev->scratch.free[i] = true;
 		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
+	}
+}
 /**
 				     &rdev->wb.wb_obj);
 		if (r) {
 			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 			return r;
+		}
-	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
+		r = radeon_bo_reserve(rdev->wb.wb_obj, false);
-	if (unlikely(r != 0)) {
+		if (unlikely(r != 0)) {
-		radeon_wb_fini(rdev);
+			radeon_wb_fini(rdev);
-		return r;
+			return r;
-	}
+		}
-	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
+		r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
-			  &rdev->wb.gpu_addr);
+				&rdev->wb.gpu_addr);
-	if (r) {
+		if (r) {
+			radeon_bo_unreserve(rdev->wb.wb_obj);
+			dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
+			radeon_wb_fini(rdev);
+			return r;
+		}
+		r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 		radeon_bo_unreserve(rdev->wb.wb_obj);
-		dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
-		radeon_wb_fini(rdev);
-		return r;
-	}
-	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
-	radeon_bo_unreserve(rdev->wb.wb_obj);
-	if (r) {
+		if (r) {
-		dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
+			dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
-		radeon_wb_fini(rdev);
+			radeon_wb_fini(rdev);
-		return r;
+			return r;
-	}
+		}
+	}
 	/* clear wb memory */
 	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 	/* disabled via module param */
 	if (radeon_no_wb == 1) {
 		rdev->wb.enabled = false;
 	} else {
 		if (rdev->flags & RADEON_IS_AGP) {
-		/* often unreliable on AGP */
+			/* often unreliable on AGP */
 			rdev->wb.enabled = false;
 		} else if (rdev->family < CHIP_R300) {
 			/* often unreliable on pre-r300 */
 			rdev->wb.enabled = false;
 		} else {
 			rdev->wb.enabled = true;
 			/* event_write fences are only available on r600+ */
 			if (rdev->family >= CHIP_R600) {
 				rdev->wb.use_event = true;
-	}
+			}
+		}
+	}
 	/* always use writeback/events on NI, APUs */
 	if (rdev->family >= CHIP_PALM) {
 		rdev->wb.enabled = true;
 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 		mc->real_vram_size = mc->aper_size;
 		mc->mc_vram_size = mc->aper_size;
-		}
+	}
 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 	if (limit && limit < mc->real_vram_size)
 		mc->real_vram_size = limit;
 	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 			mc->mc_vram_size >> 20, mc->vram_start,
 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+			}
 			if (rdev->num_crtc >= 6) {
 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
-			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+			}
 		if (reg & EVERGREEN_CRTC_MASTER_EN)
 			return true;
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 	fixed20_12 a;
 	u32 sclk = rdev->pm.current_sclk;
 	u32 mclk = rdev->pm.current_mclk;
 	/* sclk/mclk in Mhz */
-		a.full = dfixed_const(100);
+	a.full = dfixed_const(100);
-		rdev->pm.sclk.full = dfixed_const(sclk);
+	rdev->pm.sclk.full = dfixed_const(sclk);
-		rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
+	rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
-		rdev->pm.mclk.full = dfixed_const(mclk);
+	rdev->pm.mclk.full = dfixed_const(mclk);
-		rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
+	rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 	if (rdev->flags & RADEON_IS_IGP) {
 		a.full = dfixed_const(16);
  * Provides a PLL register accessor for the atom interpreter (r4xx+).
  * Returns the value of the PLL register.
  */
 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
+{
-    struct radeon_device *rdev = info->dev->dev_private;
+	struct radeon_device *rdev = info->dev->dev_private;
-    uint32_t r;
+	uint32_t r;
-    r = rdev->pll_rreg(rdev, reg);
+	r = rdev->pll_rreg(rdev, reg);
-    return r;
+	return r;
+}
 /**
+ *
  * Provides a PLL register accessor for the atom interpreter (r4xx+).
  */
 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
-    struct radeon_device *rdev = info->dev->dev_private;
+	struct radeon_device *rdev = info->dev->dev_private;
-    rdev->pll_wreg(rdev, reg, val);
+	rdev->pll_wreg(rdev, reg, val);
+}
 /**
  * Provides an MC register accessor for the atom interpreter (r4xx+).
  * Returns the value of the MC register.
  */
 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
+{
-    struct radeon_device *rdev = info->dev->dev_private;
+	struct radeon_device *rdev = info->dev->dev_private;
-    uint32_t r;
+	uint32_t r;
-    r = rdev->mc_rreg(rdev, reg);
+	r = rdev->mc_rreg(rdev, reg);
-    return r;
+	return r;
+}
 /**
+ *
  * Provides a MC register accessor for the atom interpreter (r4xx+).
  */
 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
-    struct radeon_device *rdev = info->dev->dev_private;
+	struct radeon_device *rdev = info->dev->dev_private;
-    rdev->mc_wreg(rdev, reg, val);
+	rdev->mc_wreg(rdev, reg, val);
+}
 /**
+ *
  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
  */
 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
-    struct radeon_device *rdev = info->dev->dev_private;
+	struct radeon_device *rdev = info->dev->dev_private;
-    WREG32(reg*4, val);
+	WREG32(reg*4, val);
+}
 /**
  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
  * Returns the value of the MMIO register.
  */
 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
+{
-    struct radeon_device *rdev = info->dev->dev_private;
+	struct radeon_device *rdev = info->dev->dev_private;
-    uint32_t r;
+	uint32_t r;
-    r = RREG32(reg*4);
+	r = RREG32(reg*4);
-    return r;
+	return r;
+}
 /**
 		return -ENOMEM;
+	}
 	mutex_init(&rdev->mode_info.atom_context->mutex);
 	mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
-    radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
+	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
-    return 0;
+	return 0;
+}
 /**
+{
 	return (arg & (arg - 1)) == 0;
+}
+/**
+ * Determine a sensible default GART size according to ASIC family.
+ *
+ * @family ASIC family name
+ */
+static int radeon_gart_size_auto(enum radeon_family family)
+{
+	/* default to a larger gart size on newer asics */
+	if (family >= CHIP_TAHITI)
+		return 2048;
+	else if (family >= CHIP_RV770)
+		return 1024;
+	else
+		return 512;
+}
 /**
  * radeon_check_arguments - validate module params
+ *
  * @rdev: radeon_device pointer
+ *
 				radeon_vram_limit);
 		radeon_vram_limit = 0;
+	}
 	if (radeon_gart_size == -1) {
-		/* default to a larger gart size on newer asics */
-		if (rdev->family >= CHIP_RV770)
-			radeon_gart_size = 1024;
-		else
-			radeon_gart_size = 512;
+		radeon_gart_size = radeon_gart_size_auto(rdev->family);
+	}
 	/* gtt size must be power of two and greater or equal to 32M */
 	if (radeon_gart_size < 32) {
 		dev_warn(rdev->dev, "gart size (%d) too small\n",
-				radeon_gart_size);
-		if (rdev->family >= CHIP_RV770)
-			radeon_gart_size = 1024;
-		else
+				radeon_gart_size);
-		radeon_gart_size = 512;
+		radeon_gart_size = radeon_gart_size_auto(rdev->family);
 	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
 		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
-				radeon_gart_size);
-		if (rdev->family >= CHIP_RV770)
-			radeon_gart_size = 1024;
-		else
+				radeon_gart_size);
-		radeon_gart_size = 512;
+		radeon_gart_size = radeon_gart_size_auto(rdev->family);
+	}
 	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
  * Initializes the driver info and hw (all asics).
  * Returns 0 for success or an error on failure.
  * Called at driver startup.
  */
 int radeon_device_init(struct radeon_device *rdev,
-               struct drm_device *ddev,
+		       struct drm_device *ddev,
-               struct pci_dev *pdev,
+		       struct pci_dev *pdev,
-               uint32_t flags)
+		       uint32_t flags)
+{
 	int r, i;
 	int dma_bits;
 	bool runtime = false;
-    rdev->shutdown = false;
+	rdev->shutdown = false;
 	rdev->dev = &pdev->dev;
-    rdev->ddev = ddev;
+	rdev->ddev = ddev;
-    rdev->pdev = pdev;
+	rdev->pdev = pdev;
-    rdev->flags = flags;
+	rdev->flags = flags;
-    rdev->family = flags & RADEON_FAMILY_MASK;
+	rdev->family = flags & RADEON_FAMILY_MASK;
-    rdev->is_atom_bios = false;
+	rdev->is_atom_bios = false;
-    rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
+	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 	rdev->mc.gtt_size = 512 * 1024 * 1024;
 	rdev->accel_working = false;
 	/* set up ring ids */
 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
 	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
 		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
 		pdev->subsystem_vendor, pdev->subsystem_device);
-    /* mutex initialization are all done here so we
+	/* mutex initialization are all done here so we
-     * can recall function without having locking issues */
+	 * can recall function without having locking issues */
 	mutex_init(&rdev->ring_lock);
 	mutex_init(&rdev->dc_hw_i2c_mutex);
 	atomic_set(&rdev->ih.lock, 0);
 		rdev->flags &= ~RADEON_IS_AGP;
+	}
 	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 		radeon_agp_disable(rdev);
+	}
 	/* Set the internal MC address mask
 	 * This is the max address of the GPU's
 	    (rdev->family <= CHIP_RS740))
 		rdev->need_dma32 = true;
 	dma_bits = rdev->need_dma32 ? 32 : 40;
 	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
-    if (r) {
+	if (r) {
 		rdev->need_dma32 = true;
 		dma_bits = 32;
-        printk(KERN_WARNING "radeon: No suitable DMA available.\n");
+		printk(KERN_WARNING "radeon: No suitable DMA available.\n");
-    }
+	}
-    /* Registers mapping */
+	/* Registers mapping */
-    /* TODO: block userspace mapping of io register */
+	/* TODO: block userspace mapping of io register */
 	spin_lock_init(&rdev->mmio_idx_lock);
 	spin_lock_init(&rdev->smc_idx_lock);
 	spin_lock_init(&rdev->pll_idx_lock);
 	spin_lock_init(&rdev->end_idx_lock);
 	if (rdev->family >= CHIP_BONAIRE) {
 		rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
 		rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
 	} else {
-    rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
+		rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
-    rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
+		rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
+	}
 	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
-    if (rdev->rmmio == NULL) {
+	if (rdev->rmmio == NULL) {
-        return -ENOMEM;
+		return -ENOMEM;
-    }
+	}
-    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
+	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
-    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
+	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 	/* doorbell bar mapping */
 	if (rdev->family >= CHIP_BONAIRE)
 	if (rdev->flags & RADEON_IS_PX)
 		runtime = true;
 	r = radeon_init(rdev);
 	if (r)
-        return r;
+		goto failed;
 		radeon_asic_reset(rdev);
 		radeon_fini(rdev);
 		radeon_agp_disable(rdev);
 		r = radeon_init(rdev);
 		if (r)
-		return r;
+			goto failed;
+	}
 //   r = radeon_ib_ring_tests(rdev);
 //   if (r)
 		if (rdev->accel_working)
 			radeon_test_syncing(rdev);
 		else
 			DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
+	}
-   if (radeon_benchmarking) {
+	if (radeon_benchmarking) {
 		if (rdev->accel_working)
-		radeon_benchmark(rdev, radeon_benchmarking);
+			radeon_benchmark(rdev, radeon_benchmarking);
 		else
 			DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
-    }
+	}
 	return 0;
+failed:
+	return r;
+}
 /**
  * radeon_gpu_reset - reset the asic
 static struct pci_device_id pciidlist[] = {
     radeon_PCI_IDS
+};
+u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
+int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
+void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
+int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
+				    int *max_error,
+				    struct timeval *vblank_time,
-};
+				    unsigned flags);
 void radeon_gem_object_free(struct drm_gem_object *obj);
 void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
 int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
 //    .open = radeon_driver_open_kms,
 //    .preclose = radeon_driver_preclose_kms,
 //    .postclose = radeon_driver_postclose_kms,
 //    .lastclose = radeon_driver_lastclose_kms,
 //    .unload = radeon_driver_unload_kms,
-//    .get_vblank_counter = radeon_get_vblank_counter_kms,
+    .get_vblank_counter = radeon_get_vblank_counter_kms,
-//    .enable_vblank = radeon_enable_vblank_kms,
+    .enable_vblank = radeon_enable_vblank_kms,
-//    .disable_vblank = radeon_disable_vblank_kms,
+    .disable_vblank = radeon_disable_vblank_kms,
-//    .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
+    .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
-//    .get_scanout_position = radeon_get_crtc_scanoutpos,
+    .get_scanout_position = radeon_get_crtc_scanoutpos,
 #if defined(CONFIG_DEBUG_FS)
     .debugfs_init = radeon_debugfs_init,
     .debugfs_cleanup = radeon_debugfs_cleanup,
 #endif
     .irq_preinstall = radeon_driver_irq_preinstall_kms,
     .irq_postinstall = radeon_driver_irq_postinstall_kms,
     .irq_uninstall = radeon_driver_irq_uninstall_kms,
     .irq_handler = radeon_driver_irq_handler_kms,
 //    .ioctls = radeon_ioctls_kms,
-//    .gem_free_object = radeon_gem_object_free,
+    .gem_free_object = radeon_gem_object_free,
 //    .gem_open_object = radeon_gem_object_open,
 //    .gem_close_object = radeon_gem_object_close,
 //    .dumb_create = radeon_mode_dumb_create,
 //    .dumb_map_offset = radeon_mode_dumb_mmap,
 //    .dumb_destroy = drm_gem_dumb_destroy,

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_device.c – Rev 5346 → 6104