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Rev 3192 | Rev 3764 | ||
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Line 57... | Line 57... | ||
57 | int radeon_audio = 1; |
57 | int radeon_audio = 1; |
58 | int radeon_hw_i2c = 0; |
58 | int radeon_hw_i2c = 0; |
59 | int radeon_pcie_gen2 = 0; |
59 | int radeon_pcie_gen2 = 0; |
60 | int radeon_disp_priority = 0; |
60 | int radeon_disp_priority = 0; |
61 | int radeon_lockup_timeout = 10000; |
61 | int radeon_lockup_timeout = 10000; |
62 | - | ||
- | 62 | int radeon_fastfb = 0; |
|
Line 63... | Line 63... | ||
63 | 63 | ||
Line 64... | Line 64... | ||
64 | int irq_override = 0; |
64 | int irq_override = 0; |
Line 141... | Line 141... | ||
141 | "CAYMAN", |
141 | "CAYMAN", |
142 | "ARUBA", |
142 | "ARUBA", |
143 | "TAHITI", |
143 | "TAHITI", |
144 | "PITCAIRN", |
144 | "PITCAIRN", |
145 | "VERDE", |
145 | "VERDE", |
- | 146 | "OLAND", |
|
- | 147 | "HAINAN", |
|
146 | "LAST", |
148 | "LAST", |
147 | }; |
149 | }; |
Line 148... | Line 150... | ||
148 | 150 | ||
- | 151 | /** |
|
- | 152 | * radeon_program_register_sequence - program an array of registers. |
|
- | 153 | * |
|
- | 154 | * @rdev: radeon_device pointer |
|
- | 155 | * @registers: pointer to the register array |
|
- | 156 | * @array_size: size of the register array |
|
- | 157 | * |
|
- | 158 | * Programs an array or registers with and and or masks. |
|
- | 159 | * This is a helper for setting golden registers. |
|
- | 160 | */ |
|
- | 161 | void radeon_program_register_sequence(struct radeon_device *rdev, |
|
- | 162 | const u32 *registers, |
|
- | 163 | const u32 array_size) |
|
- | 164 | { |
|
- | 165 | u32 tmp, reg, and_mask, or_mask; |
|
- | 166 | int i; |
|
- | 167 | ||
- | 168 | if (array_size % 3) |
|
- | 169 | return; |
|
- | 170 | ||
- | 171 | for (i = 0; i < array_size; i +=3) { |
|
- | 172 | reg = registers[i + 0]; |
|
- | 173 | and_mask = registers[i + 1]; |
|
- | 174 | or_mask = registers[i + 2]; |
|
- | 175 | ||
- | 176 | if (and_mask == 0xffffffff) { |
|
- | 177 | tmp = or_mask; |
|
- | 178 | } else { |
|
- | 179 | tmp = RREG32(reg); |
|
- | 180 | tmp &= ~and_mask; |
|
- | 181 | tmp |= or_mask; |
|
- | 182 | } |
|
- | 183 | WREG32(reg, tmp); |
|
- | 184 | } |
|
- | 185 | } |
|
- | 186 | ||
149 | /** |
187 | /** |
150 | * radeon_surface_init - Clear GPU surface registers. |
188 | * radeon_surface_init - Clear GPU surface registers. |
151 | * |
189 | * |
152 | * @rdev: radeon_device pointer |
190 | * @rdev: radeon_device pointer |
153 | * |
191 | * |
Line 251... | Line 289... | ||
251 | * |
289 | * |
252 | * Disables Writeback (all asics). Used for suspend. |
290 | * Disables Writeback (all asics). Used for suspend. |
253 | */ |
291 | */ |
254 | void radeon_wb_disable(struct radeon_device *rdev) |
292 | void radeon_wb_disable(struct radeon_device *rdev) |
255 | { |
293 | { |
256 | int r; |
- | |
257 | - | ||
258 | if (rdev->wb.wb_obj) { |
- | |
259 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
- | |
260 | if (unlikely(r != 0)) |
- | |
261 | return; |
- | |
262 | radeon_bo_kunmap(rdev->wb.wb_obj); |
- | |
263 | radeon_bo_unpin(rdev->wb.wb_obj); |
- | |
264 | radeon_bo_unreserve(rdev->wb.wb_obj); |
- | |
265 | } |
- | |
266 | rdev->wb.enabled = false; |
294 | rdev->wb.enabled = false; |
267 | } |
295 | } |
Line 268... | Line 296... | ||
268 | 296 | ||
269 | /** |
297 | /** |
Line 302... | Line 330... | ||
302 | RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); |
330 | RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); |
303 | if (r) { |
331 | if (r) { |
304 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
332 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
305 | return r; |
333 | return r; |
306 | } |
334 | } |
307 | } |
- | |
308 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
335 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
309 | if (unlikely(r != 0)) { |
336 | if (unlikely(r != 0)) { |
310 | radeon_wb_fini(rdev); |
337 | radeon_wb_fini(rdev); |
311 | return r; |
338 | return r; |
312 | } |
339 | } |
Line 323... | Line 350... | ||
323 | if (r) { |
350 | if (r) { |
324 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
351 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
325 | radeon_wb_fini(rdev); |
352 | radeon_wb_fini(rdev); |
326 | return r; |
353 | return r; |
327 | } |
354 | } |
- | 355 | } |
|
Line 328... | Line 356... | ||
328 | 356 | ||
329 | /* clear wb memory */ |
357 | /* clear wb memory */ |
330 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); |
358 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); |
331 | /* disable event_write fences */ |
359 | /* disable event_write fences */ |
Line 403... | Line 431... | ||
403 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
431 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
404 | { |
432 | { |
405 | uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
433 | uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
Line 406... | Line 434... | ||
406 | 434 | ||
407 | mc->vram_start = base; |
435 | mc->vram_start = base; |
408 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
436 | if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { |
409 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
437 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
410 | mc->real_vram_size = mc->aper_size; |
438 | mc->real_vram_size = mc->aper_size; |
411 | mc->mc_vram_size = mc->aper_size; |
439 | mc->mc_vram_size = mc->aper_size; |
412 | } |
440 | } |
Line 438... | Line 466... | ||
438 | */ |
466 | */ |
439 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
467 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
440 | { |
468 | { |
441 | u64 size_af, size_bf; |
469 | u64 size_af, size_bf; |
Line 442... | Line 470... | ||
442 | 470 | ||
443 | size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
471 | size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
444 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
472 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
445 | if (size_bf > size_af) { |
473 | if (size_bf > size_af) { |
446 | if (mc->gtt_size > size_bf) { |
474 | if (mc->gtt_size > size_bf) { |
447 | dev_warn(rdev->dev, "limiting GTT\n"); |
475 | dev_warn(rdev->dev, "limiting GTT\n"); |
Line 474... | Line 502... | ||
474 | */ |
502 | */ |
475 | bool radeon_card_posted(struct radeon_device *rdev) |
503 | bool radeon_card_posted(struct radeon_device *rdev) |
476 | { |
504 | { |
477 | uint32_t reg; |
505 | uint32_t reg; |
Line -... | Line 506... | ||
- | 506 | ||
- | 507 | if (ASIC_IS_NODCE(rdev)) |
|
- | 508 | goto check_memsize; |
|
478 | 509 | ||
479 | /* first check CRTCs */ |
510 | /* first check CRTCs */ |
480 | if (ASIC_IS_DCE41(rdev)) { |
511 | if (ASIC_IS_DCE4(rdev)) { |
481 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
512 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
482 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
- | |
483 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
- | |
484 | return true; |
513 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
485 | } else if (ASIC_IS_DCE4(rdev)) { |
514 | if (rdev->num_crtc >= 4) { |
486 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
- | |
487 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
515 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
- | 516 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); |
|
488 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
517 | } |
489 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
518 | if (rdev->num_crtc >= 6) { |
490 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
519 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
- | 520 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
|
491 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
521 | } |
492 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
522 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
493 | return true; |
523 | return true; |
494 | } else if (ASIC_IS_AVIVO(rdev)) { |
524 | } else if (ASIC_IS_AVIVO(rdev)) { |
495 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
525 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
Line 503... | Line 533... | ||
503 | if (reg & RADEON_CRTC_EN) { |
533 | if (reg & RADEON_CRTC_EN) { |
504 | return true; |
534 | return true; |
505 | } |
535 | } |
506 | } |
536 | } |
Line -... | Line 537... | ||
- | 537 | ||
507 | 538 | check_memsize: |
|
508 | /* then check MEM_SIZE, in case the crtcs are off */ |
539 | /* then check MEM_SIZE, in case the crtcs are off */ |
509 | if (rdev->family >= CHIP_R600) |
540 | if (rdev->family >= CHIP_R600) |
510 | reg = RREG32(R600_CONFIG_MEMSIZE); |
541 | reg = RREG32(R600_CONFIG_MEMSIZE); |
511 | else |
542 | else |
Line 795... | Line 826... | ||
795 | atom_card_info->mc_write = cail_mc_write; |
826 | atom_card_info->mc_write = cail_mc_write; |
796 | atom_card_info->pll_read = cail_pll_read; |
827 | atom_card_info->pll_read = cail_pll_read; |
797 | atom_card_info->pll_write = cail_pll_write; |
828 | atom_card_info->pll_write = cail_pll_write; |
Line 798... | Line 829... | ||
798 | 829 | ||
- | 830 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
|
- | 831 | if (!rdev->mode_info.atom_context) { |
|
- | 832 | radeon_atombios_fini(rdev); |
|
- | 833 | return -ENOMEM; |
|
- | 834 | } |
|
799 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
835 | |
800 | mutex_init(&rdev->mode_info.atom_context->mutex); |
836 | mutex_init(&rdev->mode_info.atom_context->mutex); |
801 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
837 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
802 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
838 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
803 | return 0; |
839 | return 0; |
Line 814... | Line 850... | ||
814 | */ |
850 | */ |
815 | void radeon_atombios_fini(struct radeon_device *rdev) |
851 | void radeon_atombios_fini(struct radeon_device *rdev) |
816 | { |
852 | { |
817 | if (rdev->mode_info.atom_context) { |
853 | if (rdev->mode_info.atom_context) { |
818 | kfree(rdev->mode_info.atom_context->scratch); |
854 | kfree(rdev->mode_info.atom_context->scratch); |
819 | kfree(rdev->mode_info.atom_context); |
- | |
820 | } |
855 | } |
- | 856 | kfree(rdev->mode_info.atom_context); |
|
- | 857 | rdev->mode_info.atom_context = NULL; |
|
821 | kfree(rdev->mode_info.atom_card_info); |
858 | kfree(rdev->mode_info.atom_card_info); |
- | 859 | rdev->mode_info.atom_card_info = NULL; |
|
822 | } |
860 | } |
Line 823... | Line 861... | ||
823 | 861 | ||
824 | /* COMBIOS */ |
862 | /* COMBIOS */ |
825 | /* |
863 | /* |
Line 968... | Line 1006... | ||
968 | mutex_init(&rdev->dc_hw_i2c_mutex); |
1006 | mutex_init(&rdev->dc_hw_i2c_mutex); |
969 | atomic_set(&rdev->ih.lock, 0); |
1007 | atomic_set(&rdev->ih.lock, 0); |
970 | mutex_init(&rdev->gem.mutex); |
1008 | mutex_init(&rdev->gem.mutex); |
971 | mutex_init(&rdev->pm.mutex); |
1009 | mutex_init(&rdev->pm.mutex); |
972 | mutex_init(&rdev->gpu_clock_mutex); |
1010 | mutex_init(&rdev->gpu_clock_mutex); |
973 | init_rwsem(&rdev->pm.mclk_lock); |
1011 | // init_rwsem(&rdev->pm.mclk_lock); |
974 | init_rwsem(&rdev->exclusive_lock); |
1012 | // init_rwsem(&rdev->exclusive_lock); |
975 | init_waitqueue_head(&rdev->irq.vblank_queue); |
1013 | init_waitqueue_head(&rdev->irq.vblank_queue); |
976 | r = radeon_gem_init(rdev); |
1014 | r = radeon_gem_init(rdev); |
977 | if (r) |
1015 | if (r) |
978 | return r; |
1016 | return r; |
979 | /* initialize vm here */ |
1017 | /* initialize vm here */ |
Line 1001... | Line 1039... | ||
1001 | 1039 | ||
1002 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1040 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1003 | radeon_agp_disable(rdev); |
1041 | radeon_agp_disable(rdev); |
Line -... | Line 1042... | ||
- | 1042 | } |
|
- | 1043 | ||
- | 1044 | /* Set the internal MC address mask |
|
- | 1045 | * This is the max address of the GPU's |
|
- | 1046 | * internal address space. |
|
- | 1047 | */ |
|
- | 1048 | if (rdev->family >= CHIP_CAYMAN) |
|
- | 1049 | rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ |
|
- | 1050 | else if (rdev->family >= CHIP_CEDAR) |
|
- | 1051 | rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ |
|
- | 1052 | else |
|
1004 | } |
1053 | rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ |
1005 | 1054 | ||
1006 | /* set DMA mask + need_dma32 flags. |
1055 | /* set DMA mask + need_dma32 flags. |
1007 | * PCIE - can handle 40-bits. |
1056 | * PCIE - can handle 40-bits. |
1008 | * IGP - can handle 40-bits |
1057 | * IGP - can handle 40-bits |
Line 1119... | Line 1168... | ||
1119 | dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
1168 | dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
1120 | radeon_resume(rdev); |
1169 | radeon_resume(rdev); |
1121 | } |
1170 | } |
Line 1122... | Line 1171... | ||
1122 | 1171 | ||
1123 | radeon_restore_bios_scratch_regs(rdev); |
- | |
Line 1124... | Line 1172... | ||
1124 | drm_helper_resume_force_mode(rdev->ddev); |
1172 | radeon_restore_bios_scratch_regs(rdev); |
1125 | 1173 | ||
1126 | if (!r) { |
1174 | if (!r) { |
1127 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
1175 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
Line 1163... | Line 1211... | ||
1163 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
1211 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
1164 | { |
1212 | { |
1165 | struct radeon_device *rdev; |
1213 | struct radeon_device *rdev; |
1166 | int r; |
1214 | int r; |
Line 1167... | Line -... | ||
1167 | - | ||
Line 1168... | Line 1215... | ||
1168 | ENTER(); |
1215 | |
1169 | 1216 | ||
1170 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1217 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1171 | if (rdev == NULL) { |
1218 | if (rdev == NULL) { |
Line 1214... | Line 1261... | ||
1214 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
1261 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
1215 | { |
1262 | { |
1216 | static struct drm_device *dev; |
1263 | static struct drm_device *dev; |
1217 | int ret; |
1264 | int ret; |
Line 1218... | Line -... | ||
1218 | - | ||
1219 | ENTER(); |
- | |
1220 | 1265 | ||
1221 | dev = kzalloc(sizeof(*dev), 0); |
1266 | dev = kzalloc(sizeof(*dev), 0); |
1222 | if (!dev) |
1267 | if (!dev) |
Line 1223... | Line 1268... | ||
1223 | return -ENOMEM; |
1268 | return -ENOMEM; |
Line 1257... | Line 1302... | ||
1257 | init_display_kms(dev->dev_private, &usermode); |
1302 | init_display_kms(dev->dev_private, &usermode); |
1258 | else |
1303 | else |
1259 | init_display(dev->dev_private, &usermode); |
1304 | init_display(dev->dev_private, &usermode); |
Line 1260... | Line -... | ||
1260 | - | ||
1261 | - | ||
1262 | LEAVE(); |
1305 | |
Line 1263... | Line 1306... | ||
1263 | 1306 | ||
1264 | return 0; |
1307 | return 0; |
1265 | 1308 | ||
Line 1331... | Line 1374... | ||
1331 | #define CURRENT_API 0x0200 /* 2.00 */ |
1374 | #define CURRENT_API 0x0200 /* 2.00 */ |
1332 | #define COMPATIBLE_API 0x0100 /* 1.00 */ |
1375 | #define COMPATIBLE_API 0x0100 /* 1.00 */ |
Line 1333... | Line 1376... | ||
1333 | 1376 | ||
Line 1334... | Line 1377... | ||
1334 | #define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
1377 | #define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
1335 | 1378 | ||
1336 | #define SRV_GETVERSION 0 |
1379 | #define SRV_GETVERSION 0 |
1337 | #define SRV_ENUM_MODES 1 |
1380 | #define SRV_ENUM_MODES 1 |
Line 1338... | Line 1381... | ||
1338 | #define SRV_SET_MODE 2 |
1381 | #define SRV_SET_MODE 2 |
1339 | #define SRV_GET_CAPS 3 |
1382 | #define SRV_GET_CAPS 3 |
1340 | 1383 | ||
Line 1390... | Line 1433... | ||
1390 | inp, io->inp_size); |
1433 | inp, io->inp_size); |
1391 | check_input(sizeof(videomode_t)); |
1434 | check_input(sizeof(videomode_t)); |
1392 | if( radeon_modeset ) |
1435 | if( radeon_modeset ) |
1393 | retval = set_user_mode((videomode_t*)inp); |
1436 | retval = set_user_mode((videomode_t*)inp); |
1394 | break; |
1437 | break; |
1395 | 1438 | /* |
|
1396 | case SRV_GET_CAPS: |
1439 | case SRV_GET_CAPS: |
1397 | retval = get_driver_caps((hwcaps_t*)inp); |
1440 | retval = get_driver_caps((hwcaps_t*)inp); |
1398 | break; |
1441 | break; |
Line 1399... | Line 1442... | ||
1399 | 1442 | ||
Line 1407... | Line 1450... | ||
1407 | break; |
1450 | break; |
Line 1408... | Line 1451... | ||
1408 | 1451 | ||
1409 | case SRV_BLIT_BITMAP: |
1452 | case SRV_BLIT_BITMAP: |
1410 | srv_blit_bitmap( inp[0], inp[1], inp[2], |
1453 | srv_blit_bitmap( inp[0], inp[1], inp[2], |
1411 | inp[3], inp[4], inp[5], inp[6]); |
1454 | inp[3], inp[4], inp[5], inp[6]); |
1412 | 1455 | */ |
|
Line 1413... | Line 1456... | ||
1413 | }; |
1456 | }; |
1414 | 1457 | ||
Line 1436... | Line 1479... | ||
1436 | if( cmdline && *cmdline ) |
1479 | if( cmdline && *cmdline ) |
1437 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
1480 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
Line 1438... | Line 1481... | ||
1438 | 1481 | ||
1439 | if(!dbg_open(log)) |
1482 | if(!dbg_open(log)) |
1440 | { |
1483 | { |
Line 1441... | Line 1484... | ||
1441 | strcpy(log, "/TMP1/1/atikms.log"); |
1484 | strcpy(log, "/TMP1/1/ati.log"); |
1442 | 1485 | ||
1443 | if(!dbg_open(log)) |
1486 | if(!dbg_open(log)) |
1444 | { |
1487 | { |
1445 | printf("Can't open %s\nExit\n", log); |
1488 | printf("Can't open %s\nExit\n", log); |
1446 | return 0; |
1489 | return 0; |
1447 | }; |
1490 | }; |
- | 1491 | } |
|
- | 1492 | dbgprintf("Radeon v3.10 preview-1 cmdline %s\n", cmdline); |
|
Line 1448... | Line 1493... | ||
1448 | } |
1493 | |
Line 1449... | Line 1494... | ||
1449 | dbgprintf("Radeon RC13 cmdline %s\n", cmdline); |
1494 | cpu_detect(); |
Line 1459... | Line 1504... | ||
1459 | }; |
1504 | }; |
Line 1460... | Line 1505... | ||
1460 | 1505 | ||
1461 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
1506 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
Line -... | Line 1507... | ||
- | 1507 | device.pci_dev.device); |
|
- | 1508 | ||
1462 | device.pci_dev.device); |
1509 | drm_global_init(); |
Line 1463... | Line 1510... | ||
1463 | 1510 | ||
Line 1464... | Line 1511... | ||
1464 | err = drm_get_dev(&device.pci_dev, ent); |
1511 | err = drm_get_dev(&device.pci_dev, ent); |
Line 1494... | Line 1541... | ||
1494 | ret = 1; |
1541 | ret = 1; |
1495 | } |
1542 | } |
1496 | return ret; |
1543 | return ret; |
1497 | } |
1544 | }><>>><>><>>>>>=>><>><>>><>>>=>><>>>>>>>>> |
Line 1498... | Line -... | ||
1498 | - | ||
1499 | unsigned int hweight32(unsigned int w) |
- | |
1500 | { |
- | |
1501 | unsigned int res = w - ((w >> 1) & 0x55555555); |
- | |
1502 | res = (res & 0x33333333) + ((res >> 2) & 0x33333333); |
- | |
1503 | res = (res + (res >> 4)) & 0x0F0F0F0F; |
- | |
1504 | res = res + (res >> 8); |
- | |
1505 | return (res + (res >> 16)) & 0x000000FF; |
- | |
1506 | }><>>><>><>>>>>=>><>><>>><>>>=>><>>>>>>>> |
- |